1 //===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
23 include "XCoreRegisterInfo.td"
24 include "XCoreInstrInfo.td"
25 include "XCoreCallingConv.td"
27 def XCoreInstrInfo : InstrInfo {
28 let TSFlagsFields = [];
29 let TSFlagsShifts = [];
32 //===----------------------------------------------------------------------===//
33 // XCore Subtarget features.
34 //===----------------------------------------------------------------------===//
37 : SubtargetFeature<"xs1b", "IsXS1B", "true",
38 "Enable XS1B instructions">;
40 //===----------------------------------------------------------------------===//
41 // XCore processors supported.
42 //===----------------------------------------------------------------------===//
44 class Proc<string Name, list<SubtargetFeature> Features>
45 : Processor<Name, NoItineraries, Features>;
47 def : Proc<"generic", [FeatureXS1B]>;
48 def : Proc<"xs1b-generic", [FeatureXS1B]>;
50 //===----------------------------------------------------------------------===//
51 // Declare the target which we are implementing
52 //===----------------------------------------------------------------------===//
55 // Pull in Instruction Info:
56 let InstructionSet = XCoreInstrInfo;