lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 typedef MCDisassembler::DecodeStatus DecodeStatus;
  27
  28 namespace {
  29
  30 /// \brief A disassembler class for XCore.
  31 class XCoreDisassembler : public MCDisassembler {
  32   const MCRegisterInfo *RegInfo;
  33 public:
  34   XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
  35     MCDisassembler(STI), RegInfo(Info) {}
  36
  37   /// \brief See MCDisassembler.
  38   virtual DecodeStatus getInstruction(MCInst &instr,
  39                                       uint64_t &size,
  40                                       const MemoryObject &region,
  41                                       uint64_t address,
  42                                       raw_ostream &vStream,
  43                                       raw_ostream &cStream) const;
  44
  45   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  46 };
  47 }
  48
  49 static bool readInstruction16(const MemoryObject &region,
  50                               uint64_t address,
  51                               uint64_t &size,
  52                               uint16_t &insn) {
  53   uint8_t Bytes[4];
  54
  55   // We want to read exactly 2 Bytes of data.
  56   if (region.readBytes(address, 2, Bytes, NULL) == -1) {
  57     size = 0;
  58     return false;
  59   }
  60   // Encoded as a little-endian 16-bit word in the stream.
  61   insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
  62   return true;
  63 }
  64
  65 static bool readInstruction32(const MemoryObject &region,
  66                               uint64_t address,
  67                               uint64_t &size,
  68                               uint32_t &insn) {
  69   uint8_t Bytes[4];
  70
  71   // We want to read exactly 4 Bytes of data.
  72   if (region.readBytes(address, 4, Bytes, NULL) == -1) {
  73     size = 0;
  74     return false;
  75   }
  76   // Encoded as a little-endian 32-bit word in the stream.
  77   insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
  78          (Bytes[3] << 24);
  79   return true;
  80 }
  81
  82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  83   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  84   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
  85 }
  86
  87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  88                                               unsigned RegNo,
  89                                               uint64_t Address,
  90                                               const void *Decoder);
  91
  92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  93                                       uint64_t Address, const void *Decoder);
  94
  95 static DecodeStatus Decode2RInstruction(MCInst &Inst,
  96                                         unsigned Insn,
  97                                         uint64_t Address,
  98                                         const void *Decoder);
  99
 100 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 101                                          unsigned Insn,
 102                                          uint64_t Address,
 103                                          const void *Decoder);
 104
 105 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 106                                               unsigned Insn,
 107                                               uint64_t Address,
 108                                               const void *Decoder);
 109
 110 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 111                                          unsigned Insn,
 112                                          uint64_t Address,
 113                                          const void *Decoder);
 114
 115 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 116                                              unsigned Insn,
 117                                              uint64_t Address,
 118                                              const void *Decoder);
 119
 120 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 121                                                    unsigned Insn,
 122                                                    uint64_t Address,
 123                                                    const void *Decoder);
 124
 125 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 126                                          unsigned Insn,
 127                                          uint64_t Address,
 128                                          const void *Decoder);
 129
 130 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 131                                           unsigned Insn,
 132                                           uint64_t Address,
 133                                           const void *Decoder);
 134
 135 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 136                                         unsigned Insn,
 137                                         uint64_t Address,
 138                                         const void *Decoder);
 139
 140 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 141                                           unsigned Insn,
 142                                           uint64_t Address,
 143                                           const void *Decoder);
 144
 145 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 146                                               unsigned Insn,
 147                                               uint64_t Address,
 148                                               const void *Decoder);
 149
 150 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
 151                                          unsigned Insn,
 152                                          uint64_t Address,
 153                                          const void *Decoder);
 154
 155 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
 156                                                unsigned Insn,
 157                                                uint64_t Address,
 158                                                const void *Decoder);
 159
 160 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
 161                                            unsigned Insn,
 162                                            uint64_t Address,
 163                                            const void *Decoder);
 164
 165 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
 166                                                unsigned Insn,
 167                                                uint64_t Address,
 168                                                const void *Decoder);
 169
 170 #include "XCoreGenDisassemblerTables.inc"
 171
 172 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 173                                               unsigned RegNo,
 174                                               uint64_t Address,
 175                                               const void *Decoder)
 176 {
 177   if (RegNo > 11)
 178     return MCDisassembler::Fail;
 179   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 180   Inst.addOperand(MCOperand::CreateReg(Reg));
 181   return MCDisassembler::Success;
 182 }
 183
 184 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 185                                       uint64_t Address, const void *Decoder) {
 186   if (Val > 11)
 187     return MCDisassembler::Fail;
 188   static unsigned Values[] = {
 189     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 190   };
 191   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 192   return MCDisassembler::Success;
 193 }
 194
 195 static DecodeStatus
 196 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 197   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 198   if (Combined < 27)
 199     return MCDisassembler::Fail;
 200   if (fieldFromInstruction(Insn, 5, 1)) {
 201     if (Combined == 31)
 202       return MCDisassembler::Fail;
 203     Combined += 5;
 204   }
 205   Combined -= 27;
 206   unsigned Op1High = Combined % 3;
 207   unsigned Op2High = Combined / 3;
 208   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 209   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 210   return MCDisassembler::Success;
 211 }
 212
 213 static DecodeStatus
 214 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 215                      unsigned &Op3) {
 216   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 217   if (Combined >= 27)
 218     return MCDisassembler::Fail;
 219
 220   unsigned Op1High = Combined % 3;
 221   unsigned Op2High = (Combined / 3) % 3;
 222   unsigned Op3High = Combined / 9;
 223   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 224   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 225   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 226   return MCDisassembler::Success;
 227 }
 228
 229 static DecodeStatus
 230 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 231                          const void *Decoder) {
 232   // Try and decode as a 3R instruction.
 233   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 234   switch (Opcode) {
 235   case 0x0:
 236     Inst.setOpcode(XCore::STW_2rus);
 237     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 238   case 0x1:
 239     Inst.setOpcode(XCore::LDW_2rus);
 240     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 241   case 0x2:
 242     Inst.setOpcode(XCore::ADD_3r);
 243     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 244   case 0x3:
 245     Inst.setOpcode(XCore::SUB_3r);
 246     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 247   case 0x4:
 248     Inst.setOpcode(XCore::SHL_3r);
 249     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 250   case 0x5:
 251     Inst.setOpcode(XCore::SHR_3r);
 252     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 253   case 0x6:
 254     Inst.setOpcode(XCore::EQ_3r);
 255     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 256   case 0x7:
 257     Inst.setOpcode(XCore::AND_3r);
 258     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 259   case 0x8:
 260     Inst.setOpcode(XCore::OR_3r);
 261     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 262   case 0x9:
 263     Inst.setOpcode(XCore::LDW_3r);
 264     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 265   case 0x10:
 266     Inst.setOpcode(XCore::LD16S_3r);
 267     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 268   case 0x11:
 269     Inst.setOpcode(XCore::LD8U_3r);
 270     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 271   case 0x12:
 272     Inst.setOpcode(XCore::ADD_2rus);
 273     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 274   case 0x13:
 275     Inst.setOpcode(XCore::SUB_2rus);
 276     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 277   case 0x14:
 278     Inst.setOpcode(XCore::SHL_2rus);
 279     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 280   case 0x15:
 281     Inst.setOpcode(XCore::SHR_2rus);
 282     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 283   case 0x16:
 284     Inst.setOpcode(XCore::EQ_2rus);
 285     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 286   case 0x18:
 287     Inst.setOpcode(XCore::LSS_3r);
 288     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 289   case 0x19:
 290     Inst.setOpcode(XCore::LSU_3r);
 291     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 292   }
 293   return MCDisassembler::Fail;
 294 }
 295
 296 static DecodeStatus
 297 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 298                     const void *Decoder) {
 299   unsigned Op1, Op2;
 300   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 301   if (S != MCDisassembler::Success)
 302     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 303
 304   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 305   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 306   return S;
 307 }
 308
 309 static DecodeStatus
 310 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 311                      const void *Decoder) {
 312   unsigned Op1, Op2;
 313   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 314   if (S != MCDisassembler::Success)
 315     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 316
 317   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 318   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 319   return S;
 320 }
 321
 322 static DecodeStatus
 323 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 324                           const void *Decoder) {
 325   unsigned Op1, Op2;
 326   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 327   if (S != MCDisassembler::Success)
 328     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 329
 330   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 331   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 332   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 333   return S;
 334 }
 335
 336 static DecodeStatus
 337 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 338                      const void *Decoder) {
 339   unsigned Op1, Op2;
 340   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 341   if (S != MCDisassembler::Success)
 342     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 343
 344   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 345   Inst.addOperand(MCOperand::CreateImm(Op2));
 346   return S;
 347 }
 348
 349 static DecodeStatus
 350 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 351                          const void *Decoder) {
 352   unsigned Op1, Op2;
 353   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 354   if (S != MCDisassembler::Success)
 355     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 356
 357   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 358   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 359   return S;
 360 }
 361
 362 static DecodeStatus
 363 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 364                                const void *Decoder) {
 365   unsigned Op1, Op2;
 366   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 367   if (S != MCDisassembler::Success)
 368     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 369
 370   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 371   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 372   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 373   return S;
 374 }
 375
 376 static DecodeStatus
 377 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 378                           const void *Decoder) {
 379   // Try and decode as a L3R / L2RUS instruction.
 380   unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
 381                     fieldFromInstruction(Insn, 27, 5) << 4;
 382   switch (Opcode) {
 383   case 0x0c:
 384     Inst.setOpcode(XCore::STW_3r);
 385     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 386   case 0x1c:
 387     Inst.setOpcode(XCore::XOR_l3r);
 388     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 389   case 0x2c:
 390     Inst.setOpcode(XCore::ASHR_l3r);
 391     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 392   case 0x3c:
 393     Inst.setOpcode(XCore::LDAWF_l3r);
 394     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 395   case 0x4c:
 396     Inst.setOpcode(XCore::LDAWB_l3r);
 397     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 398   case 0x5c:
 399     Inst.setOpcode(XCore::LDA16F_l3r);
 400     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 401   case 0x6c:
 402     Inst.setOpcode(XCore::LDA16B_l3r);
 403     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 404   case 0x7c:
 405     Inst.setOpcode(XCore::MUL_l3r);
 406     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 407   case 0x8c:
 408     Inst.setOpcode(XCore::DIVS_l3r);
 409     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 410   case 0x9c:
 411     Inst.setOpcode(XCore::DIVU_l3r);
 412     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 413   case 0x10c:
 414     Inst.setOpcode(XCore::ST16_l3r);
 415     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 416   case 0x11c:
 417     Inst.setOpcode(XCore::ST8_l3r);
 418     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 419   case 0x12c:
 420     Inst.setOpcode(XCore::ASHR_l2rus);
 421     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 422   case 0x13c:
 423     Inst.setOpcode(XCore::LDAWF_l2rus);
 424     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 425   case 0x14c:
 426     Inst.setOpcode(XCore::LDAWB_l2rus);
 427     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
 428   case 0x15c:
 429     Inst.setOpcode(XCore::CRC_l3r);
 430     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
 431   case 0x18c:
 432     Inst.setOpcode(XCore::REMS_l3r);
 433     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 434   case 0x19c:
 435     Inst.setOpcode(XCore::REMU_l3r);
 436     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
 437   }
 438   return MCDisassembler::Fail;
 439 }
 440
 441 static DecodeStatus
 442 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 443                                const void *Decoder) {
 444   unsigned Op1, Op2;
 445   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 446                                         Op1, Op2);
 447   if (S != MCDisassembler::Success)
 448     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 449
 450   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 451   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 452   return S;
 453 }
 454
 455 static DecodeStatus
 456 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 457                                const void *Decoder) {
 458   unsigned Op1, Op2;
 459   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 460                                         Op1, Op2);
 461   if (S != MCDisassembler::Success)
 462     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
 463
 464   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 465   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 466   return S;
 467 }
 468
 469 static DecodeStatus
 470 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 471                     const void *Decoder) {
 472   unsigned Op1, Op2, Op3;
 473   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 474   if (S == MCDisassembler::Success) {
 475     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 476     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 477     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 478   }
 479   return S;
 480 }
 481
 482 static DecodeStatus
 483 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 484                       const void *Decoder) {
 485   unsigned Op1, Op2, Op3;
 486   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 487   if (S == MCDisassembler::Success) {
 488     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 489     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 490     Inst.addOperand(MCOperand::CreateImm(Op3));
 491   }
 492   return S;
 493 }
 494
 495 static DecodeStatus
 496 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 497                       const void *Decoder) {
 498   unsigned Op1, Op2, Op3;
 499   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 500   if (S == MCDisassembler::Success) {
 501     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 502     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 503     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 504   }
 505   return S;
 506 }
 507
 508 static DecodeStatus
 509 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 510                      const void *Decoder) {
 511   unsigned Op1, Op2, Op3;
 512   DecodeStatus S =
 513     Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 514   if (S == MCDisassembler::Success) {
 515     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 516     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 517     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 518   }
 519   return S;
 520 }
 521
 522 static DecodeStatus
 523 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 524                            const void *Decoder) {
 525   unsigned Op1, Op2, Op3;
 526   DecodeStatus S =
 527   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 528   if (S == MCDisassembler::Success) {
 529     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 530     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 531     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 532     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 533   }
 534   return S;
 535 }
 536
 537 static DecodeStatus
 538 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 539                        const void *Decoder) {
 540   unsigned Op1, Op2, Op3;
 541   DecodeStatus S =
 542   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 543   if (S == MCDisassembler::Success) {
 544     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 545     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 546     Inst.addOperand(MCOperand::CreateImm(Op3));
 547   }
 548   return S;
 549 }
 550
 551 static DecodeStatus
 552 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 553                            const void *Decoder) {
 554   unsigned Op1, Op2, Op3;
 555   DecodeStatus S =
 556   Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
 557   if (S == MCDisassembler::Success) {
 558     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 559     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 560     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 561   }
 562   return S;
 563 }
 564
 565 MCDisassembler::DecodeStatus
 566 XCoreDisassembler::getInstruction(MCInst &instr,
 567                                   uint64_t &Size,
 568                                   const MemoryObject &Region,
 569                                   uint64_t Address,
 570                                   raw_ostream &vStream,
 571                                   raw_ostream &cStream) const {
 572   uint16_t insn16;
 573
 574   if (!readInstruction16(Region, Address, Size, insn16)) {
 575     return Fail;
 576   }
 577
 578   // Calling the auto-generated decoder function.
 579   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 580                                           Address, this, STI);
 581   if (Result != Fail) {
 582     Size = 2;
 583     return Result;
 584   }
 585
 586   uint32_t insn32;
 587
 588   if (!readInstruction32(Region, Address, Size, insn32)) {
 589     return Fail;
 590   }
 591
 592   // Calling the auto-generated decoder function.
 593   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 594   if (Result != Fail) {
 595     Size = 4;
 596     return Result;
 597   }
 598
 599   return Fail;
 600 }
 601
 602 namespace llvm {
 603   extern Target TheXCoreTarget;
 604 }
 605
 606 static MCDisassembler *createXCoreDisassembler(const Target &T,
 607                                                const MCSubtargetInfo &STI) {
 608   return new XCoreDisassembler(STI, T.createMCRegInfo(""));
 609 }
 610
 611 extern "C" void LLVMInitializeXCoreDisassembler() {
 612   // Register the disassembler.
 613   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 614                                          createXCoreDisassembler);
 615 }