lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

   1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 ///
  10 /// \file
  11 /// \brief This file is part of the XCore Disassembler.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "XCore.h"
  16 #include "XCoreRegisterInfo.h"
  17 #include "llvm/MC/MCDisassembler.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCSubtargetInfo.h"
  21 #include "llvm/Support/MemoryObject.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23
  24 using namespace llvm;
  25
  26 typedef MCDisassembler::DecodeStatus DecodeStatus;
  27
  28 namespace {
  29
  30 /// \brief A disassembler class for XCore.
  31 class XCoreDisassembler : public MCDisassembler {
  32   const MCRegisterInfo *RegInfo;
  33 public:
  34   XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
  35     MCDisassembler(STI), RegInfo(Info) {}
  36
  37   /// \brief See MCDisassembler.
  38   virtual DecodeStatus getInstruction(MCInst &instr,
  39                                       uint64_t &size,
  40                                       const MemoryObject &region,
  41                                       uint64_t address,
  42                                       raw_ostream &vStream,
  43                                       raw_ostream &cStream) const;
  44
  45   const MCRegisterInfo *getRegInfo() const { return RegInfo; }
  46 };
  47 }
  48
  49 static bool readInstruction16(const MemoryObject &region,
  50                               uint64_t address,
  51                               uint64_t &size,
  52                               uint16_t &insn) {
  53   uint8_t Bytes[4];
  54
  55   // We want to read exactly 2 Bytes of data.
  56   if (region.readBytes(address, 2, Bytes, NULL) == -1) {
  57     size = 0;
  58     return false;
  59   }
  60   // Encoded as a little-endian 16-bit word in the stream.
  61   insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
  62   return true;
  63 }
  64
  65 static bool readInstruction32(const MemoryObject &region,
  66                               uint64_t address,
  67                               uint64_t &size,
  68                               uint32_t &insn) {
  69   uint8_t Bytes[4];
  70
  71   // We want to read exactly 4 Bytes of data.
  72   if (region.readBytes(address, 4, Bytes, NULL) == -1) {
  73     size = 0;
  74     return false;
  75   }
  76   // Encoded as a little-endian 32-bit word in the stream.
  77   insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
  78          (Bytes[3] << 24);
  79   return true;
  80 }
  81
  82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
  83   const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
  84   return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
  85 }
  86
  87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
  88                                               unsigned RegNo,
  89                                               uint64_t Address,
  90                                               const void *Decoder);
  91
  92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
  93                                       uint64_t Address, const void *Decoder);
  94
  95 static DecodeStatus Decode2RInstruction(MCInst &Inst,
  96                                         unsigned Insn,
  97                                         uint64_t Address,
  98                                         const void *Decoder);
  99
 100 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
 101                                          unsigned Insn,
 102                                          uint64_t Address,
 103                                          const void *Decoder);
 104
 105 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
 106                                               unsigned Insn,
 107                                               uint64_t Address,
 108                                               const void *Decoder);
 109
 110 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
 111                                          unsigned Insn,
 112                                          uint64_t Address,
 113                                          const void *Decoder);
 114
 115 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
 116                                              unsigned Insn,
 117                                              uint64_t Address,
 118                                              const void *Decoder);
 119
 120 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
 121                                                    unsigned Insn,
 122                                                    uint64_t Address,
 123                                                    const void *Decoder);
 124
 125 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
 126                                          unsigned Insn,
 127                                          uint64_t Address,
 128                                          const void *Decoder);
 129
 130 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
 131                                           unsigned Insn,
 132                                           uint64_t Address,
 133                                           const void *Decoder);
 134
 135 static DecodeStatus Decode3RInstruction(MCInst &Inst,
 136                                         unsigned Insn,
 137                                         uint64_t Address,
 138                                         const void *Decoder);
 139
 140 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
 141                                           unsigned Insn,
 142                                           uint64_t Address,
 143                                           const void *Decoder);
 144
 145 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
 146                                               unsigned Insn,
 147                                               uint64_t Address,
 148                                               const void *Decoder);
 149
 150 #include "XCoreGenDisassemblerTables.inc"
 151
 152 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
 153                                               unsigned RegNo,
 154                                               uint64_t Address,
 155                                               const void *Decoder)
 156 {
 157   if (RegNo > 11)
 158     return MCDisassembler::Fail;
 159   unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
 160   Inst.addOperand(MCOperand::CreateReg(Reg));
 161   return MCDisassembler::Success;
 162 }
 163
 164 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
 165                                       uint64_t Address, const void *Decoder) {
 166   if (Val > 11)
 167     return MCDisassembler::Fail;
 168   static unsigned Values[] = {
 169     32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
 170   };
 171   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
 172   return MCDisassembler::Success;
 173 }
 174
 175 static DecodeStatus
 176 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
 177   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 178   if (Combined < 27)
 179     return MCDisassembler::Fail;
 180   if (fieldFromInstruction(Insn, 5, 1)) {
 181     if (Combined == 31)
 182       return MCDisassembler::Fail;
 183     Combined += 5;
 184   }
 185   Combined -= 27;
 186   unsigned Op1High = Combined % 3;
 187   unsigned Op2High = Combined / 3;
 188   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
 189   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
 190   return MCDisassembler::Success;
 191 }
 192
 193 static DecodeStatus
 194 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
 195                      unsigned &Op3) {
 196   unsigned Combined = fieldFromInstruction(Insn, 6, 5);
 197   if (Combined >= 27)
 198     return MCDisassembler::Fail;
 199
 200   unsigned Op1High = Combined % 3;
 201   unsigned Op2High = (Combined / 3) % 3;
 202   unsigned Op3High = Combined / 9;
 203   Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
 204   Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
 205   Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
 206   return MCDisassembler::Success;
 207 }
 208
 209 static DecodeStatus
 210 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
 211                          const void *Decoder) {
 212   // Try and decode as a 3R instruction.
 213   unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
 214   switch (Opcode) {
 215   case 0x0:
 216     Inst.setOpcode(XCore::STW_2rus);
 217     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 218   case 0x1:
 219     Inst.setOpcode(XCore::LDW_2rus);
 220     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 221   case 0x2:
 222     Inst.setOpcode(XCore::ADD_3r);
 223     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 224   case 0x3:
 225     Inst.setOpcode(XCore::SUB_3r);
 226     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 227   case 0x4:
 228     Inst.setOpcode(XCore::SHL_3r);
 229     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 230   case 0x5:
 231     Inst.setOpcode(XCore::SHR_3r);
 232     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 233   case 0x6:
 234     Inst.setOpcode(XCore::EQ_3r);
 235     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 236   case 0x7:
 237     Inst.setOpcode(XCore::AND_3r);
 238     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 239   case 0x8:
 240     Inst.setOpcode(XCore::OR_3r);
 241     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 242   case 0x9:
 243     Inst.setOpcode(XCore::LDW_3r);
 244     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 245   case 0x10:
 246     Inst.setOpcode(XCore::LD16S_3r);
 247     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 248   case 0x11:
 249     Inst.setOpcode(XCore::LD8U_3r);
 250     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 251   case 0x12:
 252     Inst.setOpcode(XCore::ADD_2rus);
 253     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 254   case 0x13:
 255     Inst.setOpcode(XCore::SUB_2rus);
 256     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 257   case 0x14:
 258     Inst.setOpcode(XCore::SHL_2rus);
 259     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 260   case 0x15:
 261     Inst.setOpcode(XCore::SHR_2rus);
 262     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
 263   case 0x16:
 264     Inst.setOpcode(XCore::EQ_2rus);
 265     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
 266   case 0x18:
 267     Inst.setOpcode(XCore::LSS_3r);
 268     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 269   case 0x19:
 270     Inst.setOpcode(XCore::LSU_3r);
 271     return Decode3RInstruction(Inst, Insn, Address, Decoder);
 272   }
 273   return MCDisassembler::Fail;
 274 }
 275
 276 static DecodeStatus
 277 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 278                     const void *Decoder) {
 279   unsigned Op1, Op2;
 280   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 281   if (S != MCDisassembler::Success)
 282     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 283
 284   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 285   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 286   return S;
 287 }
 288
 289 static DecodeStatus
 290 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 291                      const void *Decoder) {
 292   unsigned Op1, Op2;
 293   DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
 294   if (S != MCDisassembler::Success)
 295     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 296
 297   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 298   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 299   return S;
 300 }
 301
 302 static DecodeStatus
 303 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 304                           const void *Decoder) {
 305   unsigned Op1, Op2;
 306   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 307   if (S != MCDisassembler::Success)
 308     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 309
 310   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 311   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 312   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 313   return S;
 314 }
 315
 316 static DecodeStatus
 317 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 318                      const void *Decoder) {
 319   unsigned Op1, Op2;
 320   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 321   if (S != MCDisassembler::Success)
 322     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 323
 324   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 325   Inst.addOperand(MCOperand::CreateImm(Op2));
 326   return S;
 327 }
 328
 329 static DecodeStatus
 330 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 331                          const void *Decoder) {
 332   unsigned Op1, Op2;
 333   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 334   if (S != MCDisassembler::Success)
 335     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 336
 337   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 338   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 339   return S;
 340 }
 341
 342 static DecodeStatus
 343 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 344                                const void *Decoder) {
 345   unsigned Op1, Op2;
 346   DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
 347   if (S != MCDisassembler::Success)
 348     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
 349
 350   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 351   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 352   DecodeBitpOperand(Inst, Op2, Address, Decoder);
 353   return S;
 354 }
 355
 356 static DecodeStatus
 357 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 358                                const void *Decoder) {
 359   unsigned Op1, Op2;
 360   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 361                                         Op1, Op2);
 362   if (S == MCDisassembler::Success) {
 363     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 364     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 365   }
 366   return S;
 367 }
 368
 369 static DecodeStatus
 370 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 371                                const void *Decoder) {
 372   unsigned Op1, Op2;
 373   DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
 374                                         Op1, Op2);
 375   if (S == MCDisassembler::Success) {
 376     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 377     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 378   }
 379   return S;
 380 }
 381
 382 static DecodeStatus
 383 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 384                     const void *Decoder) {
 385   unsigned Op1, Op2, Op3;
 386   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 387   if (S == MCDisassembler::Success) {
 388     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 389     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 390     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
 391   }
 392   return S;
 393 }
 394
 395 static DecodeStatus
 396 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 397                       const void *Decoder) {
 398   unsigned Op1, Op2, Op3;
 399   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 400   if (S == MCDisassembler::Success) {
 401     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 402     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 403     Inst.addOperand(MCOperand::CreateImm(Op3));
 404   }
 405   return S;
 406 }
 407
 408 static DecodeStatus
 409 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
 410                       const void *Decoder) {
 411   unsigned Op1, Op2, Op3;
 412   DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
 413   if (S == MCDisassembler::Success) {
 414     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
 415     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
 416     DecodeBitpOperand(Inst, Op3, Address, Decoder);
 417   }
 418   return S;
 419 }
 420
 421 MCDisassembler::DecodeStatus
 422 XCoreDisassembler::getInstruction(MCInst &instr,
 423                                   uint64_t &Size,
 424                                   const MemoryObject &Region,
 425                                   uint64_t Address,
 426                                   raw_ostream &vStream,
 427                                   raw_ostream &cStream) const {
 428   uint16_t insn16;
 429
 430   if (!readInstruction16(Region, Address, Size, insn16)) {
 431     return Fail;
 432   }
 433
 434   // Calling the auto-generated decoder function.
 435   DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
 436                                           Address, this, STI);
 437   if (Result != Fail) {
 438     Size = 2;
 439     return Result;
 440   }
 441
 442   uint32_t insn32;
 443
 444   if (!readInstruction32(Region, Address, Size, insn32)) {
 445     return Fail;
 446   }
 447
 448   // Calling the auto-generated decoder function.
 449   Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
 450   if (Result != Fail) {
 451     Size = 4;
 452     return Result;
 453   }
 454
 455   return Fail;
 456 }
 457
 458 namespace llvm {
 459   extern Target TheXCoreTarget;
 460 }
 461
 462 static MCDisassembler *createXCoreDisassembler(const Target &T,
 463                                                const MCSubtargetInfo &STI) {
 464   return new XCoreDisassembler(STI, T.createMCRegInfo(""));
 465 }
 466
 467 extern "C" void LLVMInitializeXCoreDisassembler() {
 468   // Register the disassembler.
 469   TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
 470                                          createXCoreDisassembler);
 471 }