1 //===-- X86TargetTransformInfo.cpp - X86 specific TTI pass ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// This file implements a TargetTransformInfo analysis pass specific to the
11 /// X86 target machine. It uses the target's detailed information to provide
12 /// more precise answers to certain TTI queries, while letting the target
13 /// independent and default TTI implementations handle the rest.
15 //===----------------------------------------------------------------------===//
17 #define DEBUG_TYPE "x86tti"
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/CostTable.h"
26 // Declare the pass initialization routine locally as target-specific passes
27 // don't havve a target-wide initialization entry point, and so we rely on the
28 // pass constructor initialization.
30 void initializeX86TTIPass(PassRegistry &);
35 class X86TTI : public ImmutablePass, public TargetTransformInfo {
36 const X86TargetMachine *TM;
37 const X86Subtarget *ST;
38 const X86TargetLowering *TLI;
40 /// Estimate the overhead of scalarizing an instruction. Insert and Extract
41 /// are set if the result needs to be inserted and/or extracted from vectors.
42 unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const;
45 X86TTI() : ImmutablePass(ID), TM(0), ST(0), TLI(0) {
46 llvm_unreachable("This pass cannot be directly constructed");
49 X86TTI(const X86TargetMachine *TM)
50 : ImmutablePass(ID), TM(TM), ST(TM->getSubtargetImpl()),
51 TLI(TM->getTargetLowering()) {
52 initializeX86TTIPass(*PassRegistry::getPassRegistry());
55 virtual void initializePass() {
59 virtual void finalizePass() {
63 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
64 TargetTransformInfo::getAnalysisUsage(AU);
67 /// Pass identification.
70 /// Provide necessary pointer adjustments for the two base classes.
71 virtual void *getAdjustedAnalysisPointer(const void *ID) {
72 if (ID == &TargetTransformInfo::ID)
73 return (TargetTransformInfo*)this;
77 /// \name Scalar TTI Implementations
79 virtual PopcntSupportKind getPopcntSupport(unsigned TyWidth) const;
83 /// \name Vector TTI Implementations
86 virtual unsigned getNumberOfRegisters(bool Vector) const;
87 virtual unsigned getRegisterBitWidth(bool Vector) const;
88 virtual unsigned getMaximumUnrollFactor() const;
89 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
91 OperandValueKind) const;
92 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
93 int Index, Type *SubTp) const;
94 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
96 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
98 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
99 unsigned Index) const;
100 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
102 unsigned AddressSpace) const;
107 } // end anonymous namespace
109 INITIALIZE_AG_PASS(X86TTI, TargetTransformInfo, "x86tti",
110 "X86 Target Transform Info", true, true, false)
114 llvm::createX86TargetTransformInfoPass(const X86TargetMachine *TM) {
115 return new X86TTI(TM);
119 //===----------------------------------------------------------------------===//
123 //===----------------------------------------------------------------------===//
125 X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
126 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
127 // TODO: Currently the __builtin_popcount() implementation using SSE3
128 // instructions is inefficient. Once the problem is fixed, we should
129 // call ST->hasSSE3() instead of ST->hasSSE4().
130 return ST->hasSSE41() ? PSK_FastHardware : PSK_Software;
133 unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
134 if (Vector && !ST->hasSSE1())
142 unsigned X86TTI::getRegisterBitWidth(bool Vector) const {
144 if (ST->hasAVX()) return 256;
145 if (ST->hasSSE1()) return 128;
155 unsigned X86TTI::getMaximumUnrollFactor() const {
159 // Sandybridge and Haswell have multiple execution ports and pipelined
167 unsigned X86TTI::getArithmeticInstrCost(unsigned Opcode, Type *Ty,
168 OperandValueKind Op1Info,
169 OperandValueKind Op2Info) const {
170 // Legalize the type.
171 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Ty);
173 int ISD = TLI->InstructionOpcodeToISD(Opcode);
174 assert(ISD && "Invalid opcode");
176 static const CostTblEntry<MVT> AVX2CostTable[] = {
177 // Shifts on v4i64/v8i32 on AVX2 is legal even though we declare to
178 // customize them to detect the cases where shift amount is a scalar one.
179 { ISD::SHL, MVT::v4i32, 1 },
180 { ISD::SRL, MVT::v4i32, 1 },
181 { ISD::SRA, MVT::v4i32, 1 },
182 { ISD::SHL, MVT::v8i32, 1 },
183 { ISD::SRL, MVT::v8i32, 1 },
184 { ISD::SRA, MVT::v8i32, 1 },
185 { ISD::SHL, MVT::v2i64, 1 },
186 { ISD::SRL, MVT::v2i64, 1 },
187 { ISD::SHL, MVT::v4i64, 1 },
188 { ISD::SRL, MVT::v4i64, 1 },
190 { ISD::SHL, MVT::v32i8, 42 }, // cmpeqb sequence.
191 { ISD::SHL, MVT::v16i16, 16*10 }, // Scalarized.
193 { ISD::SRL, MVT::v32i8, 32*10 }, // Scalarized.
194 { ISD::SRL, MVT::v16i16, 8*10 }, // Scalarized.
196 { ISD::SRA, MVT::v32i8, 32*10 }, // Scalarized.
197 { ISD::SRA, MVT::v16i16, 16*10 }, // Scalarized.
198 { ISD::SRA, MVT::v4i64, 4*10 }, // Scalarized.
200 // Vectorizing division is a bad idea. See the SSE2 table for more comments.
201 { ISD::SDIV, MVT::v32i8, 32*20 },
202 { ISD::SDIV, MVT::v16i16, 16*20 },
203 { ISD::SDIV, MVT::v8i32, 8*20 },
204 { ISD::SDIV, MVT::v4i64, 4*20 },
205 { ISD::UDIV, MVT::v32i8, 32*20 },
206 { ISD::UDIV, MVT::v16i16, 16*20 },
207 { ISD::UDIV, MVT::v8i32, 8*20 },
208 { ISD::UDIV, MVT::v4i64, 4*20 },
211 // Look for AVX2 lowering tricks.
213 int Idx = CostTableLookup<MVT>(AVX2CostTable, array_lengthof(AVX2CostTable),
216 return LT.first * AVX2CostTable[Idx].Cost;
219 static const CostTblEntry<MVT> SSE2UniformConstCostTable[] = {
220 // We don't correctly identify costs of casts because they are marked as
222 // Constant splats are cheaper for the following instructions.
223 { ISD::SHL, MVT::v16i8, 1 }, // psllw.
224 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
225 { ISD::SHL, MVT::v4i32, 1 }, // pslld
226 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
228 { ISD::SRL, MVT::v16i8, 1 }, // psrlw.
229 { ISD::SRL, MVT::v8i16, 1 }, // psrlw.
230 { ISD::SRL, MVT::v4i32, 1 }, // psrld.
231 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
233 { ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
234 { ISD::SRA, MVT::v8i16, 1 }, // psraw.
235 { ISD::SRA, MVT::v4i32, 1 }, // psrad.
238 if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
240 int Idx = CostTableLookup<MVT>(SSE2UniformConstCostTable,
241 array_lengthof(SSE2UniformConstCostTable),
244 return LT.first * SSE2UniformConstCostTable[Idx].Cost;
248 static const CostTblEntry<MVT> SSE2CostTable[] = {
249 // We don't correctly identify costs of casts because they are marked as
251 // For some cases, where the shift amount is a scalar we would be able
252 // to generate better code. Unfortunately, when this is the case the value
253 // (the splat) will get hoisted out of the loop, thereby making it invisible
254 // to ISel. The cost model must return worst case assumptions because it is
255 // used for vectorization and we don't want to make vectorized code worse
257 { ISD::SHL, MVT::v16i8, 30 }, // cmpeqb sequence.
258 { ISD::SHL, MVT::v8i16, 8*10 }, // Scalarized.
259 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
260 { ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
262 { ISD::SRL, MVT::v16i8, 16*10 }, // Scalarized.
263 { ISD::SRL, MVT::v8i16, 8*10 }, // Scalarized.
264 { ISD::SRL, MVT::v4i32, 4*10 }, // Scalarized.
265 { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
267 { ISD::SRA, MVT::v16i8, 16*10 }, // Scalarized.
268 { ISD::SRA, MVT::v8i16, 8*10 }, // Scalarized.
269 { ISD::SRA, MVT::v4i32, 4*10 }, // Scalarized.
270 { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
272 // It is not a good idea to vectorize division. We have to scalarize it and
273 // in the process we will often end up having to spilling regular
274 // registers. The overhead of division is going to dominate most kernels
275 // anyways so try hard to prevent vectorization of division - it is
276 // generally a bad idea. Assume somewhat arbitrarily that we have to be able
277 // to hide "20 cycles" for each lane.
278 { ISD::SDIV, MVT::v16i8, 16*20 },
279 { ISD::SDIV, MVT::v8i16, 8*20 },
280 { ISD::SDIV, MVT::v4i32, 4*20 },
281 { ISD::SDIV, MVT::v2i64, 2*20 },
282 { ISD::UDIV, MVT::v16i8, 16*20 },
283 { ISD::UDIV, MVT::v8i16, 8*20 },
284 { ISD::UDIV, MVT::v4i32, 4*20 },
285 { ISD::UDIV, MVT::v2i64, 2*20 },
289 int Idx = CostTableLookup<MVT>(SSE2CostTable, array_lengthof(SSE2CostTable),
292 return LT.first * SSE2CostTable[Idx].Cost;
295 static const CostTblEntry<MVT> AVX1CostTable[] = {
296 // We don't have to scalarize unsupported ops. We can issue two half-sized
297 // operations and we only need to extract the upper YMM half.
298 // Two ops + 1 extract + 1 insert = 4.
299 { ISD::MUL, MVT::v8i32, 4 },
300 { ISD::SUB, MVT::v8i32, 4 },
301 { ISD::ADD, MVT::v8i32, 4 },
302 { ISD::SUB, MVT::v4i64, 4 },
303 { ISD::ADD, MVT::v4i64, 4 },
304 // A v4i64 multiply is custom lowered as two split v2i64 vectors that then
305 // are lowered as a series of long multiplies(3), shifts(4) and adds(2)
306 // Because we believe v4i64 to be a legal type, we must also include the
307 // split factor of two in the cost table. Therefore, the cost here is 18
309 { ISD::MUL, MVT::v4i64, 18 },
312 // Look for AVX1 lowering tricks.
313 if (ST->hasAVX() && !ST->hasAVX2()) {
314 int Idx = CostTableLookup<MVT>(AVX1CostTable, array_lengthof(AVX1CostTable),
317 return LT.first * AVX1CostTable[Idx].Cost;
320 // Custom lowering of vectors.
321 static const CostTblEntry<MVT> CustomLowered[] = {
322 // A v2i64/v4i64 and multiply is custom lowered as a series of long
323 // multiplies(3), shifts(4) and adds(2).
324 { ISD::MUL, MVT::v2i64, 9 },
325 { ISD::MUL, MVT::v4i64, 9 },
327 int Idx = CostTableLookup<MVT>(CustomLowered, array_lengthof(CustomLowered),
330 return LT.first * CustomLowered[Idx].Cost;
332 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle,
333 // 2x pmuludq, 2x shuffle.
334 if (ISD == ISD::MUL && LT.second == MVT::v4i32 && ST->hasSSE2() &&
338 // Fallback to the default implementation.
339 return TargetTransformInfo::getArithmeticInstrCost(Opcode, Ty, Op1Info,
343 unsigned X86TTI::getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
345 // We only estimate the cost of reverse shuffles.
346 if (Kind != SK_Reverse)
347 return TargetTransformInfo::getShuffleCost(Kind, Tp, Index, SubTp);
349 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Tp);
351 if (LT.second.getSizeInBits() > 128)
352 Cost = 3; // Extract + insert + copy.
354 // Multiple by the number of parts.
355 return Cost * LT.first;
358 unsigned X86TTI::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) const {
359 int ISD = TLI->InstructionOpcodeToISD(Opcode);
360 assert(ISD && "Invalid opcode");
362 std::pair<unsigned, MVT> LTSrc = TLI->getTypeLegalizationCost(Src);
363 std::pair<unsigned, MVT> LTDest = TLI->getTypeLegalizationCost(Dst);
365 static const TypeConversionCostTblEntry<MVT> SSE2ConvTbl[] = {
366 // These are somewhat magic numbers justified by looking at the output of
367 // Intel's IACA, running some kernels and making sure when we take
368 // legalization into account the throughput will be overestimated.
369 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
370 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
371 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
372 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
373 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 },
374 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 },
375 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 },
376 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 },
377 // There are faster sequences for float conversions.
378 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
379 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
380 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
381 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
382 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 },
383 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 },
384 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 },
385 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 },
388 if (ST->hasSSE2() && !ST->hasAVX()) {
389 int Idx = ConvertCostTableLookup<MVT>(SSE2ConvTbl,
390 array_lengthof(SSE2ConvTbl),
391 ISD, LTDest.second, LTSrc.second);
393 return LTSrc.first * SSE2ConvTbl[Idx].Cost;
396 EVT SrcTy = TLI->getValueType(Src);
397 EVT DstTy = TLI->getValueType(Dst);
399 // The function getSimpleVT only handles simple value types.
400 if (!SrcTy.isSimple() || !DstTy.isSimple())
401 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
403 static const TypeConversionCostTblEntry<MVT> AVXConversionTbl[] = {
404 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
405 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
406 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
407 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
408 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
409 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
411 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
412 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
413 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
414 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 },
415 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
416 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
417 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 },
418 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
419 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i1, 3 },
420 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i8, 3 },
421 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 },
422 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32, 1 },
424 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i1, 6 },
425 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 5 },
426 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
427 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 9 },
428 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 7 },
429 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 2 },
430 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
431 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 6 },
432 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i1, 7 },
433 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i8, 2 },
434 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 },
435 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i32, 6 },
437 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
438 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
439 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
440 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
441 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i1, 8 },
442 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i8, 6 },
443 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 },
444 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
448 int Idx = ConvertCostTableLookup<MVT>(AVXConversionTbl,
449 array_lengthof(AVXConversionTbl),
450 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
452 return AVXConversionTbl[Idx].Cost;
455 return TargetTransformInfo::getCastInstrCost(Opcode, Dst, Src);
458 unsigned X86TTI::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
459 Type *CondTy) const {
460 // Legalize the type.
461 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(ValTy);
465 int ISD = TLI->InstructionOpcodeToISD(Opcode);
466 assert(ISD && "Invalid opcode");
468 static const CostTblEntry<MVT> SSE42CostTbl[] = {
469 { ISD::SETCC, MVT::v2f64, 1 },
470 { ISD::SETCC, MVT::v4f32, 1 },
471 { ISD::SETCC, MVT::v2i64, 1 },
472 { ISD::SETCC, MVT::v4i32, 1 },
473 { ISD::SETCC, MVT::v8i16, 1 },
474 { ISD::SETCC, MVT::v16i8, 1 },
477 static const CostTblEntry<MVT> AVX1CostTbl[] = {
478 { ISD::SETCC, MVT::v4f64, 1 },
479 { ISD::SETCC, MVT::v8f32, 1 },
480 // AVX1 does not support 8-wide integer compare.
481 { ISD::SETCC, MVT::v4i64, 4 },
482 { ISD::SETCC, MVT::v8i32, 4 },
483 { ISD::SETCC, MVT::v16i16, 4 },
484 { ISD::SETCC, MVT::v32i8, 4 },
487 static const CostTblEntry<MVT> AVX2CostTbl[] = {
488 { ISD::SETCC, MVT::v4i64, 1 },
489 { ISD::SETCC, MVT::v8i32, 1 },
490 { ISD::SETCC, MVT::v16i16, 1 },
491 { ISD::SETCC, MVT::v32i8, 1 },
495 int Idx = CostTableLookup<MVT>(AVX2CostTbl, array_lengthof(AVX2CostTbl),
498 return LT.first * AVX2CostTbl[Idx].Cost;
502 int Idx = CostTableLookup<MVT>(AVX1CostTbl, array_lengthof(AVX1CostTbl),
505 return LT.first * AVX1CostTbl[Idx].Cost;
508 if (ST->hasSSE42()) {
509 int Idx = CostTableLookup<MVT>(SSE42CostTbl, array_lengthof(SSE42CostTbl),
512 return LT.first * SSE42CostTbl[Idx].Cost;
515 return TargetTransformInfo::getCmpSelInstrCost(Opcode, ValTy, CondTy);
518 unsigned X86TTI::getVectorInstrCost(unsigned Opcode, Type *Val,
519 unsigned Index) const {
520 assert(Val->isVectorTy() && "This must be a vector type");
523 // Legalize the type.
524 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Val);
526 // This type is legalized to a scalar type.
527 if (!LT.second.isVector())
530 // The type may be split. Normalize the index to the new type.
531 unsigned Width = LT.second.getVectorNumElements();
532 Index = Index % Width;
534 // Floating point scalars are already located in index #0.
535 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
539 return TargetTransformInfo::getVectorInstrCost(Opcode, Val, Index);
542 unsigned X86TTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
543 unsigned AddressSpace) const {
544 // Legalize the type.
545 std::pair<unsigned, MVT> LT = TLI->getTypeLegalizationCost(Src);
546 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
549 // Each load/store unit costs 1.
550 unsigned Cost = LT.first * 1;
552 // On Sandybridge 256bit load/stores are double pumped
553 // (but not on Haswell).
554 if (LT.second.getSizeInBits() > 128 && !ST->hasAVX2())