lib/Target/X86/X86TargetMachine.cpp

   1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the X86 specific subclass of TargetMachine.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86TargetMachine.h"
  15 #include "X86.h"
  16 #include "llvm/PassManager.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/FormattedStream.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 using namespace llvm;
  24
  25 extern "C" void LLVMInitializeX86Target() {
  26   // Register the target.
  27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
  28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
  29 }
  30
  31
  32 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
  33                                          StringRef CPU, StringRef FS,
  34                                          Reloc::Model RM, CodeModel::Model CM,
  35                                          CodeGenOpt::Level OL)
  36   : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, false),
  37     DataLayout(getSubtargetImpl()->isTargetDarwin() ?
  38                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
  39                "n8:16:32-S128" :
  40                (getSubtargetImpl()->isTargetCygMing() ||
  41                 getSubtargetImpl()->isTargetWindows()) ?
  42                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
  43                "n8:16:32-S32" :
  44                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
  45                "n8:16:32-S128"),
  46     InstrInfo(*this),
  47     TSInfo(*this),
  48     TLInfo(*this),
  49     JITInfo(*this) {
  50 }
  51
  52
  53 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
  54                                          StringRef CPU, StringRef FS,
  55                                          Reloc::Model RM, CodeModel::Model CM,
  56                                          CodeGenOpt::Level OL)
  57   : X86TargetMachine(T, TT, CPU, FS, RM, CM, OL, true),
  58     DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
  59                "n8:16:32:64-S128"),
  60     InstrInfo(*this),
  61     TSInfo(*this),
  62     TLInfo(*this),
  63     JITInfo(*this) {
  64 }
  65
  66 /// X86TargetMachine ctor - Create an X86 target.
  67 ///
  68 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
  69                                    StringRef CPU, StringRef FS,
  70                                    Reloc::Model RM, CodeModel::Model CM,
  71                                    CodeGenOpt::Level OL,
  72                                    bool is64Bit)
  73   : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
  74     Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
  75     FrameLowering(*this, Subtarget),
  76     ELFWriterInfo(is64Bit, true) {
  77   // Determine the PICStyle based on the target selected.
  78   if (getRelocationModel() == Reloc::Static) {
  79     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
  80     Subtarget.setPICStyle(PICStyles::None);
  81   } else if (Subtarget.is64Bit()) {
  82     // PIC in 64 bit mode is always rip-rel.
  83     Subtarget.setPICStyle(PICStyles::RIPRel);
  84   } else if (Subtarget.isTargetCygMing()) {
  85     Subtarget.setPICStyle(PICStyles::None);
  86   } else if (Subtarget.isTargetDarwin()) {
  87     if (getRelocationModel() == Reloc::PIC_)
  88       Subtarget.setPICStyle(PICStyles::StubPIC);
  89     else {
  90       assert(getRelocationModel() == Reloc::DynamicNoPIC);
  91       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
  92     }
  93   } else if (Subtarget.isTargetELF()) {
  94     Subtarget.setPICStyle(PICStyles::GOT);
  95   }
  96
  97   // default to hard float ABI
  98   if (FloatABIType == FloatABI::Default)
  99     FloatABIType = FloatABI::Hard;
 100 }
 101
 102 //===----------------------------------------------------------------------===//
 103 // Command line options for x86
 104 //===----------------------------------------------------------------------===//
 105 static cl::opt<bool>
 106 UseVZeroUpper("x86-use-vzeroupper",
 107   cl::desc("Minimize AVX to SSE transition penalty"),
 108   cl::init(false));
 109
 110 //===----------------------------------------------------------------------===//
 111 // Pass Pipeline Configuration
 112 //===----------------------------------------------------------------------===//
 113
 114 bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
 115   // Install an instruction selector.
 116   PM.add(createX86ISelDag(*this, getOptLevel()));
 117
 118   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
 119   if (!Subtarget.is64Bit())
 120     PM.add(createGlobalBaseRegPass());
 121
 122   return false;
 123 }
 124
 125 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
 126   PM.add(createX86MaxStackAlignmentHeuristicPass());
 127   return false;  // -print-machineinstr shouldn't print after this.
 128 }
 129
 130 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
 131   PM.add(createX86FloatingPointStackifierPass());
 132   return true;  // -print-machineinstr should print after this.
 133 }
 134
 135 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
 136   bool ShouldPrint = false;
 137   if (getOptLevel() != CodeGenOpt::None && Subtarget.hasXMMInt()) {
 138     PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
 139     ShouldPrint = true;
 140   }
 141
 142   if (Subtarget.hasAVX() && UseVZeroUpper) {
 143     PM.add(createX86IssueVZeroUpperPass());
 144     ShouldPrint = true;
 145   }
 146
 147   return ShouldPrint;
 148 }
 149
 150 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
 151                                       JITCodeEmitter &JCE) {
 152   PM.add(createX86JITCodeEmitterPass(*this, JCE));
 153
 154   return false;
 155 }