lib/Target/X86/X86TargetMachine.cpp

   1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the X86 specific subclass of TargetMachine.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "X86TargetMachine.h"
  15 #include "X86.h"
  16 #include "llvm/PassManager.h"
  17 #include "llvm/CodeGen/MachineFunction.h"
  18 #include "llvm/CodeGen/Passes.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Support/FormattedStream.h"
  21 #include "llvm/Target/TargetOptions.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 using namespace llvm;
  24
  25 extern "C" void LLVMInitializeX86Target() {
  26   // Register the target.
  27   RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
  28   RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
  29 }
  30
  31 void X86_32TargetMachine::anchor() { }
  32
  33 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
  34                                          StringRef CPU, StringRef FS,
  35                                          const TargetOptions &Options,
  36                                          Reloc::Model RM, CodeModel::Model CM,
  37                                          CodeGenOpt::Level OL)
  38   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
  39     DataLayout(getSubtargetImpl()->isTargetDarwin() ?
  40                "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-"
  41                "n8:16:32-S128" :
  42                (getSubtargetImpl()->isTargetCygMing() ||
  43                 getSubtargetImpl()->isTargetWindows()) ?
  44                "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-"
  45                "n8:16:32-S32" :
  46                "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-"
  47                "n8:16:32-S128"),
  48     InstrInfo(*this),
  49     TSInfo(*this),
  50     TLInfo(*this),
  51     JITInfo(*this) {
  52 }
  53
  54 void X86_64TargetMachine::anchor() { }
  55
  56 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
  57                                          StringRef CPU, StringRef FS,
  58                                          const TargetOptions &Options,
  59                                          Reloc::Model RM, CodeModel::Model CM,
  60                                          CodeGenOpt::Level OL)
  61   : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
  62     DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-"
  63                "n8:16:32:64-S128"),
  64     InstrInfo(*this),
  65     TSInfo(*this),
  66     TLInfo(*this),
  67     JITInfo(*this) {
  68 }
  69
  70 /// X86TargetMachine ctor - Create an X86 target.
  71 ///
  72 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
  73                                    StringRef CPU, StringRef FS,
  74                                    const TargetOptions &Options,
  75                                    Reloc::Model RM, CodeModel::Model CM,
  76                                    CodeGenOpt::Level OL,
  77                                    bool is64Bit)
  78   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
  79     Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
  80     FrameLowering(*this, Subtarget),
  81     ELFWriterInfo(is64Bit, true) {
  82   // Determine the PICStyle based on the target selected.
  83   if (getRelocationModel() == Reloc::Static) {
  84     // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
  85     Subtarget.setPICStyle(PICStyles::None);
  86   } else if (Subtarget.is64Bit()) {
  87     // PIC in 64 bit mode is always rip-rel.
  88     Subtarget.setPICStyle(PICStyles::RIPRel);
  89   } else if (Subtarget.isTargetCygMing()) {
  90     Subtarget.setPICStyle(PICStyles::None);
  91   } else if (Subtarget.isTargetDarwin()) {
  92     if (getRelocationModel() == Reloc::PIC_)
  93       Subtarget.setPICStyle(PICStyles::StubPIC);
  94     else {
  95       assert(getRelocationModel() == Reloc::DynamicNoPIC);
  96       Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
  97     }
  98   } else if (Subtarget.isTargetELF()) {
  99     Subtarget.setPICStyle(PICStyles::GOT);
 100   }
 101
 102   // default to hard float ABI
 103   if (Options.FloatABIType == FloatABI::Default)
 104     this->Options.FloatABIType = FloatABI::Hard;
 105
 106   if (Options.EnableSegmentedStacks && !Subtarget.isTargetELF())
 107     report_fatal_error("Segmented stacks are only implemented on ELF.");
 108 }
 109
 110 //===----------------------------------------------------------------------===//
 111 // Command line options for x86
 112 //===----------------------------------------------------------------------===//
 113 static cl::opt<bool>
 114 UseVZeroUpper("x86-use-vzeroupper",
 115   cl::desc("Minimize AVX to SSE transition penalty"),
 116   cl::init(true));
 117
 118 //===----------------------------------------------------------------------===//
 119 // Pass Pipeline Configuration
 120 //===----------------------------------------------------------------------===//
 121
 122 bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
 123   // Install an instruction selector.
 124   PM.add(createX86ISelDag(*this, getOptLevel()));
 125
 126   // For 32-bit, prepend instructions to set the "global base reg" for PIC.
 127   if (!Subtarget.is64Bit())
 128     PM.add(createGlobalBaseRegPass());
 129
 130   return false;
 131 }
 132
 133 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
 134   PM.add(createX86MaxStackAlignmentHeuristicPass());
 135   return false;  // -print-machineinstr shouldn't print after this.
 136 }
 137
 138 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
 139   PM.add(createX86FloatingPointStackifierPass());
 140   return true;  // -print-machineinstr should print after this.
 141 }
 142
 143 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
 144   bool ShouldPrint = false;
 145   if (getOptLevel() != CodeGenOpt::None && Subtarget.hasXMMInt()) {
 146     PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
 147     ShouldPrint = true;
 148   }
 149
 150   if (Subtarget.hasAVX() && UseVZeroUpper) {
 151     PM.add(createX86IssueVZeroUpperPass());
 152     ShouldPrint = true;
 153   }
 154
 155   return ShouldPrint;
 156 }
 157
 158 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
 159                                       JITCodeEmitter &JCE) {
 160   PM.add(createX86JITCodeEmitterPass(*this, JCE));
 161
 162   return false;
 163 }