1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/IntrinsicLowering.h"
17 #include "llvm/Module.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Target/TargetMachineImpls.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/Transforms/Scalar.h"
23 #include "Support/CommandLine.h"
24 #include "Support/Statistic.h"
28 cl::opt<bool> PrintCode("print-machineinstrs",
29 cl::desc("Print generated machine code"));
30 cl::opt<bool> NoPatternISel("disable-pattern-isel", cl::init(true),
31 cl::desc("Use the 'simple' X86 instruction selector"));
32 cl::opt<bool> NoSSAPeephole("disable-ssa-peephole", cl::init(true),
33 cl::desc("Disable the ssa-based peephole optimizer "
34 "(defaults to disabled)"));
37 // allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
38 // that implements the X86 backend.
40 TargetMachine *llvm::allocateX86TargetMachine(const Module &M,
41 IntrinsicLowering *IL) {
42 return new X86TargetMachine(M, IL);
46 /// X86TargetMachine ctor - Create an ILP32 architecture model
48 X86TargetMachine::X86TargetMachine(const Module &M, IntrinsicLowering *il)
49 : TargetMachine("X86", true, 4, 4, 4, 4, 4),
50 IL(il ? il : new DefaultIntrinsicLowering()),
51 FrameInfo(TargetFrameInfo::StackGrowsDown, 8/*16 for SSE*/, 4),
55 X86TargetMachine::~X86TargetMachine() {
60 // addPassesToEmitAssembly - We currently use all of the same passes as the JIT
61 // does to emit statically compiled machine code.
62 bool X86TargetMachine::addPassesToEmitAssembly(PassManager &PM,
64 // FIXME: Implement the switch instruction in the instruction selector!
65 PM.add(createLowerSwitchPass());
67 // FIXME: Implement the invoke/unwind instructions!
68 PM.add(createLowerInvokePass());
70 // FIXME: The code generator does not properly handle functions with
71 // unreachable basic blocks.
72 PM.add(createCFGSimplificationPass());
75 PM.add(createX86SimpleInstructionSelector(*this, *IL));
77 PM.add(createX86PatternInstructionSelector(*this, *IL));
79 // Run optional SSA-based machine code optimizations next...
81 PM.add(createX86SSAPeepholeOptimizerPass());
83 // Print the instruction selected machine code...
85 PM.add(createMachineFunctionPrinterPass());
87 // Perform register allocation to convert to a concrete x86 representation
88 PM.add(createRegisterAllocator());
91 PM.add(createMachineFunctionPrinterPass());
93 PM.add(createX86FloatingPointStackifierPass());
96 PM.add(createMachineFunctionPrinterPass());
98 // Insert prolog/epilog code. Eliminate abstract frame index references...
99 PM.add(createPrologEpilogCodeInserter());
101 PM.add(createX86PeepholeOptimizerPass());
103 if (PrintCode) // Print the register-allocated code
104 PM.add(createX86CodePrinterPass(std::cerr, *this));
106 PM.add(createX86CodePrinterPass(Out, *this));
108 // Delete machine code for this function
109 PM.add(createMachineCodeDeleter());
111 return false; // success!
114 /// addPassesToJITCompile - Add passes to the specified pass manager to
115 /// implement a fast dynamic compiler for this target. Return true if this is
116 /// not supported for this target.
118 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
119 // FIXME: Implement the switch instruction in the instruction selector!
120 PM.add(createLowerSwitchPass());
122 // FIXME: Implement the invoke/unwind instructions!
123 PM.add(createLowerInvokePass());
125 // FIXME: The code generator does not properly handle functions with
126 // unreachable basic blocks.
127 PM.add(createCFGSimplificationPass());
130 PM.add(createX86SimpleInstructionSelector(TM, IL));
132 PM.add(createX86PatternInstructionSelector(TM, IL));
134 // Run optional SSA-based machine code optimizations next...
136 PM.add(createX86SSAPeepholeOptimizerPass());
138 // FIXME: Add SSA based peephole optimizer here.
140 // Print the instruction selected machine code...
142 PM.add(createMachineFunctionPrinterPass());
144 // Perform register allocation to convert to a concrete x86 representation
145 PM.add(createRegisterAllocator());
148 PM.add(createMachineFunctionPrinterPass());
150 PM.add(createX86FloatingPointStackifierPass());
153 PM.add(createMachineFunctionPrinterPass());
155 // Insert prolog/epilog code. Eliminate abstract frame index references...
156 PM.add(createPrologEpilogCodeInserter());
158 PM.add(createX86PeepholeOptimizerPass());
160 if (PrintCode) // Print the register-allocated code
161 PM.add(createX86CodePrinterPass(std::cerr, TM));