1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/FormattedStream.h"
21 #include "llvm/Support/TargetRegistry.h"
22 #include "llvm/Target/TargetOptions.h"
25 extern "C" void LLVMInitializeX86Target() {
26 // Register the target.
27 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
28 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
31 void X86_32TargetMachine::anchor() { }
33 static std::string computeDataLayout(const X86Subtarget &ST) {
34 // X86 is little endian
35 std::string Ret = "e";
37 Ret += DataLayout::getManglingComponent(ST.getTargetTriple());
38 // X86 and x32 have 32 bit pointers.
39 if (ST.isTarget64BitILP32() || !ST.is64Bit())
42 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
43 if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
49 // Some ABIs align long double to 128 bits, others to 32.
50 if (ST.isTargetNaCl())
52 else if (ST.is64Bit() || ST.isTargetDarwin())
57 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
59 Ret += "-n8:16:32:64";
63 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
64 if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
72 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
73 StringRef CPU, StringRef FS,
74 const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
77 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false),
78 DL(computeDataLayout(*getSubtargetImpl())),
86 void X86_64TargetMachine::anchor() { }
88 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
89 StringRef CPU, StringRef FS,
90 const TargetOptions &Options,
91 Reloc::Model RM, CodeModel::Model CM,
93 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true),
94 // The x32 ABI dictates the ILP32 programming model for x64.
95 DL(computeDataLayout(*getSubtargetImpl())),
103 /// X86TargetMachine ctor - Create an X86 target.
105 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
106 StringRef CPU, StringRef FS,
107 const TargetOptions &Options,
108 Reloc::Model RM, CodeModel::Model CM,
109 CodeGenOpt::Level OL,
111 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
112 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit),
113 FrameLowering(*this, Subtarget),
114 InstrItins(Subtarget.getInstrItineraryData()){
115 // Determine the PICStyle based on the target selected.
116 if (getRelocationModel() == Reloc::Static) {
117 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
118 Subtarget.setPICStyle(PICStyles::None);
119 } else if (Subtarget.is64Bit()) {
120 // PIC in 64 bit mode is always rip-rel.
121 Subtarget.setPICStyle(PICStyles::RIPRel);
122 } else if (Subtarget.isTargetCOFF()) {
123 Subtarget.setPICStyle(PICStyles::None);
124 } else if (Subtarget.isTargetDarwin()) {
125 if (getRelocationModel() == Reloc::PIC_)
126 Subtarget.setPICStyle(PICStyles::StubPIC);
128 assert(getRelocationModel() == Reloc::DynamicNoPIC);
129 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
131 } else if (Subtarget.isTargetELF()) {
132 Subtarget.setPICStyle(PICStyles::GOT);
135 // default to hard float ABI
136 if (Options.FloatABIType == FloatABI::Default)
137 this->Options.FloatABIType = FloatABI::Hard;
140 //===----------------------------------------------------------------------===//
141 // Command line options for x86
142 //===----------------------------------------------------------------------===//
144 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
145 cl::desc("Minimize AVX to SSE transition penalty"),
148 // Temporary option to control early if-conversion for x86 while adding machine
151 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
152 cl::desc("Enable early if-conversion on X86"));
154 //===----------------------------------------------------------------------===//
155 // X86 Analysis Pass Setup
156 //===----------------------------------------------------------------------===//
158 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) {
159 // Add first the target-independent BasicTTI pass, then our X86 pass. This
160 // allows the X86 pass to delegate to the target independent layer when
162 PM.add(createBasicTargetTransformInfoPass(this));
163 PM.add(createX86TargetTransformInfoPass(this));
167 //===----------------------------------------------------------------------===//
168 // Pass Pipeline Configuration
169 //===----------------------------------------------------------------------===//
172 /// X86 Code Generator Pass Configuration Options.
173 class X86PassConfig : public TargetPassConfig {
175 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
176 : TargetPassConfig(TM, PM) {}
178 X86TargetMachine &getX86TargetMachine() const {
179 return getTM<X86TargetMachine>();
182 const X86Subtarget &getX86Subtarget() const {
183 return *getX86TargetMachine().getSubtargetImpl();
186 virtual bool addInstSelector();
187 virtual bool addILPOpts();
188 virtual bool addPreRegAlloc();
189 virtual bool addPostRegAlloc();
190 virtual bool addPreEmitPass();
194 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
195 return new X86PassConfig(this, PM);
198 bool X86PassConfig::addInstSelector() {
199 // Install an instruction selector.
200 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
202 // For ELF, cleanup any local-dynamic TLS accesses.
203 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None)
204 addPass(createCleanupLocalDynamicTLSPass());
206 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
207 if (!getX86Subtarget().is64Bit())
208 addPass(createGlobalBaseRegPass());
213 bool X86PassConfig::addILPOpts() {
214 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) {
215 addPass(&EarlyIfConverterID);
221 bool X86PassConfig::addPreRegAlloc() {
222 return false; // -print-machineinstr shouldn't print after this.
225 bool X86PassConfig::addPostRegAlloc() {
226 addPass(createX86FloatingPointStackifierPass());
227 return true; // -print-machineinstr should print after this.
230 bool X86PassConfig::addPreEmitPass() {
231 bool ShouldPrint = false;
232 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
233 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass));
237 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
238 addPass(createX86IssueVZeroUpperPass());
242 if (getOptLevel() != CodeGenOpt::None &&
243 getX86Subtarget().padShortFunctions()) {
244 addPass(createX86PadShortFunctions());
247 if (getOptLevel() != CodeGenOpt::None &&
248 getX86Subtarget().LEAusesAG()){
249 addPass(createX86FixupLEAs());
256 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
257 JITCodeEmitter &JCE) {
258 PM.add(createX86JITCodeEmitterPass(*this, JCE));