1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the X86 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #include "X86TargetMachine.h"
16 #include "llvm/Module.h"
17 #include "llvm/PassManager.h"
18 #include "llvm/CodeGen/IntrinsicLowering.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/Target/TargetMachineRegistry.h"
23 #include "llvm/Transforms/Scalar.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/ADT/Statistic.h"
29 X86VectorEnum llvm::X86Vector = NoSSE;
30 bool llvm::X86ScalarSSE = false;
31 bool llvm::X86DAGIsel = false;
33 /// X86TargetMachineModule - Note that this is used on hosts that cannot link
34 /// in a library unless there are references into the library. In particular,
35 /// it seems that it is not possible to get things to work on Win32 without
36 /// this. Though it is unused, do not remove it.
37 extern "C" int X86TargetMachineModule;
38 int X86TargetMachineModule = 0;
41 cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
42 cl::desc("Disable the X86 asm printer, for use "
43 "when profiling the code generator."));
44 cl::opt<bool, true> EnableSSEFP("enable-sse-scalar-fp",
45 cl::desc("Perform FP math in SSE regs instead of the FP stack"),
46 cl::location(X86ScalarSSE),
49 cl::opt<bool, true> EnableX86DAGDAG("enable-x86-dag-isel", cl::Hidden,
50 cl::desc("Enable DAG-to-DAG isel for X86"),
51 cl::location(X86DAGIsel),
54 // FIXME: This should eventually be handled with target triples and
56 cl::opt<X86VectorEnum, true>
58 cl::desc("Enable SSE support in the X86 target:"),
60 clEnumValN(SSE, "sse", " Enable SSE support"),
61 clEnumValN(SSE2, "sse2", " Enable SSE and SSE2 support"),
62 clEnumValN(SSE3, "sse3", " Enable SSE, SSE2, and SSE3 support"),
64 cl::location(X86Vector), cl::init(NoSSE));
66 // Register the target.
67 RegisterTarget<X86TargetMachine> X("x86", " IA-32 (Pentium and above)");
70 unsigned X86TargetMachine::getJITMatchQuality() {
71 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
78 unsigned X86TargetMachine::getModuleMatchQuality(const Module &M) {
79 // We strongly match "i[3-9]86-*".
80 std::string TT = M.getTargetTriple();
81 if (TT.size() >= 5 && TT[0] == 'i' && TT[2] == '8' && TT[3] == '6' &&
82 TT[4] == '-' && TT[1] - '3' < 6)
85 if (M.getEndianness() == Module::LittleEndian &&
86 M.getPointerSize() == Module::Pointer32)
87 return 10; // Weak match
88 else if (M.getEndianness() != Module::AnyEndianness ||
89 M.getPointerSize() != Module::AnyPointerSize)
90 return 0; // Match for some other target
92 return getJITMatchQuality()/2;
95 /// X86TargetMachine ctor - Create an ILP32 architecture model
97 X86TargetMachine::X86TargetMachine(const Module &M,
98 IntrinsicLowering *IL,
99 const std::string &FS)
100 : TargetMachine("X86", IL, true, 4, 4, 4, 4, 4),
102 FrameInfo(TargetFrameInfo::StackGrowsDown,
103 Subtarget.getStackAlignment(), -4),
105 // Scalar SSE FP requires at least SSE2
106 X86ScalarSSE &= X86Vector >= SSE2;
108 // Ignore -enable-sse-scalar-fp if -enable-x86-dag-isel.
109 X86ScalarSSE |= (X86DAGIsel && X86Vector >= SSE2);
113 // addPassesToEmitFile - We currently use all of the same passes as the JIT
114 // does to emit statically compiled machine code.
115 bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
116 CodeGenFileType FileType,
118 if (FileType != TargetMachine::AssemblyFile &&
119 FileType != TargetMachine::ObjectFile) return true;
121 // FIXME: Implement efficient support for garbage collection intrinsics.
122 PM.add(createLowerGCPass());
124 // FIXME: Implement the invoke/unwind instructions!
125 PM.add(createLowerInvokePass());
127 // FIXME: Implement the switch instruction in the instruction selector!
128 PM.add(createLowerSwitchPass());
130 // Make sure that no unreachable blocks are instruction selected.
131 PM.add(createUnreachableBlockEliminationPass());
133 // Install an instruction selector.
135 PM.add(createX86ISelDag(*this));
137 PM.add(createX86ISelPattern(*this));
139 // Print the instruction selected machine code...
140 if (PrintMachineCode)
141 PM.add(createMachineFunctionPrinterPass(&std::cerr));
143 // Perform register allocation to convert to a concrete x86 representation
144 PM.add(createRegisterAllocator());
146 if (PrintMachineCode)
147 PM.add(createMachineFunctionPrinterPass(&std::cerr));
149 PM.add(createX86FloatingPointStackifierPass());
151 if (PrintMachineCode)
152 PM.add(createMachineFunctionPrinterPass(&std::cerr));
154 // Insert prolog/epilog code. Eliminate abstract frame index references...
155 PM.add(createPrologEpilogCodeInserter());
157 PM.add(createX86PeepholeOptimizerPass());
159 if (PrintMachineCode) // Print the register-allocated code
160 PM.add(createX86CodePrinterPass(std::cerr, *this));
165 assert(0 && "Unexpected filetype here!");
166 case TargetMachine::AssemblyFile:
167 PM.add(createX86CodePrinterPass(Out, *this));
169 case TargetMachine::ObjectFile:
170 // FIXME: We only support emission of ELF files for now, this should check
171 // the target triple and decide on the format to write (e.g. COFF on
173 addX86ELFObjectWriterPass(PM, Out, *this);
177 // Delete machine code for this function
178 PM.add(createMachineCodeDeleter());
180 return false; // success!
183 /// addPassesToJITCompile - Add passes to the specified pass manager to
184 /// implement a fast dynamic compiler for this target. Return true if this is
185 /// not supported for this target.
187 void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
188 // FIXME: Implement efficient support for garbage collection intrinsics.
189 PM.add(createLowerGCPass());
191 // FIXME: Implement the invoke/unwind instructions!
192 PM.add(createLowerInvokePass());
194 // FIXME: Implement the switch instruction in the instruction selector!
195 PM.add(createLowerSwitchPass());
197 // Make sure that no unreachable blocks are instruction selected.
198 PM.add(createUnreachableBlockEliminationPass());
200 // Install an instruction selector.
202 PM.add(createX86ISelDag(TM));
204 PM.add(createX86ISelPattern(TM));
206 // FIXME: Add SSA based peephole optimizer here.
208 // Print the instruction selected machine code...
209 if (PrintMachineCode)
210 PM.add(createMachineFunctionPrinterPass(&std::cerr));
212 // Perform register allocation to convert to a concrete x86 representation
213 PM.add(createRegisterAllocator());
215 if (PrintMachineCode)
216 PM.add(createMachineFunctionPrinterPass(&std::cerr));
218 PM.add(createX86FloatingPointStackifierPass());
220 if (PrintMachineCode)
221 PM.add(createMachineFunctionPrinterPass(&std::cerr));
223 // Insert prolog/epilog code. Eliminate abstract frame index references...
224 PM.add(createPrologEpilogCodeInserter());
226 PM.add(createX86PeepholeOptimizerPass());
228 if (PrintMachineCode) // Print the register-allocated code
229 PM.add(createX86CodePrinterPass(std::cerr, TM));
232 bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
233 MachineCodeEmitter &MCE) {
234 PM.add(createX86CodeEmitterPass(MCE));
235 // Delete machine code for this function
236 PM.add(createMachineCodeDeleter());