1 //=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/CallingConv.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 /// PICStyle - Which PIC style to use
54 PICStyles::Style PICStyle;
56 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
58 X86SSEEnum X86SSELevel;
60 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
62 X863DNowEnum X863DNowLevel;
64 /// HasCMov - True if this processor has conditional move instructions
65 /// (generally pentium pro+).
68 /// HasX86_64 - True if the processor supports X86-64 instructions.
72 /// HasPOPCNT - True if the processor supports POPCNT.
75 /// HasSSE4A - True if the processor supports SSE4A instructions.
78 /// HasAVX - Target has AVX instructions
81 /// HasAVX2 - Target has AVX2 instructions
84 /// HasAES - Target has AES instructions
87 /// HasCLMUL - Target has carry-less multiplication
90 /// HasFMA3 - Target has 3-operand fused multiply-add
93 /// HasFMA4 - Target has 4-operand fused multiply-add
96 /// HasMOVBE - True if the processor has the MOVBE instruction.
99 /// HasRDRAND - True if the processor has the RDRAND instruction.
102 /// HasF16C - Processor has 16-bit floating point conversion instructions.
105 /// HasFSGSBase - Processor has FS/GS base insturctions.
108 /// HasLZCNT - Processor has LZCNT instruction.
111 /// HasBMI - Processor has BMI1 instructions.
114 /// HasBMI2 - Processor has BMI2 instructions.
117 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
120 /// IsUAMemFast - True if unaligned memory access is fast.
123 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
124 /// operands. This may require setting a feature bit in the processor.
127 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
128 /// this is true for most x86-64 chips, but not the first AMD chips.
131 /// stackAlignment - The minimum alignment known to hold of the stack frame on
132 /// entry to the function and which must be maintained by every function.
133 unsigned stackAlignment;
135 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
137 unsigned MaxInlineSizeThreshold;
139 /// TargetTriple - What processor and OS we're targeting.
143 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
148 /// This constructor initializes the data members to match that
149 /// of the specified triple.
151 X86Subtarget(const std::string &TT, const std::string &CPU,
152 const std::string &FS,
153 unsigned StackAlignOverride, bool is64Bit);
155 /// getStackAlignment - Returns the minimum alignment known to hold of the
156 /// stack frame on entry to the function and which must be maintained by every
157 /// function for this subtarget.
158 unsigned getStackAlignment() const { return stackAlignment; }
160 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
161 /// that still makes it profitable to inline the call.
162 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
164 /// ParseSubtargetFeatures - Parses features string setting specified
165 /// subtarget options. Definition of function is auto generated by tblgen.
166 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
168 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
170 void AutoDetectSubtargetFeatures();
172 bool is64Bit() const { return In64BitMode; }
174 PICStyles::Style getPICStyle() const { return PICStyle; }
175 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
177 bool hasCMov() const { return HasCMov; }
178 bool hasMMX() const { return X86SSELevel >= MMX; }
179 bool hasSSE1() const { return X86SSELevel >= SSE1; }
180 bool hasSSE2() const { return X86SSELevel >= SSE2; }
181 bool hasSSE3() const { return X86SSELevel >= SSE3; }
182 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
183 bool hasSSE41() const { return X86SSELevel >= SSE41; }
184 bool hasSSE42() const { return X86SSELevel >= SSE42; }
185 bool hasSSE4A() const { return HasSSE4A; }
186 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
187 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
188 bool hasPOPCNT() const { return HasPOPCNT; }
189 bool hasAVX() const { return HasAVX; }
190 bool hasAVX2() const { return HasAVX2; }
191 bool hasXMM() const { return hasSSE1() || hasAVX(); }
192 bool hasXMMInt() const { return hasSSE2() || hasAVX(); }
193 bool hasSSE3orAVX() const { return hasSSE3() || hasAVX(); }
194 bool hasSSSE3orAVX() const { return hasSSSE3() || hasAVX(); }
195 bool hasSSE41orAVX() const { return hasSSE41() || hasAVX(); }
196 bool hasSSE42orAVX() const { return hasSSE42() || hasAVX(); }
197 bool hasAES() const { return HasAES; }
198 bool hasCLMUL() const { return HasCLMUL; }
199 bool hasFMA3() const { return HasFMA3; }
200 bool hasFMA4() const { return HasFMA4; }
201 bool hasMOVBE() const { return HasMOVBE; }
202 bool hasRDRAND() const { return HasRDRAND; }
203 bool hasF16C() const { return HasF16C; }
204 bool hasFSGSBase() const { return HasFSGSBase; }
205 bool hasLZCNT() const { return HasLZCNT; }
206 bool hasBMI() const { return HasBMI; }
207 bool hasBMI2() const { return HasBMI2; }
208 bool isBTMemSlow() const { return IsBTMemSlow; }
209 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
210 bool hasVectorUAMem() const { return HasVectorUAMem; }
211 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
213 const Triple &getTargetTriple() const { return TargetTriple; }
215 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
216 bool isTargetFreeBSD() const {
217 return TargetTriple.getOS() == Triple::FreeBSD;
219 bool isTargetSolaris() const {
220 return TargetTriple.getOS() == Triple::Solaris;
223 // ELF is a reasonably sane default and the only other X86 targets we
224 // support are Darwin and Windows. Just use "not those".
225 bool isTargetELF() const {
226 return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
228 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
229 bool isTargetNaCl() const {
230 return TargetTriple.getOS() == Triple::NativeClient;
232 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
233 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
235 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
236 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
237 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
238 bool isTargetCygMing() const {
239 return isTargetMingw() || isTargetCygwin();
242 /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
243 bool isTargetCOFF() const {
244 return isTargetMingw() || isTargetCygwin() || isTargetWindows();
247 bool isTargetWin64() const {
248 // FIXME: x86_64-cygwin has not been released yet.
249 return In64BitMode && (isTargetCygMing() || isTargetWindows());
252 bool isTargetEnvMacho() const {
253 return isTargetDarwin() || (TargetTriple.getEnvironment() == Triple::MachO);
256 bool isTargetWin32() const {
257 return !In64BitMode && (isTargetMingw() || isTargetWindows());
260 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
261 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
262 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
264 bool isPICStyleStubPIC() const {
265 return PICStyle == PICStyles::StubPIC;
268 bool isPICStyleStubNoDynamic() const {
269 return PICStyle == PICStyles::StubDynamicNoPIC;
271 bool isPICStyleStubAny() const {
272 return PICStyle == PICStyles::StubDynamicNoPIC ||
273 PICStyle == PICStyles::StubPIC; }
275 /// ClassifyGlobalReference - Classify a global variable reference for the
276 /// current subtarget according to how we should reference it in a non-pcrel
278 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
279 const TargetMachine &TM)const;
281 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
282 /// current subtarget according to how we should reference it in a non-pcrel
284 unsigned char ClassifyBlockAddressReference() const;
286 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
287 /// to immediate address.
288 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
290 /// This function returns the name of a function which has an interface
291 /// like the non-standard bzero function, if such a function exists on
292 /// the current subtarget and it is considered prefereable over
293 /// memset with zero passed as the second argument. Otherwise it
295 const char *getBZeroEntry() const;
297 /// getSpecialAddressLatency - For targets where it is beneficial to
298 /// backschedule instructions that compute addresses, return a value
299 /// indicating the number of scheduling cycles of backscheduling that
300 /// should be attempted.
301 unsigned getSpecialAddressLatency() const;
304 } // End llvm namespace