1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// PICStyles - The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86ProcFamily - X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// PICStyle - Which PIC style to use
66 PICStyles::Style PICStyle;
68 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
70 X86SSEEnum X86SSELevel;
72 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
74 X863DNowEnum X863DNowLevel;
76 /// HasCMov - True if this processor has conditional move instructions
77 /// (generally pentium pro+).
80 /// HasX86_64 - True if the processor supports X86-64 instructions.
84 /// HasPOPCNT - True if the processor supports POPCNT.
87 /// HasSSE4A - True if the processor supports SSE4A instructions.
90 /// HasAES - Target has AES instructions
93 /// HasPCLMUL - Target has carry-less multiplication
96 /// HasFMA - Target has 3-operand fused multiply-add
99 /// HasFMA4 - Target has 4-operand fused multiply-add
102 /// HasXOP - Target has XOP instructions
105 /// HasTBM - Target has TBM instructions.
108 /// HasMOVBE - True if the processor has the MOVBE instruction.
111 /// HasRDRAND - True if the processor has the RDRAND instruction.
114 /// HasF16C - Processor has 16-bit floating point conversion instructions.
117 /// HasFSGSBase - Processor has FS/GS base insturctions.
120 /// HasLZCNT - Processor has LZCNT instruction.
123 /// HasBMI - Processor has BMI1 instructions.
126 /// HasBMI2 - Processor has BMI2 instructions.
129 /// HasRTM - Processor has RTM instructions.
132 /// HasHLE - Processor has HLE.
135 /// HasADX - Processor has ADX instructions.
138 /// HasSHA - Processor has SHA instructions.
141 /// HasSGX - Processor has SGX instructions.
144 /// HasPRFCHW - Processor has PRFCHW instructions.
147 /// HasRDSEED - Processor has RDSEED instructions.
150 /// HasSMAP - Processor has SMAP instructions.
153 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
156 /// IsSHLDSlow - True if SHLD instructions are slow.
159 /// IsUAMemFast - True if unaligned memory access is fast.
162 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
163 /// operands. This may require setting a feature bit in the processor.
166 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
167 /// this is true for most x86-64 chips, but not the first AMD chips.
170 /// UseLeaForSP - True if the LEA instruction should be used for adjusting
171 /// the stack pointer. This is an optimization for Intel Atom processors.
174 /// HasSlowDivide - True if smaller divides are significantly faster than
175 /// full divides and should be used when possible.
178 /// PadShortFunctions - True if the short functions should be padded to prevent
179 /// a stall when returning too early.
180 bool PadShortFunctions;
182 /// CallRegIndirect - True if the Calls with memory reference should be converted
183 /// to a register-based indirect call.
184 bool CallRegIndirect;
185 /// LEAUsesAG - True if the LEA instruction inputs have to be ready at
186 /// address generation (AG) time.
189 /// SlowLEA - True if the LEA instruction with certain arguments is slow
192 /// SlowIncDec - True if INC and DEC instructions are slow when writing to flags
195 /// Processor has AVX-512 PreFetch Instructions
198 /// Processor has AVX-512 Exponential and Reciprocal Instructions
201 /// Processor has AVX-512 Conflict Detection Instructions
204 /// Processor has AVX-512 Doubleword and Quadword instructions
207 /// Processor has AVX-512 Byte and Word instructions
210 /// Processor has AVX-512 Vector Length eXtenstions
213 /// stackAlignment - The minimum alignment known to hold of the stack frame on
214 /// entry to the function and which must be maintained by every function.
215 unsigned stackAlignment;
217 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
219 unsigned MaxInlineSizeThreshold;
221 /// TargetTriple - What processor and OS we're targeting.
224 /// Instruction itineraries for scheduling
225 InstrItineraryData InstrItins;
228 // Calculates type size & alignment
231 /// StackAlignOverride - Override the stack alignment.
232 unsigned StackAlignOverride;
234 /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit.
237 /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit.
240 /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit.
243 X86SelectionDAGInfo TSInfo;
244 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
245 // X86TargetLowering needs.
246 X86InstrInfo InstrInfo;
247 X86TargetLowering TLInfo;
248 X86FrameLowering FrameLowering;
251 /// This constructor initializes the data members to match that
252 /// of the specified triple.
254 X86Subtarget(const std::string &TT, const std::string &CPU,
255 const std::string &FS, X86TargetMachine &TM,
256 unsigned StackAlignOverride);
258 const X86TargetLowering *getTargetLowering() const override {
261 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
262 const DataLayout *getDataLayout() const override { return &DL; }
263 const X86FrameLowering *getFrameLowering() const override {
264 return &FrameLowering;
266 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
269 const X86RegisterInfo *getRegisterInfo() const override {
270 return &getInstrInfo()->getRegisterInfo();
273 /// getStackAlignment - Returns the minimum alignment known to hold of the
274 /// stack frame on entry to the function and which must be maintained by every
275 /// function for this subtarget.
276 unsigned getStackAlignment() const { return stackAlignment; }
278 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
279 /// that still makes it profitable to inline the call.
280 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
282 /// ParseSubtargetFeatures - Parses features string setting specified
283 /// subtarget options. Definition of function is auto generated by tblgen.
284 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
287 /// \brief Initialize the full set of dependencies so we can use an initializer
288 /// list for X86Subtarget.
289 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
290 void initializeEnvironment();
291 void initSubtargetFeatures(StringRef CPU, StringRef FS);
293 /// Is this x86_64? (disregarding specific ABI / programming model)
294 bool is64Bit() const {
298 bool is32Bit() const {
302 bool is16Bit() const {
306 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
307 bool isTarget64BitILP32() const {
308 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
309 TargetTriple.getOS() == Triple::NaCl);
312 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
313 bool isTarget64BitLP64() const {
314 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
315 TargetTriple.getOS() != Triple::NaCl);
318 PICStyles::Style getPICStyle() const { return PICStyle; }
319 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
321 bool hasCMov() const { return HasCMov; }
322 bool hasMMX() const { return X86SSELevel >= MMX; }
323 bool hasSSE1() const { return X86SSELevel >= SSE1; }
324 bool hasSSE2() const { return X86SSELevel >= SSE2; }
325 bool hasSSE3() const { return X86SSELevel >= SSE3; }
326 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
327 bool hasSSE41() const { return X86SSELevel >= SSE41; }
328 bool hasSSE42() const { return X86SSELevel >= SSE42; }
329 bool hasAVX() const { return X86SSELevel >= AVX; }
330 bool hasAVX2() const { return X86SSELevel >= AVX2; }
331 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
332 bool hasFp256() const { return hasAVX(); }
333 bool hasInt256() const { return hasAVX2(); }
334 bool hasSSE4A() const { return HasSSE4A; }
335 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
336 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
337 bool hasPOPCNT() const { return HasPOPCNT; }
338 bool hasAES() const { return HasAES; }
339 bool hasPCLMUL() const { return HasPCLMUL; }
340 bool hasFMA() const { return HasFMA; }
341 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
342 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
343 bool hasXOP() const { return HasXOP; }
344 bool hasTBM() const { return HasTBM; }
345 bool hasMOVBE() const { return HasMOVBE; }
346 bool hasRDRAND() const { return HasRDRAND; }
347 bool hasF16C() const { return HasF16C; }
348 bool hasFSGSBase() const { return HasFSGSBase; }
349 bool hasLZCNT() const { return HasLZCNT; }
350 bool hasBMI() const { return HasBMI; }
351 bool hasBMI2() const { return HasBMI2; }
352 bool hasRTM() const { return HasRTM; }
353 bool hasHLE() const { return HasHLE; }
354 bool hasADX() const { return HasADX; }
355 bool hasSHA() const { return HasSHA; }
356 bool hasSGX() const { return HasSGX; }
357 bool hasPRFCHW() const { return HasPRFCHW; }
358 bool hasRDSEED() const { return HasRDSEED; }
359 bool hasSMAP() const { return HasSMAP; }
360 bool isBTMemSlow() const { return IsBTMemSlow; }
361 bool isSHLDSlow() const { return IsSHLDSlow; }
362 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
363 bool hasVectorUAMem() const { return HasVectorUAMem; }
364 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
365 bool useLeaForSP() const { return UseLeaForSP; }
366 bool hasSlowDivide() const { return HasSlowDivide; }
367 bool padShortFunctions() const { return PadShortFunctions; }
368 bool callRegIndirect() const { return CallRegIndirect; }
369 bool LEAusesAG() const { return LEAUsesAG; }
370 bool slowLEA() const { return SlowLEA; }
371 bool slowIncDec() const { return SlowIncDec; }
372 bool hasCDI() const { return HasCDI; }
373 bool hasPFI() const { return HasPFI; }
374 bool hasERI() const { return HasERI; }
375 bool hasDQI() const { return HasDQI; }
376 bool hasBWI() const { return HasBWI; }
377 bool hasVLX() const { return HasVLX; }
379 bool isAtom() const { return X86ProcFamily == IntelAtom; }
380 bool isSLM() const { return X86ProcFamily == IntelSLM; }
382 const Triple &getTargetTriple() const { return TargetTriple; }
384 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
385 bool isTargetFreeBSD() const {
386 return TargetTriple.getOS() == Triple::FreeBSD;
388 bool isTargetSolaris() const {
389 return TargetTriple.getOS() == Triple::Solaris;
392 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
393 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
394 bool isTargetMacho() const { return TargetTriple.isOSBinFormatMachO(); }
396 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
397 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
398 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
399 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
401 bool isTargetWindowsMSVC() const {
402 return TargetTriple.isWindowsMSVCEnvironment();
405 bool isTargetKnownWindowsMSVC() const {
406 return TargetTriple.isKnownWindowsMSVCEnvironment();
409 bool isTargetWindowsCygwin() const {
410 return TargetTriple.isWindowsCygwinEnvironment();
413 bool isTargetWindowsGNU() const {
414 return TargetTriple.isWindowsGNUEnvironment();
417 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
419 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
421 bool isTargetWin64() const {
422 return In64BitMode && TargetTriple.isOSWindows();
425 bool isTargetWin32() const {
426 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
429 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
430 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
431 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
433 bool isPICStyleStubPIC() const {
434 return PICStyle == PICStyles::StubPIC;
437 bool isPICStyleStubNoDynamic() const {
438 return PICStyle == PICStyles::StubDynamicNoPIC;
440 bool isPICStyleStubAny() const {
441 return PICStyle == PICStyles::StubDynamicNoPIC ||
442 PICStyle == PICStyles::StubPIC;
445 bool isCallingConvWin64(CallingConv::ID CC) const {
446 return (isTargetWin64() && CC != CallingConv::X86_64_SysV) ||
447 CC == CallingConv::X86_64_Win64;
450 /// ClassifyGlobalReference - Classify a global variable reference for the
451 /// current subtarget according to how we should reference it in a non-pcrel
453 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
454 const TargetMachine &TM)const;
456 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
457 /// current subtarget according to how we should reference it in a non-pcrel
459 unsigned char ClassifyBlockAddressReference() const;
461 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
462 /// to immediate address.
463 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
465 /// This function returns the name of a function which has an interface
466 /// like the non-standard bzero function, if such a function exists on
467 /// the current subtarget and it is considered prefereable over
468 /// memset with zero passed as the second argument. Otherwise it
470 const char *getBZeroEntry() const;
472 /// This function returns true if the target has sincos() routine in its
473 /// compiler runtime or math libraries.
474 bool hasSinCos() const;
476 /// Enable the MachineScheduler pass for all X86 subtargets.
477 bool enableMachineScheduler() const override { return true; }
479 bool enableEarlyIfConversion() const override;
481 /// getInstrItins = Return the instruction itineraries based on the
482 /// subtarget selection.
483 const InstrItineraryData *getInstrItineraryData() const override {
487 AntiDepBreakMode getAntiDepBreakMode() const override {
488 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
492 } // End llvm namespace