1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
17 #include "X86FrameLowering.h"
18 #include "X86ISelLowering.h"
19 #include "X86InstrInfo.h"
20 #include "X86SelectionDAGInfo.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
34 /// The X86 backend supports a number of different styles of PIC.
38 StubPIC, // Used on i386-darwin in -fPIC mode.
39 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
40 GOT, // Used on many 32-bit unices in -fPIC mode.
41 RIPRel, // Used on X86-64 when not in -static mode.
42 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
46 class X86Subtarget final : public X86GenSubtargetInfo {
50 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
54 NoThreeDNow, ThreeDNow, ThreeDNowA
57 enum X86ProcFamilyEnum {
58 Others, IntelAtom, IntelSLM
61 /// X86 processor family: Intel Atom, and others
62 X86ProcFamilyEnum X86ProcFamily;
64 /// Which PIC style to use
65 PICStyles::Style PICStyle;
67 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
68 X86SSEEnum X86SSELevel;
70 /// 3DNow, 3DNow Athlon, or none supported.
71 X863DNowEnum X863DNowLevel;
73 /// True if this processor has conditional move instructions
74 /// (generally pentium pro+).
77 /// True if this processor supports MMX instructions.
80 /// True if the processor supports X86-64 instructions.
83 /// True if the processor supports POPCNT.
86 /// True if the processor supports SSE4A instructions.
89 /// Target has AES instructions
92 /// Target has FXSAVE/FXRESTOR instructions
95 /// Target has XSAVE instructions
97 /// Target has XSAVEOPT instructions
99 /// Target has XSAVEC instructions
101 /// Target has XSAVES instructions
104 /// Target has carry-less multiplication
107 /// Target has 3-operand fused multiply-add
110 /// Target has 4-operand fused multiply-add
113 /// Target has XOP instructions
116 /// Target has TBM instructions.
119 /// True if the processor has the MOVBE instruction.
122 /// True if the processor has the RDRAND instruction.
125 /// Processor has 16-bit floating point conversion instructions.
128 /// Processor has FS/GS base insturctions.
131 /// Processor has LZCNT instruction.
134 /// Processor has BMI1 instructions.
137 /// Processor has BMI2 instructions.
140 /// Processor has RTM instructions.
143 /// Processor has HLE.
146 /// Processor has ADX instructions.
149 /// Processor has SHA instructions.
152 /// Processor has PRFCHW instructions.
155 /// Processor has RDSEED instructions.
158 /// True if BT (bit test) of memory instructions are slow.
161 /// True if SHLD instructions are slow.
164 /// True if unaligned memory accesses of 16-bytes are slow.
167 /// True if unaligned memory accesses of 32-bytes are slow.
170 /// True if SSE operations can have unaligned memory operands.
171 /// This may require setting a configuration bit in the processor.
172 bool HasSSEUnalignedMem;
174 /// True if this processor has the CMPXCHG16B instruction;
175 /// this is true for most x86-64 chips, but not the first AMD chips.
178 /// True if the LEA instruction should be used for adjusting
179 /// the stack pointer. This is an optimization for Intel Atom processors.
182 /// True if 8-bit divisions are significantly faster than
183 /// 32-bit divisions and should be used when possible.
184 bool HasSlowDivide32;
186 /// True if 16-bit divides are significantly faster than
187 /// 64-bit divisions and should be used when possible.
188 bool HasSlowDivide64;
190 /// True if the short functions should be padded to prevent
191 /// a stall when returning too early.
192 bool PadShortFunctions;
194 /// True if the Calls with memory reference should be converted
195 /// to a register-based indirect call.
196 bool CallRegIndirect;
198 /// True if the LEA instruction inputs have to be ready at address generation
202 /// True if the LEA instruction with certain arguments is slow
205 /// True if INC and DEC instructions are slow when writing to flags
208 /// Processor has AVX-512 PreFetch Instructions
211 /// Processor has AVX-512 Exponential and Reciprocal Instructions
214 /// Processor has AVX-512 Conflict Detection Instructions
217 /// Processor has AVX-512 Doubleword and Quadword instructions
220 /// Processor has AVX-512 Byte and Word instructions
223 /// Processor has AVX-512 Vector Length eXtenstions
226 /// Processot supports MPX - Memory Protection Extensions
229 /// Use software floating point for code generation.
232 /// The minimum alignment known to hold of the stack frame on
233 /// entry to the function and which must be maintained by every function.
234 unsigned stackAlignment;
236 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
238 unsigned MaxInlineSizeThreshold;
240 /// What processor and OS we're targeting.
243 /// Instruction itineraries for scheduling
244 InstrItineraryData InstrItins;
248 /// Override the stack alignment.
249 unsigned StackAlignOverride;
251 /// True if compiling for 64-bit, false for 16-bit or 32-bit.
254 /// True if compiling for 32-bit, false for 16-bit or 64-bit.
257 /// True if compiling for 16-bit, false for 32-bit or 64-bit.
260 X86SelectionDAGInfo TSInfo;
261 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
262 // X86TargetLowering needs.
263 X86InstrInfo InstrInfo;
264 X86TargetLowering TLInfo;
265 X86FrameLowering FrameLowering;
268 /// This constructor initializes the data members to match that
269 /// of the specified triple.
271 X86Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
272 const X86TargetMachine &TM, unsigned StackAlignOverride);
274 const X86TargetLowering *getTargetLowering() const override {
277 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
278 const X86FrameLowering *getFrameLowering() const override {
279 return &FrameLowering;
281 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
284 const X86RegisterInfo *getRegisterInfo() const override {
285 return &getInstrInfo()->getRegisterInfo();
288 /// Returns the minimum alignment known to hold of the
289 /// stack frame on entry to the function and which must be maintained by every
290 /// function for this subtarget.
291 unsigned getStackAlignment() const { return stackAlignment; }
293 /// Returns the maximum memset / memcpy size
294 /// that still makes it profitable to inline the call.
295 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
297 /// ParseSubtargetFeatures - Parses features string setting specified
298 /// subtarget options. Definition of function is auto generated by tblgen.
299 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
302 /// Initialize the full set of dependencies so we can use an initializer
303 /// list for X86Subtarget.
304 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
305 void initializeEnvironment();
306 void initSubtargetFeatures(StringRef CPU, StringRef FS);
308 /// Is this x86_64? (disregarding specific ABI / programming model)
309 bool is64Bit() const {
313 bool is32Bit() const {
317 bool is16Bit() const {
321 /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
322 bool isTarget64BitILP32() const {
323 return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
324 TargetTriple.isOSNaCl());
327 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
328 bool isTarget64BitLP64() const {
329 return In64BitMode && (TargetTriple.getEnvironment() != Triple::GNUX32 &&
330 !TargetTriple.isOSNaCl());
333 PICStyles::Style getPICStyle() const { return PICStyle; }
334 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
336 bool hasCMov() const { return HasCMov; }
337 bool hasMMX() const { return HasMMX; }
338 bool hasSSE1() const { return X86SSELevel >= SSE1; }
339 bool hasSSE2() const { return X86SSELevel >= SSE2; }
340 bool hasSSE3() const { return X86SSELevel >= SSE3; }
341 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
342 bool hasSSE41() const { return X86SSELevel >= SSE41; }
343 bool hasSSE42() const { return X86SSELevel >= SSE42; }
344 bool hasAVX() const { return X86SSELevel >= AVX; }
345 bool hasAVX2() const { return X86SSELevel >= AVX2; }
346 bool hasAVX512() const { return X86SSELevel >= AVX512F; }
347 bool hasFp256() const { return hasAVX(); }
348 bool hasInt256() const { return hasAVX2(); }
349 bool hasSSE4A() const { return HasSSE4A; }
350 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
351 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
352 bool hasPOPCNT() const { return HasPOPCNT; }
353 bool hasAES() const { return HasAES; }
354 bool hasFXSR() const { return HasFXSR; }
355 bool hasXSAVE() const { return HasXSAVE; }
356 bool hasXSAVEOPT() const { return HasXSAVEOPT; }
357 bool hasXSAVEC() const { return HasXSAVEC; }
358 bool hasXSAVES() const { return HasXSAVES; }
359 bool hasPCLMUL() const { return HasPCLMUL; }
360 bool hasFMA() const { return HasFMA; }
361 // FIXME: Favor FMA when both are enabled. Is this the right thing to do?
362 bool hasFMA4() const { return HasFMA4 && !HasFMA; }
363 bool hasXOP() const { return HasXOP; }
364 bool hasTBM() const { return HasTBM; }
365 bool hasMOVBE() const { return HasMOVBE; }
366 bool hasRDRAND() const { return HasRDRAND; }
367 bool hasF16C() const { return HasF16C; }
368 bool hasFSGSBase() const { return HasFSGSBase; }
369 bool hasLZCNT() const { return HasLZCNT; }
370 bool hasBMI() const { return HasBMI; }
371 bool hasBMI2() const { return HasBMI2; }
372 bool hasRTM() const { return HasRTM; }
373 bool hasHLE() const { return HasHLE; }
374 bool hasADX() const { return HasADX; }
375 bool hasSHA() const { return HasSHA; }
376 bool hasPRFCHW() const { return HasPRFCHW; }
377 bool hasRDSEED() const { return HasRDSEED; }
378 bool isBTMemSlow() const { return IsBTMemSlow; }
379 bool isSHLDSlow() const { return IsSHLDSlow; }
380 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
381 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
382 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
383 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
384 bool useLeaForSP() const { return UseLeaForSP; }
385 bool hasSlowDivide32() const { return HasSlowDivide32; }
386 bool hasSlowDivide64() const { return HasSlowDivide64; }
387 bool padShortFunctions() const { return PadShortFunctions; }
388 bool callRegIndirect() const { return CallRegIndirect; }
389 bool LEAusesAG() const { return LEAUsesAG; }
390 bool slowLEA() const { return SlowLEA; }
391 bool slowIncDec() const { return SlowIncDec; }
392 bool hasCDI() const { return HasCDI; }
393 bool hasPFI() const { return HasPFI; }
394 bool hasERI() const { return HasERI; }
395 bool hasDQI() const { return HasDQI; }
396 bool hasBWI() const { return HasBWI; }
397 bool hasVLX() const { return HasVLX; }
398 bool hasMPX() const { return HasMPX; }
400 bool isAtom() const { return X86ProcFamily == IntelAtom; }
401 bool isSLM() const { return X86ProcFamily == IntelSLM; }
402 bool useSoftFloat() const { return UseSoftFloat; }
404 const Triple &getTargetTriple() const { return TargetTriple; }
406 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
407 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
408 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
409 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
410 bool isTargetPS4() const { return TargetTriple.isPS4(); }
412 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
413 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
414 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
416 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
417 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
418 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
419 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
420 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
421 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
423 bool isTargetWindowsMSVC() const {
424 return TargetTriple.isWindowsMSVCEnvironment();
427 bool isTargetKnownWindowsMSVC() const {
428 return TargetTriple.isKnownWindowsMSVCEnvironment();
431 bool isTargetWindowsCoreCLR() const {
432 return TargetTriple.isWindowsCoreCLREnvironment();
435 bool isTargetWindowsCygwin() const {
436 return TargetTriple.isWindowsCygwinEnvironment();
439 bool isTargetWindowsGNU() const {
440 return TargetTriple.isWindowsGNUEnvironment();
443 bool isTargetWindowsItanium() const {
444 return TargetTriple.isWindowsItaniumEnvironment();
447 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
449 bool isOSWindows() const { return TargetTriple.isOSWindows(); }
451 bool isTargetWin64() const {
452 return In64BitMode && TargetTriple.isOSWindows();
455 bool isTargetWin32() const {
456 return !In64BitMode && (isTargetCygMing() || isTargetKnownWindowsMSVC());
459 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
460 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
461 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
463 bool isPICStyleStubPIC() const {
464 return PICStyle == PICStyles::StubPIC;
467 bool isPICStyleStubNoDynamic() const {
468 return PICStyle == PICStyles::StubDynamicNoPIC;
470 bool isPICStyleStubAny() const {
471 return PICStyle == PICStyles::StubDynamicNoPIC ||
472 PICStyle == PICStyles::StubPIC;
475 bool isCallingConvWin64(CallingConv::ID CC) const {
477 // On Win64, all these conventions just use the default convention.
479 case CallingConv::Fast:
480 case CallingConv::X86_FastCall:
481 case CallingConv::X86_StdCall:
482 case CallingConv::X86_ThisCall:
483 case CallingConv::X86_VectorCall:
484 case CallingConv::Intel_OCL_BI:
485 return isTargetWin64();
486 // This convention allows using the Win64 convention on other targets.
487 case CallingConv::X86_64_Win64:
489 // This convention allows using the SysV convention on Windows targets.
490 case CallingConv::X86_64_SysV:
492 // Otherwise, who knows what this is.
498 /// ClassifyGlobalReference - Classify a global variable reference for the
499 /// current subtarget according to how we should reference it in a non-pcrel
501 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
502 const TargetMachine &TM)const;
504 /// Classify a blockaddress reference for the current subtarget according to
505 /// how we should reference it in a non-pcrel context.
506 unsigned char ClassifyBlockAddressReference() const;
508 /// Return true if the subtarget allows calls to immediate address.
509 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
511 /// This function returns the name of a function which has an interface
512 /// like the non-standard bzero function, if such a function exists on
513 /// the current subtarget and it is considered prefereable over
514 /// memset with zero passed as the second argument. Otherwise it
516 const char *getBZeroEntry() const;
518 /// This function returns true if the target has sincos() routine in its
519 /// compiler runtime or math libraries.
520 bool hasSinCos() const;
522 /// Enable the MachineScheduler pass for all X86 subtargets.
523 bool enableMachineScheduler() const override { return true; }
525 bool enableEarlyIfConversion() const override;
527 /// Return the instruction itineraries based on the subtarget selection.
528 const InstrItineraryData *getInstrItineraryData() const override {
532 AntiDepBreakMode getAntiDepBreakMode() const override {
533 return TargetSubtargetInfo::ANTIDEP_CRITICAL;
537 } // End llvm namespace