1 //=====---- X86Subtarget.h - Define Subtarget for the X86 -----*- C++ -*--====//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the X86 specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #ifndef X86SUBTARGET_H
15 #define X86SUBTARGET_H
17 #include "llvm/ADT/Triple.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/CallingConv.h"
22 #define GET_SUBTARGETINFO_HEADER
23 #include "X86GenSubtargetInfo.inc"
30 /// PICStyles - The X86 backend supports a number of different styles of PIC.
34 StubPIC, // Used on i386-darwin in -fPIC mode.
35 StubDynamicNoPIC, // Used on i386-darwin in -mdynamic-no-pic mode.
36 GOT, // Used on many 32-bit unices in -fPIC mode.
37 RIPRel, // Used on X86-64 when not in -static mode.
38 None // Set when in -static mode (not PIC or DynamicNoPIC mode).
42 class X86Subtarget : public X86GenSubtargetInfo {
45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
49 NoThreeDNow, ThreeDNow, ThreeDNowA
52 enum X86ProcFamilyEnum {
56 /// X86ProcFamily - X86 processor family: Intel Atom, and others
57 X86ProcFamilyEnum X86ProcFamily;
59 /// PICStyle - Which PIC style to use
61 PICStyles::Style PICStyle;
63 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
65 X86SSEEnum X86SSELevel;
67 /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported.
69 X863DNowEnum X863DNowLevel;
71 /// HasCMov - True if this processor has conditional move instructions
72 /// (generally pentium pro+).
75 /// HasX86_64 - True if the processor supports X86-64 instructions.
79 /// HasPOPCNT - True if the processor supports POPCNT.
82 /// HasSSE4A - True if the processor supports SSE4A instructions.
85 /// HasAES - Target has AES instructions
88 /// HasCLMUL - Target has carry-less multiplication
91 /// HasFMA3 - Target has 3-operand fused multiply-add
94 /// HasFMA4 - Target has 4-operand fused multiply-add
97 /// HasXOP - Target has XOP instructions
100 /// HasMOVBE - True if the processor has the MOVBE instruction.
103 /// HasRDRAND - True if the processor has the RDRAND instruction.
106 /// HasF16C - Processor has 16-bit floating point conversion instructions.
109 /// HasFSGSBase - Processor has FS/GS base insturctions.
112 /// HasLZCNT - Processor has LZCNT instruction.
115 /// HasBMI - Processor has BMI1 instructions.
118 /// HasBMI2 - Processor has BMI2 instructions.
121 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
124 /// IsUAMemFast - True if unaligned memory access is fast.
127 /// HasVectorUAMem - True if SIMD operations can have unaligned memory
128 /// operands. This may require setting a feature bit in the processor.
131 /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction;
132 /// this is true for most x86-64 chips, but not the first AMD chips.
135 /// PostRAScheduler - True if using post-register-allocation scheduler.
136 bool PostRAScheduler;
138 /// stackAlignment - The minimum alignment known to hold of the stack frame on
139 /// entry to the function and which must be maintained by every function.
140 unsigned stackAlignment;
142 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
144 unsigned MaxInlineSizeThreshold;
146 /// TargetTriple - What processor and OS we're targeting.
149 /// Instruction itineraries for scheduling
150 InstrItineraryData InstrItins;
153 /// In64BitMode - True if compiling for 64-bit, false for 32-bit.
158 /// This constructor initializes the data members to match that
159 /// of the specified triple.
161 X86Subtarget(const std::string &TT, const std::string &CPU,
162 const std::string &FS,
163 unsigned StackAlignOverride, bool is64Bit);
165 /// getStackAlignment - Returns the minimum alignment known to hold of the
166 /// stack frame on entry to the function and which must be maintained by every
167 /// function for this subtarget.
168 unsigned getStackAlignment() const { return stackAlignment; }
170 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
171 /// that still makes it profitable to inline the call.
172 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
174 /// ParseSubtargetFeatures - Parses features string setting specified
175 /// subtarget options. Definition of function is auto generated by tblgen.
176 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
178 /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID
180 void AutoDetectSubtargetFeatures();
182 bool is64Bit() const { return In64BitMode; }
184 PICStyles::Style getPICStyle() const { return PICStyle; }
185 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; }
187 bool hasCMov() const { return HasCMov; }
188 bool hasMMX() const { return X86SSELevel >= MMX; }
189 bool hasSSE1() const { return X86SSELevel >= SSE1; }
190 bool hasSSE2() const { return X86SSELevel >= SSE2; }
191 bool hasSSE3() const { return X86SSELevel >= SSE3; }
192 bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
193 bool hasSSE41() const { return X86SSELevel >= SSE41; }
194 bool hasSSE42() const { return X86SSELevel >= SSE42; }
195 bool hasAVX() const { return X86SSELevel >= AVX; }
196 bool hasAVX2() const { return X86SSELevel >= AVX2; }
197 bool hasSSE4A() const { return HasSSE4A; }
198 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
199 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
200 bool hasPOPCNT() const { return HasPOPCNT; }
201 bool hasAES() const { return HasAES; }
202 bool hasCLMUL() const { return HasCLMUL; }
203 bool hasFMA3() const { return HasFMA3; }
204 bool hasFMA4() const { return HasFMA4; }
205 bool hasXOP() const { return HasXOP; }
206 bool hasMOVBE() const { return HasMOVBE; }
207 bool hasRDRAND() const { return HasRDRAND; }
208 bool hasF16C() const { return HasF16C; }
209 bool hasFSGSBase() const { return HasFSGSBase; }
210 bool hasLZCNT() const { return HasLZCNT; }
211 bool hasBMI() const { return HasBMI; }
212 bool hasBMI2() const { return HasBMI2; }
213 bool isBTMemSlow() const { return IsBTMemSlow; }
214 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
215 bool hasVectorUAMem() const { return HasVectorUAMem; }
216 bool hasCmpxchg16b() const { return HasCmpxchg16b; }
218 bool isAtom() const { return X86ProcFamily == IntelAtom; }
220 const Triple &getTargetTriple() const { return TargetTriple; }
222 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
223 bool isTargetFreeBSD() const {
224 return TargetTriple.getOS() == Triple::FreeBSD;
226 bool isTargetSolaris() const {
227 return TargetTriple.getOS() == Triple::Solaris;
230 // ELF is a reasonably sane default and the only other X86 targets we
231 // support are Darwin and Windows. Just use "not those".
232 bool isTargetELF() const {
233 return !isTargetDarwin() && !isTargetWindows() && !isTargetCygMing();
235 bool isTargetLinux() const { return TargetTriple.getOS() == Triple::Linux; }
236 bool isTargetNaCl() const {
237 return TargetTriple.getOS() == Triple::NativeClient;
239 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
240 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
242 bool isTargetWindows() const { return TargetTriple.getOS() == Triple::Win32; }
243 bool isTargetMingw() const { return TargetTriple.getOS() == Triple::MinGW32; }
244 bool isTargetCygwin() const { return TargetTriple.getOS() == Triple::Cygwin; }
245 bool isTargetCygMing() const {
246 return isTargetMingw() || isTargetCygwin();
249 /// isTargetCOFF - Return true if this is any COFF/Windows target variant.
250 bool isTargetCOFF() const {
251 return isTargetMingw() || isTargetCygwin() || isTargetWindows();
254 bool isTargetWin64() const {
255 // FIXME: x86_64-cygwin has not been released yet.
256 return In64BitMode && (isTargetCygMing() || isTargetWindows());
259 bool isTargetEnvMacho() const {
260 return isTargetDarwin() || (TargetTriple.getEnvironment() == Triple::MachO);
263 bool isTargetWin32() const {
264 return !In64BitMode && (isTargetMingw() || isTargetWindows());
267 bool isPICStyleSet() const { return PICStyle != PICStyles::None; }
268 bool isPICStyleGOT() const { return PICStyle == PICStyles::GOT; }
269 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::RIPRel; }
271 bool isPICStyleStubPIC() const {
272 return PICStyle == PICStyles::StubPIC;
275 bool isPICStyleStubNoDynamic() const {
276 return PICStyle == PICStyles::StubDynamicNoPIC;
278 bool isPICStyleStubAny() const {
279 return PICStyle == PICStyles::StubDynamicNoPIC ||
280 PICStyle == PICStyles::StubPIC; }
282 /// ClassifyGlobalReference - Classify a global variable reference for the
283 /// current subtarget according to how we should reference it in a non-pcrel
285 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
286 const TargetMachine &TM)const;
288 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
289 /// current subtarget according to how we should reference it in a non-pcrel
291 unsigned char ClassifyBlockAddressReference() const;
293 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
294 /// to immediate address.
295 bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const;
297 /// This function returns the name of a function which has an interface
298 /// like the non-standard bzero function, if such a function exists on
299 /// the current subtarget and it is considered prefereable over
300 /// memset with zero passed as the second argument. Otherwise it
302 const char *getBZeroEntry() const;
304 /// getSpecialAddressLatency - For targets where it is beneficial to
305 /// backschedule instructions that compute addresses, return a value
306 /// indicating the number of scheduling cycles of backscheduling that
307 /// should be attempted.
308 unsigned getSpecialAddressLatency() const;
310 /// enablePostRAScheduler - run for Atom optimization.
311 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
312 TargetSubtargetInfo::AntiDepBreakMode& Mode,
313 RegClassVector& CriticalPathRCs) const;
315 /// getInstrItins = Return the instruction itineraries based on the
316 /// subtarget selection.
317 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
320 } // End llvm namespace