1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86GenSubtarget.inc"
17 #include "llvm/Module.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
28 static cl::opt<X86Subtarget::AsmWriterFlavorTy>
29 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
30 cl::desc("Choose style of code to emit from X86 backend:"),
32 clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
33 clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
37 /// True if accessing the GV requires an extra load. For Windows, dllimported
38 /// symbols are indirect, loading the value at address GV rather then the
39 /// value of GV itself. This means that the GlobalAddress must be in the base
40 /// or index register of the address, not the GV offset field.
41 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue *GV,
42 const TargetMachine &TM) const {
43 // Windows targets only require an extra load for DLLImport linkage values,
44 // and they need these regardless of whether we're in PIC mode or not.
45 if (isTargetCygMing() || isTargetWindows())
46 return GV->hasDLLImportLinkage();
48 if (TM.getRelocationModel() == Reloc::Static ||
49 TM.getCodeModel() == CodeModel::Large)
52 if (isTargetDarwin()) {
53 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
54 if (GV->hasHiddenVisibility() &&
55 (Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
56 // If symbol visibility is hidden, the extra load is not needed if
57 // target is x86-64 or the symbol is definitely defined in the current
60 return isDecl || GV->isWeakForLinker();
61 } else if (isTargetELF()) {
62 // Extra load is needed for all externally visible.
63 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
70 /// True if accessing the GV requires a register. This is a superset of the
71 /// cases where GVRequiresExtraLoad is true. Some variations of PIC require
72 /// a register, but not an extra load.
73 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
74 const TargetMachine &TM) const {
75 if (GVRequiresExtraLoad(GV, TM))
78 // Code below here need only consider cases where GVRequiresExtraLoad
80 if (TM.getRelocationModel() == Reloc::PIC_)
81 return GV->hasLocalLinkage() || GV->hasExternalLinkage();
85 /// getBZeroEntry - This function returns the name of a function which has an
86 /// interface like the non-standard bzero function, if such a function exists on
87 /// the current subtarget and it is considered prefereable over memset with zero
88 /// passed as the second argument. Otherwise it returns null.
89 const char *X86Subtarget::getBZeroEntry() const {
90 // Darwin 10 has a __bzero entry point for this purpose.
91 if (getDarwinVers() >= 10)
97 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
98 /// to immediate address.
99 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
102 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
105 /// getSpecialAddressLatency - For targets where it is beneficial to
106 /// backschedule instructions that compute addresses, return a value
107 /// indicating the number of scheduling cycles of backscheduling that
108 /// should be attempted.
109 unsigned X86Subtarget::getSpecialAddressLatency() const {
110 // For x86 out-of-order targets, back-schedule address computations so
111 // that loads and stores aren't blocked.
112 // This value was chosen arbitrarily.
116 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
117 /// specified arguments. If we can't run cpuid on the host, return true.
118 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
119 unsigned *rECX, unsigned *rEDX) {
120 #if defined(__x86_64__) || defined(_M_AMD64)
121 #if defined(__GNUC__)
122 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
123 asm ("movq\t%%rbx, %%rsi\n\t"
125 "xchgq\t%%rbx, %%rsi\n\t"
132 #elif defined(_MSC_VER)
134 __cpuid(registers, value);
135 *rEAX = registers[0];
136 *rEBX = registers[1];
137 *rECX = registers[2];
138 *rEDX = registers[3];
141 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
142 #if defined(__GNUC__)
143 asm ("movl\t%%ebx, %%esi\n\t"
145 "xchgl\t%%ebx, %%esi\n\t"
152 #elif defined(_MSC_VER)
157 mov dword ptr [esi],eax
159 mov dword ptr [esi],ebx
161 mov dword ptr [esi],ecx
163 mov dword ptr [esi],edx
171 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
172 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
173 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
174 if (Family == 6 || Family == 0xf) {
176 // Examine extended family ID if family ID is F.
177 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
178 // Examine extended model ID if family ID is 6 or F.
179 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
183 void X86Subtarget::AutoDetectSubtargetFeatures() {
184 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
190 if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
193 X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
195 if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
196 if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
197 if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
198 if (ECX & 0x1) X86SSELevel = SSE3;
199 if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
200 if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
201 if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
203 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
204 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
206 HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
207 HasAVX = ((ECX >> 28) & 0x1);
209 if (IsIntel || IsAMD) {
210 // Determine if bit test memory instructions are slow.
213 DetectFamilyModel(EAX, Family, Model);
214 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
216 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
217 HasX86_64 = (EDX >> 29) & 0x1;
218 HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
219 HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
223 static const char *GetCurrentX86CPU() {
224 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
225 if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
229 DetectFamilyModel(EAX, Family, Model);
231 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
232 bool Em64T = (EDX >> 29) & 0x1;
233 bool HasSSE3 = (ECX & 0x1);
240 X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
241 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
249 case 4: return "pentium-mmx";
250 default: return "pentium";
254 case 1: return "pentiumpro";
257 case 6: return "pentium2";
261 case 11: return "pentium3";
263 case 13: return "pentium-m";
264 case 14: return "yonah";
266 case 22: // Celeron M 540
268 case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
270 default: return "i686";
276 case 6: // same as 4, but 65nm
277 return (Em64T) ? "nocona" : "prescott";
283 return (Em64T) ? "x86-64" : "pentium4";
290 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
291 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
292 // appears to be no way to generate the wide variety of AMD-specific targets
293 // from the information returned from CPUID.
301 case 8: return "k6-2";
303 case 13: return "k6-3";
304 default: return "pentium";
308 case 4: return "athlon-tbird";
311 case 8: return "athlon-mp";
312 case 10: return "athlon-xp";
313 default: return "athlon";
318 default: return "k8-sse3";
322 case 1: return "opteron";
323 case 5: return "athlon-fx"; // also opteron
324 default: return "athlon64";
329 default: return "amdfam10";
339 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
340 : AsmFlavor(AsmWriterFlavor)
341 , PICStyle(PICStyles::None)
342 , X86SSELevel(NoMMXSSE)
343 , X863DNowLevel(NoThreeDNow)
353 // FIXME: this is a known good value for Yonah. How about others?
354 , MaxInlineSizeThreshold(128)
356 , TargetType(isELF) { // Default to ELF unless otherwise specified.
358 // default to hard float ABI
359 if (FloatABIType == FloatABI::Default)
360 FloatABIType = FloatABI::Hard;
362 // Determine default and user specified characteristics
364 // If feature string is not empty, parse features string.
365 std::string CPU = GetCurrentX86CPU();
366 ParseSubtargetFeatures(FS, CPU);
367 // All X86-64 CPUs also have SSE2, however user might request no SSE via
368 // -mattr, so don't force SSELevel here.
370 // Otherwise, use CPUID to auto-detect feature set.
371 AutoDetectSubtargetFeatures();
372 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
373 if (Is64Bit && X86SSELevel < SSE2)
377 // If requesting codegen for X86-64, make sure that 64-bit features
382 DOUT << "Subtarget features: SSELevel " << X86SSELevel
383 << ", 3DNowLevel " << X863DNowLevel
384 << ", 64bit " << HasX86_64 << "\n";
385 assert((!Is64Bit || HasX86_64) &&
386 "64-bit code requested on a subtarget that doesn't support it!");
388 // Set the boolean corresponding to the current target triple, or the default
389 // if one cannot be determined, to true.
390 const std::string& TT = M.getTargetTriple();
391 if (TT.length() > 5) {
393 if ((Pos = TT.find("-darwin")) != std::string::npos) {
394 TargetType = isDarwin;
396 // Compute the darwin version number.
397 if (isdigit(TT[Pos+7]))
398 DarwinVers = atoi(&TT[Pos+7]);
400 DarwinVers = 8; // Minimum supported darwin is Tiger.
401 } else if (TT.find("linux") != std::string::npos) {
402 // Linux doesn't imply ELF, but we don't currently support anything else.
405 } else if (TT.find("cygwin") != std::string::npos) {
406 TargetType = isCygwin;
407 } else if (TT.find("mingw") != std::string::npos) {
408 TargetType = isMingw;
409 } else if (TT.find("win32") != std::string::npos) {
410 TargetType = isWindows;
411 } else if (TT.find("windows") != std::string::npos) {
412 TargetType = isWindows;
414 else if (TT.find("-cl") != std::string::npos) {
415 TargetType = isDarwin;
418 } else if (TT.empty()) {
419 #if defined(__CYGWIN__)
420 TargetType = isCygwin;
421 #elif defined(__MINGW32__) || defined(__MINGW64__)
422 TargetType = isMingw;
423 #elif defined(__APPLE__)
424 TargetType = isDarwin;
425 #if __APPLE_CC__ > 5400
426 DarwinVers = 9; // GCC 5400+ is Leopard.
428 DarwinVers = 8; // Minimum supported darwin is Tiger.
431 #elif defined(_WIN32) || defined(_WIN64)
432 TargetType = isWindows;
433 #elif defined(__linux__)
434 // Linux doesn't imply ELF, but we don't currently support anything else.
440 // If the asm syntax hasn't been overridden on the command line, use whatever
442 if (AsmFlavor == X86Subtarget::Unset) {
443 AsmFlavor = (TargetType == isWindows)
444 ? X86Subtarget::Intel : X86Subtarget::ATT;
447 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
449 if (TargetType == isDarwin || Is64Bit)
453 stackAlignment = StackAlignment;