1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86GenSubtarget.inc"
17 #include "llvm/Module.h"
18 #include "llvm/Support/CommandLine.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
28 static cl::opt<X86Subtarget::AsmWriterFlavorTy>
29 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
30 cl::desc("Choose style of code to emit from X86 backend:"),
32 clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
33 clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
37 /// True if accessing the GV requires an extra load. For Windows, dllimported
38 /// symbols are indirect, loading the value at address GV rather then the
39 /// value of GV itself. This means that the GlobalAddress must be in the base
40 /// or index register of the address, not the GV offset field.
41 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue *GV,
42 const TargetMachine &TM,
43 bool isDirectCall) const {
44 // Windows targets only require an extra load for DLLImport linkage values,
45 // and they need these regardless of whether we're in PIC mode or not.
46 if (isTargetCygMing() || isTargetWindows())
47 return GV->hasDLLImportLinkage();
49 if (TM.getRelocationModel() == Reloc::Static ||
50 TM.getCodeModel() == CodeModel::Large)
53 if (isTargetDarwin()) {
56 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
57 if (GV->hasHiddenVisibility() &&
58 (Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
59 // If symbol visibility is hidden, the extra load is not needed if
60 // target is x86-64 or the symbol is definitely defined in the current
63 return !isDirectCall && (isDecl || GV->isWeakForLinker());
64 } else if (isTargetELF()) {
65 // Extra load is needed for all externally visible.
68 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
75 /// PCRelGVRequiresExtraLoad - True if accessing the GV from a PC-relative
76 /// operand like a call target requires an extra load.
77 bool X86Subtarget::PCRelGVRequiresExtraLoad(const GlobalValue *GV,
78 const TargetMachine &TM) const {
79 // Windows targets only require an extra load for DLLImport linkage values,
80 // and they need these regardless of whether we're in PIC mode or not.
81 if (isTargetCygMing() || isTargetWindows())
82 return GV->hasDLLImportLinkage();
88 /// True if accessing the GV requires a register. This is a superset of the
89 /// cases where GVRequiresExtraLoad is true. Some variations of PIC require
90 /// a register, but not an extra load.
91 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
92 const TargetMachine &TM) const {
93 if (GVRequiresExtraLoad(GV, TM, false))
96 // Code below here need only consider cases where GVRequiresExtraLoad
98 if (TM.getRelocationModel() == Reloc::PIC_)
99 return GV->hasLocalLinkage() || GV->hasExternalLinkage();
103 /// getBZeroEntry - This function returns the name of a function which has an
104 /// interface like the non-standard bzero function, if such a function exists on
105 /// the current subtarget and it is considered prefereable over memset with zero
106 /// passed as the second argument. Otherwise it returns null.
107 const char *X86Subtarget::getBZeroEntry() const {
108 // Darwin 10 has a __bzero entry point for this purpose.
109 if (getDarwinVers() >= 10)
115 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
116 /// to immediate address.
117 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
120 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
123 /// getSpecialAddressLatency - For targets where it is beneficial to
124 /// backschedule instructions that compute addresses, return a value
125 /// indicating the number of scheduling cycles of backscheduling that
126 /// should be attempted.
127 unsigned X86Subtarget::getSpecialAddressLatency() const {
128 // For x86 out-of-order targets, back-schedule address computations so
129 // that loads and stores aren't blocked.
130 // This value was chosen arbitrarily.
134 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
135 /// specified arguments. If we can't run cpuid on the host, return true.
136 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
137 unsigned *rECX, unsigned *rEDX) {
138 #if defined(__x86_64__) || defined(_M_AMD64)
139 #if defined(__GNUC__)
140 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
141 asm ("movq\t%%rbx, %%rsi\n\t"
143 "xchgq\t%%rbx, %%rsi\n\t"
150 #elif defined(_MSC_VER)
152 __cpuid(registers, value);
153 *rEAX = registers[0];
154 *rEBX = registers[1];
155 *rECX = registers[2];
156 *rEDX = registers[3];
159 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
160 #if defined(__GNUC__)
161 asm ("movl\t%%ebx, %%esi\n\t"
163 "xchgl\t%%ebx, %%esi\n\t"
170 #elif defined(_MSC_VER)
175 mov dword ptr [esi],eax
177 mov dword ptr [esi],ebx
179 mov dword ptr [esi],ecx
181 mov dword ptr [esi],edx
189 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
190 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
191 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
192 if (Family == 6 || Family == 0xf) {
194 // Examine extended family ID if family ID is F.
195 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
196 // Examine extended model ID if family ID is 6 or F.
197 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
201 void X86Subtarget::AutoDetectSubtargetFeatures() {
202 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
208 if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
211 X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
213 if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
214 if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
215 if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
216 if (ECX & 0x1) X86SSELevel = SSE3;
217 if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
218 if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
219 if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
221 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
222 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
224 HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
225 HasAVX = ((ECX >> 28) & 0x1);
227 if (IsIntel || IsAMD) {
228 // Determine if bit test memory instructions are slow.
231 DetectFamilyModel(EAX, Family, Model);
232 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
234 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
235 HasX86_64 = (EDX >> 29) & 0x1;
236 HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
237 HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
241 static const char *GetCurrentX86CPU() {
242 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
243 if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
247 DetectFamilyModel(EAX, Family, Model);
249 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
250 bool Em64T = (EDX >> 29) & 0x1;
251 bool HasSSE3 = (ECX & 0x1);
258 X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
259 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
267 case 4: return "pentium-mmx";
268 default: return "pentium";
272 case 1: return "pentiumpro";
275 case 6: return "pentium2";
279 case 11: return "pentium3";
281 case 13: return "pentium-m";
282 case 14: return "yonah";
284 case 22: // Celeron M 540
286 case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
288 default: return "i686";
294 case 6: // same as 4, but 65nm
295 return (Em64T) ? "nocona" : "prescott";
301 return (Em64T) ? "x86-64" : "pentium4";
308 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
309 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
310 // appears to be no way to generate the wide variety of AMD-specific targets
311 // from the information returned from CPUID.
319 case 8: return "k6-2";
321 case 13: return "k6-3";
322 default: return "pentium";
326 case 4: return "athlon-tbird";
329 case 8: return "athlon-mp";
330 case 10: return "athlon-xp";
331 default: return "athlon";
336 default: return "k8-sse3";
340 case 1: return "opteron";
341 case 5: return "athlon-fx"; // also opteron
342 default: return "athlon64";
347 default: return "amdfam10";
357 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
358 : AsmFlavor(AsmWriterFlavor)
359 , PICStyle(PICStyles::None)
360 , X86SSELevel(NoMMXSSE)
361 , X863DNowLevel(NoThreeDNow)
371 // FIXME: this is a known good value for Yonah. How about others?
372 , MaxInlineSizeThreshold(128)
374 , TargetType(isELF) { // Default to ELF unless otherwise specified.
376 // default to hard float ABI
377 if (FloatABIType == FloatABI::Default)
378 FloatABIType = FloatABI::Hard;
380 // Determine default and user specified characteristics
382 // If feature string is not empty, parse features string.
383 std::string CPU = GetCurrentX86CPU();
384 ParseSubtargetFeatures(FS, CPU);
385 // All X86-64 CPUs also have SSE2, however user might request no SSE via
386 // -mattr, so don't force SSELevel here.
388 // Otherwise, use CPUID to auto-detect feature set.
389 AutoDetectSubtargetFeatures();
390 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
391 if (Is64Bit && X86SSELevel < SSE2)
395 // If requesting codegen for X86-64, make sure that 64-bit features
400 DOUT << "Subtarget features: SSELevel " << X86SSELevel
401 << ", 3DNowLevel " << X863DNowLevel
402 << ", 64bit " << HasX86_64 << "\n";
403 assert((!Is64Bit || HasX86_64) &&
404 "64-bit code requested on a subtarget that doesn't support it!");
406 // Set the boolean corresponding to the current target triple, or the default
407 // if one cannot be determined, to true.
408 const std::string& TT = M.getTargetTriple();
409 if (TT.length() > 5) {
411 if ((Pos = TT.find("-darwin")) != std::string::npos) {
412 TargetType = isDarwin;
414 // Compute the darwin version number.
415 if (isdigit(TT[Pos+7]))
416 DarwinVers = atoi(&TT[Pos+7]);
418 DarwinVers = 8; // Minimum supported darwin is Tiger.
419 } else if (TT.find("linux") != std::string::npos) {
420 // Linux doesn't imply ELF, but we don't currently support anything else.
423 } else if (TT.find("cygwin") != std::string::npos) {
424 TargetType = isCygwin;
425 } else if (TT.find("mingw") != std::string::npos) {
426 TargetType = isMingw;
427 } else if (TT.find("win32") != std::string::npos) {
428 TargetType = isWindows;
429 } else if (TT.find("windows") != std::string::npos) {
430 TargetType = isWindows;
432 else if (TT.find("-cl") != std::string::npos) {
433 TargetType = isDarwin;
436 } else if (TT.empty()) {
437 #if defined(__CYGWIN__)
438 TargetType = isCygwin;
439 #elif defined(__MINGW32__) || defined(__MINGW64__)
440 TargetType = isMingw;
441 #elif defined(__APPLE__)
442 TargetType = isDarwin;
443 #if __APPLE_CC__ > 5400
444 DarwinVers = 9; // GCC 5400+ is Leopard.
446 DarwinVers = 8; // Minimum supported darwin is Tiger.
449 #elif defined(_WIN32) || defined(_WIN64)
450 TargetType = isWindows;
451 #elif defined(__linux__)
452 // Linux doesn't imply ELF, but we don't currently support anything else.
458 // If the asm syntax hasn't been overridden on the command line, use whatever
460 if (AsmFlavor == X86Subtarget::Unset) {
461 AsmFlavor = (TargetType == isWindows)
462 ? X86Subtarget::Intel : X86Subtarget::ATT;
465 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
467 if (TargetType == isDarwin || Is64Bit)
471 stackAlignment = StackAlignment;