1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "X86Subtarget.h"
15 #include "X86GenSubtarget.inc"
16 #include "llvm/Module.h"
17 #include "llvm/Support/CommandLine.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetOptions.h"
22 static cl::opt<X86Subtarget::AsmWriterFlavorTy>
23 AsmWriterFlavor("x86-asm-syntax", cl::init(X86Subtarget::Unset),
24 cl::desc("Choose style of code to emit from X86 backend:"),
26 clEnumValN(X86Subtarget::ATT, "att", "Emit AT&T-style assembly"),
27 clEnumValN(X86Subtarget::Intel, "intel", "Emit Intel-style assembly"),
31 /// True if accessing the GV requires an extra load. For Windows, dllimported
32 /// symbols are indirect, loading the value at address GV rather then the
33 /// value of GV itself. This means that the GlobalAddress must be in the base
34 /// or index register of the address, not the GV offset field.
35 bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
36 const TargetMachine& TM,
37 bool isDirectCall) const
40 if (TM.getRelocationModel() != Reloc::Static &&
41 TM.getCodeModel() != CodeModel::Large) {
42 if (isTargetDarwin()) {
45 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
46 if (GV->hasHiddenVisibility() &&
47 (Is64Bit || (!isDecl && !GV->hasCommonLinkage())))
48 // If symbol visibility is hidden, the extra load is not needed if
49 // target is x86-64 or the symbol is definitely defined in the current
52 return !isDirectCall && (isDecl || GV->mayBeOverridden());
53 } else if (isTargetELF()) {
54 // Extra load is needed for all externally visible.
57 if (GV->hasInternalLinkage() || GV->hasHiddenVisibility())
60 } else if (isTargetCygMing() || isTargetWindows()) {
61 return (GV->hasDLLImportLinkage());
67 /// True if accessing the GV requires a register. This is a superset of the
68 /// cases where GVRequiresExtraLoad is true. Some variations of PIC require
69 /// a register, but not an extra load.
70 bool X86Subtarget::GVRequiresRegister(const GlobalValue *GV,
71 const TargetMachine& TM,
72 bool isDirectCall) const
74 if (GVRequiresExtraLoad(GV, TM, isDirectCall))
76 // Code below here need only consider cases where GVRequiresExtraLoad
78 if (TM.getRelocationModel() == Reloc::PIC_)
79 return !isDirectCall &&
80 (GV->hasInternalLinkage() || GV->hasExternalLinkage());
84 /// getBZeroEntry - This function returns the name of a function which has an
85 /// interface like the non-standard bzero function, if such a function exists on
86 /// the current subtarget and it is considered prefereable over memset with zero
87 /// passed as the second argument. Otherwise it returns null.
88 const char *X86Subtarget::getBZeroEntry() const {
89 // Darwin 10 has a __bzero entry point for this purpose.
90 if (getDarwinVers() >= 10)
96 /// getSpecialAddressLatency - For targets where it is beneficial to
97 /// backschedule instructions that compute addresses, return a value
98 /// indicating the number of scheduling cycles of backscheduling that
99 /// should be attempted.
100 unsigned X86Subtarget::getSpecialAddressLatency() const {
101 // For x86 out-of-order targets, back-schedule address computations so
102 // that loads and stores aren't blocked.
103 // This value was chosen arbitrarily.
107 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
108 /// specified arguments. If we can't run cpuid on the host, return true.
109 bool X86::GetCpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
110 unsigned *rECX, unsigned *rEDX) {
111 #if defined(__x86_64__)
112 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
113 asm ("movq\t%%rbx, %%rsi\n\t"
115 "xchgq\t%%rbx, %%rsi\n\t"
122 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
123 #if defined(__GNUC__)
124 asm ("movl\t%%ebx, %%esi\n\t"
126 "xchgl\t%%ebx, %%esi\n\t"
133 #elif defined(_MSC_VER)
138 mov dword ptr [esi],eax
140 mov dword ptr [esi],ebx
142 mov dword ptr [esi],ecx
144 mov dword ptr [esi],edx
152 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
153 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
154 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
155 if (Family == 6 || Family == 0xf) {
157 // Examine extended family ID if family ID is F.
158 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
159 // Examine extended model ID if family ID is 6 or F.
160 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
164 void X86Subtarget::AutoDetectSubtargetFeatures() {
165 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
171 if (X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
174 X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
176 if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
177 if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
178 if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
179 if (ECX & 0x1) X86SSELevel = SSE3;
180 if ((ECX >> 9) & 0x1) X86SSELevel = SSSE3;
181 if ((ECX >> 19) & 0x1) X86SSELevel = SSE41;
182 if ((ECX >> 20) & 0x1) X86SSELevel = SSE42;
184 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
185 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
186 if (IsIntel || IsAMD) {
187 // Determine if bit test memory instructions are slow.
190 DetectFamilyModel(EAX, Family, Model);
191 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
193 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
194 HasX86_64 = (EDX >> 29) & 0x1;
198 static const char *GetCurrentX86CPU() {
199 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
200 if (X86::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
204 DetectFamilyModel(EAX, Family, Model);
206 X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
207 bool Em64T = (EDX >> 29) & 0x1;
214 X86::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
215 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
223 case 4: return "pentium-mmx";
224 default: return "pentium";
228 case 1: return "pentiumpro";
231 case 6: return "pentium2";
235 case 11: return "pentium3";
237 case 13: return "pentium-m";
238 case 14: return "yonah";
239 case 15: return "core2";
240 case 23: return "penryn";
241 default: return "i686";
247 return (Em64T) ? "nocona" : "prescott";
249 return (Em64T) ? "x86-64" : "pentium4";
256 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
257 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
258 // appears to be no way to generate the wide variety of AMD-specific targets
259 // from the information returned from CPUID.
267 case 8: return "k6-2";
269 case 13: return "k6-3";
270 default: return "pentium";
274 case 4: return "athlon-tbird";
277 case 8: return "athlon-mp";
278 case 10: return "athlon-xp";
279 default: return "athlon";
283 case 1: return "opteron";
284 case 5: return "athlon-fx"; // also opteron
285 default: return "athlon64";
295 X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
296 : AsmFlavor(AsmWriterFlavor)
297 , PICStyle(PICStyles::None)
298 , X86SSELevel(NoMMXSSE)
299 , X863DNowLevel(NoThreeDNow)
305 // FIXME: this is a known good value for Yonah. How about others?
306 , MaxInlineSizeThreshold(128)
308 , TargetType(isELF) { // Default to ELF unless otherwise specified.
310 // Determine default and user specified characteristics
312 // If feature string is not empty, parse features string.
313 std::string CPU = GetCurrentX86CPU();
314 ParseSubtargetFeatures(FS, CPU);
316 // Otherwise, use CPUID to auto-detect feature set.
317 AutoDetectSubtargetFeatures();
320 // If requesting codegen for X86-64, make sure that 64-bit and SSE2 features
321 // are enabled. These are available on all x86-64 CPUs.
324 if (X86SSELevel < SSE2)
328 // Set the boolean corresponding to the current target triple, or the default
329 // if one cannot be determined, to true.
330 const std::string& TT = M.getTargetTriple();
331 if (TT.length() > 5) {
333 if ((Pos = TT.find("-darwin")) != std::string::npos) {
334 TargetType = isDarwin;
336 // Compute the darwin version number.
337 if (isdigit(TT[Pos+7]))
338 DarwinVers = atoi(&TT[Pos+7]);
340 DarwinVers = 8; // Minimum supported darwin is Tiger.
341 } else if (TT.find("linux") != std::string::npos) {
342 // Linux doesn't imply ELF, but we don't currently support anything else.
345 } else if (TT.find("cygwin") != std::string::npos) {
346 TargetType = isCygwin;
347 } else if (TT.find("mingw") != std::string::npos) {
348 TargetType = isMingw;
349 } else if (TT.find("win32") != std::string::npos) {
350 TargetType = isWindows;
351 } else if (TT.find("windows") != std::string::npos) {
352 TargetType = isWindows;
354 } else if (TT.empty()) {
355 #if defined(__CYGWIN__)
356 TargetType = isCygwin;
357 #elif defined(__MINGW32__) || defined(__MINGW64__)
358 TargetType = isMingw;
359 #elif defined(__APPLE__)
360 TargetType = isDarwin;
361 #if __APPLE_CC__ > 5400
362 DarwinVers = 9; // GCC 5400+ is Leopard.
364 DarwinVers = 8; // Minimum supported darwin is Tiger.
367 #elif defined(_WIN32) || defined(_WIN64)
368 TargetType = isWindows;
369 #elif defined(__linux__)
370 // Linux doesn't imply ELF, but we don't currently support anything else.
376 // If the asm syntax hasn't been overridden on the command line, use whatever
378 if (AsmFlavor == X86Subtarget::Unset) {
379 AsmFlavor = (TargetType == isWindows)
380 ? X86Subtarget::Intel : X86Subtarget::ATT;
383 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
385 if (TargetType == isDarwin || Is64Bit)
389 stackAlignment = StackAlignment;