1 //===-- X86Subtarget.cpp - X86 Subtarget Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "subtarget"
15 #include "X86Subtarget.h"
16 #include "X86InstrInfo.h"
17 #include "X86GenSubtarget.inc"
18 #include "llvm/GlobalValue.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/ADT/SmallVector.h"
30 /// ClassifyGlobalReference - Classify a global variable reference for the
31 /// current subtarget according to how we should reference it in a non-pcrel
33 unsigned char X86Subtarget::
34 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
35 // DLLImport only exists on windows, it is implemented as a load from a
37 if (GV->hasDLLImportLinkage())
38 return X86II::MO_DLLIMPORT;
40 // GV with ghost linkage (in JIT lazy compilation mode) do not require an
41 // extra load from stub.
42 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode();
44 // X86-64 in PIC mode.
45 if (isPICStyleRIPRel()) {
46 // Large model never uses stubs.
47 if (TM.getCodeModel() == CodeModel::Large)
48 return X86II::MO_NO_FLAG;
50 if (isTargetDarwin()) {
51 // If symbol visibility is hidden, the extra load is not needed if
52 // target is x86-64 or the symbol is definitely defined in the current
54 if (GV->hasDefaultVisibility() &&
55 (isDecl || GV->isWeakForLinker()))
56 return X86II::MO_GOTPCREL;
58 assert(isTargetELF() && "Unknown rip-relative target");
60 // Extra load is needed for all externally visible.
61 if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
62 return X86II::MO_GOTPCREL;
65 return X86II::MO_NO_FLAG;
68 if (isPICStyleGOT()) { // 32-bit ELF targets.
69 // Extra load is needed for all externally visible.
70 if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
71 return X86II::MO_GOTOFF;
75 if (isPICStyleStubPIC()) { // Darwin/32 in PIC mode.
76 // Determine whether we have a stub reference and/or whether the reference
77 // is relative to the PIC base or not.
79 // If this is a strong reference to a definition, it is definitely not
81 if (!isDecl && !GV->isWeakForLinker())
82 return X86II::MO_PIC_BASE_OFFSET;
84 // Unless we have a symbol with hidden visibility, we have to go through a
85 // normal $non_lazy_ptr stub because this symbol might be resolved late.
86 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
87 return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
89 // If symbol visibility is hidden, we have a stub for common symbol
90 // references and external declarations.
91 if (isDecl || GV->hasCommonLinkage()) {
92 // Hidden $non_lazy_ptr reference.
93 return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
96 // Otherwise, no stub.
97 return X86II::MO_PIC_BASE_OFFSET;
100 if (isPICStyleStubNoDynamic()) { // Darwin/32 in -mdynamic-no-pic mode.
101 // Determine whether we have a stub reference.
103 // If this is a strong reference to a definition, it is definitely not
105 if (!isDecl && !GV->isWeakForLinker())
106 return X86II::MO_NO_FLAG;
108 // Unless we have a symbol with hidden visibility, we have to go through a
109 // normal $non_lazy_ptr stub because this symbol might be resolved late.
110 if (!GV->hasHiddenVisibility()) // Non-hidden $non_lazy_ptr reference.
111 return X86II::MO_DARWIN_NONLAZY;
113 // Otherwise, no stub.
114 return X86II::MO_NO_FLAG;
117 // Direct static reference to global.
118 return X86II::MO_NO_FLAG;
122 /// getBZeroEntry - This function returns the name of a function which has an
123 /// interface like the non-standard bzero function, if such a function exists on
124 /// the current subtarget and it is considered prefereable over memset with zero
125 /// passed as the second argument. Otherwise it returns null.
126 const char *X86Subtarget::getBZeroEntry() const {
127 // Darwin 10 has a __bzero entry point for this purpose.
128 if (getDarwinVers() >= 10)
134 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
135 /// to immediate address.
136 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
139 return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
142 /// getSpecialAddressLatency - For targets where it is beneficial to
143 /// backschedule instructions that compute addresses, return a value
144 /// indicating the number of scheduling cycles of backscheduling that
145 /// should be attempted.
146 unsigned X86Subtarget::getSpecialAddressLatency() const {
147 // For x86 out-of-order targets, back-schedule address computations so
148 // that loads and stores aren't blocked.
149 // This value was chosen arbitrarily.
153 /// GetCpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
154 /// specified arguments. If we can't run cpuid on the host, return true.
155 static bool GetCpuIDAndInfo(unsigned value, unsigned *rEAX,
156 unsigned *rEBX, unsigned *rECX, unsigned *rEDX) {
157 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
158 #if defined(__GNUC__)
159 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
160 asm ("movq\t%%rbx, %%rsi\n\t"
162 "xchgq\t%%rbx, %%rsi\n\t"
169 #elif defined(_MSC_VER)
171 __cpuid(registers, value);
172 *rEAX = registers[0];
173 *rEBX = registers[1];
174 *rECX = registers[2];
175 *rEDX = registers[3];
178 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
179 #if defined(__GNUC__)
180 asm ("movl\t%%ebx, %%esi\n\t"
182 "xchgl\t%%ebx, %%esi\n\t"
189 #elif defined(_MSC_VER)
194 mov dword ptr [esi],eax
196 mov dword ptr [esi],ebx
198 mov dword ptr [esi],ecx
200 mov dword ptr [esi],edx
208 static void DetectFamilyModel(unsigned EAX, unsigned &Family, unsigned &Model) {
209 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
210 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
211 if (Family == 6 || Family == 0xf) {
213 // Examine extended family ID if family ID is F.
214 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
215 // Examine extended model ID if family ID is 6 or F.
216 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
220 void X86Subtarget::AutoDetectSubtargetFeatures() {
221 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
227 if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
230 GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
232 if ((EDX >> 15) & 1) HasCMov = true;
233 if ((EDX >> 23) & 1) X86SSELevel = MMX;
234 if ((EDX >> 25) & 1) X86SSELevel = SSE1;
235 if ((EDX >> 26) & 1) X86SSELevel = SSE2;
236 if (ECX & 0x1) X86SSELevel = SSE3;
237 if ((ECX >> 9) & 1) X86SSELevel = SSSE3;
238 if ((ECX >> 19) & 1) X86SSELevel = SSE41;
239 if ((ECX >> 20) & 1) X86SSELevel = SSE42;
241 bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
242 bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
244 HasFMA3 = IsIntel && ((ECX >> 12) & 0x1);
245 HasAVX = ((ECX >> 28) & 0x1);
247 if (IsIntel || IsAMD) {
248 // Determine if bit test memory instructions are slow.
251 DetectFamilyModel(EAX, Family, Model);
252 IsBTMemSlow = IsAMD || (Family == 6 && Model >= 13);
254 GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
255 HasX86_64 = (EDX >> 29) & 0x1;
256 HasSSE4A = IsAMD && ((ECX >> 6) & 0x1);
257 HasFMA4 = IsAMD && ((ECX >> 16) & 0x1);
261 static const char *GetCurrentX86CPU() {
262 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
263 if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
267 DetectFamilyModel(EAX, Family, Model);
269 GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
270 bool Em64T = (EDX >> 29) & 0x1;
271 bool HasSSE3 = (ECX & 0x1);
278 GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
279 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
287 case 4: return "pentium-mmx";
288 default: return "pentium";
292 case 1: return "pentiumpro";
295 case 6: return "pentium2";
299 case 11: return "pentium3";
301 case 13: return "pentium-m";
302 case 14: return "yonah";
304 case 22: // Celeron M 540
306 case 23: // 45nm: Penryn , Wolfdale, Yorkfield (XE)
308 default: return "i686";
314 case 6: // same as 4, but 65nm
315 return (Em64T) ? "nocona" : "prescott";
321 return (Em64T) ? "x86-64" : "pentium4";
328 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
329 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
330 // appears to be no way to generate the wide variety of AMD-specific targets
331 // from the information returned from CPUID.
339 case 8: return "k6-2";
341 case 13: return "k6-3";
342 default: return "pentium";
346 case 4: return "athlon-tbird";
349 case 8: return "athlon-mp";
350 case 10: return "athlon-xp";
351 default: return "athlon";
358 case 1: return "opteron";
359 case 5: return "athlon-fx"; // also opteron
360 default: return "athlon64";
373 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS,
375 : PICStyle(PICStyles::None)
376 , X86SSELevel(NoMMXSSE)
377 , X863DNowLevel(NoThreeDNow)
387 // FIXME: this is a known good value for Yonah. How about others?
388 , MaxInlineSizeThreshold(128)
390 , TargetType(isELF) { // Default to ELF unless otherwise specified.
392 // default to hard float ABI
393 if (FloatABIType == FloatABI::Default)
394 FloatABIType = FloatABI::Hard;
396 // Determine default and user specified characteristics
398 // If feature string is not empty, parse features string.
399 std::string CPU = GetCurrentX86CPU();
400 ParseSubtargetFeatures(FS, CPU);
401 // All X86-64 CPUs also have SSE2, however user might request no SSE via
402 // -mattr, so don't force SSELevel here.
404 // Otherwise, use CPUID to auto-detect feature set.
405 AutoDetectSubtargetFeatures();
406 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
407 if (Is64Bit && X86SSELevel < SSE2)
411 // If requesting codegen for X86-64, make sure that 64-bit features
416 DEBUG(errs() << "Subtarget features: SSELevel " << X86SSELevel
417 << ", 3DNowLevel " << X863DNowLevel
418 << ", 64bit " << HasX86_64 << "\n");
419 assert((!Is64Bit || HasX86_64) &&
420 "64-bit code requested on a subtarget that doesn't support it!");
422 // Set the boolean corresponding to the current target triple, or the default
423 // if one cannot be determined, to true.
424 if (TT.length() > 5) {
426 if ((Pos = TT.find("-darwin")) != std::string::npos) {
427 TargetType = isDarwin;
429 // Compute the darwin version number.
430 if (isdigit(TT[Pos+7]))
431 DarwinVers = atoi(&TT[Pos+7]);
433 DarwinVers = 8; // Minimum supported darwin is Tiger.
434 } else if (TT.find("linux") != std::string::npos) {
435 // Linux doesn't imply ELF, but we don't currently support anything else.
437 } else if (TT.find("cygwin") != std::string::npos) {
438 TargetType = isCygwin;
439 } else if (TT.find("mingw") != std::string::npos) {
440 TargetType = isMingw;
441 } else if (TT.find("win32") != std::string::npos) {
442 TargetType = isWindows;
443 } else if (TT.find("windows") != std::string::npos) {
444 TargetType = isWindows;
445 } else if (TT.find("-cl") != std::string::npos) {
446 TargetType = isDarwin;
451 // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64
453 if (TargetType == isDarwin || Is64Bit)
457 stackAlignment = StackAlignment;
460 bool X86Subtarget::enablePostRAScheduler(
461 CodeGenOpt::Level OptLevel,
462 TargetSubtarget::AntiDepBreakMode& Mode,
463 RegClassVector& CriticalPathRCs) const {
464 Mode = TargetSubtarget::ANTIDEP_CRITICAL;
465 CriticalPathRCs.clear();
466 return OptLevel >= CodeGenOpt::Default;