1 //=- X86SchedHaswell.td - X86 Haswell Scheduling -------------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the machine model for Haswell to support instruction
11 // scheduling and other instruction cost heuristics.
13 //===----------------------------------------------------------------------===//
15 def HaswellModel : SchedMachineModel {
16 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
17 // instructions per cycle.
19 let MicroOpBufferSize = 192; // Based on the reorder buffer.
21 let MispredictPenalty = 16;
23 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
24 let LoopMicroOpBufferSize = 50;
26 // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow
27 // the scheduler to assign a default model to unrecognized opcodes.
28 let CompleteModel = 0;
31 let SchedModel = HaswellModel in {
33 // Haswell can issue micro-ops to 8 different ports in one cycle.
35 // Ports 0, 1, 5, and 6 handle all computation.
36 // Port 4 gets the data half of stores. Store data can be available later than
37 // the store address, but since we don't model the latency of stores, we can
39 // Ports 2 and 3 are identical. They handle loads and the address half of
40 // stores. Port 7 can handle address calculations.
41 def HWPort0 : ProcResource<1>;
42 def HWPort1 : ProcResource<1>;
43 def HWPort2 : ProcResource<1>;
44 def HWPort3 : ProcResource<1>;
45 def HWPort4 : ProcResource<1>;
46 def HWPort5 : ProcResource<1>;
47 def HWPort6 : ProcResource<1>;
48 def HWPort7 : ProcResource<1>;
50 // Many micro-ops are capable of issuing on multiple ports.
51 def HWPort01 : ProcResGroup<[HWPort0, HWPort1]>;
52 def HWPort23 : ProcResGroup<[HWPort2, HWPort3]>;
53 def HWPort237 : ProcResGroup<[HWPort2, HWPort3, HWPort7]>;
54 def HWPort04 : ProcResGroup<[HWPort0, HWPort4]>;
55 def HWPort05 : ProcResGroup<[HWPort0, HWPort5]>;
56 def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
57 def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
58 def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
59 def HWPort56: ProcResGroup<[HWPort5, HWPort6]>;
60 def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
61 def HWPort056: ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
62 def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
64 // 60 Entry Unified Scheduler
65 def HWPortAny : ProcResGroup<[HWPort0, HWPort1, HWPort2, HWPort3, HWPort4,
66 HWPort5, HWPort6, HWPort7]> {
70 // Integer division issued on port 0.
71 def HWDivider : ProcResource<1>;
73 // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4
74 // cycles after the memory operand.
75 def : ReadAdvance<ReadAfterLd, 4>;
77 // Many SchedWrites are defined in pairs with and without a folded load.
78 // Instructions with folded loads are usually micro-fused, so they only appear
79 // as two micro-ops when queued in the reservation station.
80 // This multiclass defines the resource usage for variants with and without
82 multiclass HWWriteResPair<X86FoldableSchedWrite SchedRW,
83 ProcResourceKind ExePort,
85 // Register variant is using a single cycle on ExePort.
86 def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
88 // Memory variant also uses a cycle on port 2/3 and adds 4 cycles to the
90 def : WriteRes<SchedRW.Folded, [HWPort23, ExePort]> {
91 let Latency = !add(Lat, 4);
95 // A folded store needs a cycle on port 4 for the store data, but it does not
96 // need an extra port 2/3 cycle to recompute the address.
97 def : WriteRes<WriteRMW, [HWPort4]>;
101 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
102 def : WriteRes<WriteLoad, [HWPort23]> { let Latency = 4; }
103 def : WriteRes<WriteMove, [HWPort0156]>;
104 def : WriteRes<WriteZero, []>;
106 defm : HWWriteResPair<WriteALU, HWPort0156, 1>;
107 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
108 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
109 defm : HWWriteResPair<WriteShift, HWPort06, 1>;
110 defm : HWWriteResPair<WriteJump, HWPort06, 1>;
112 // This is for simple LEAs with one or two input operands.
113 // The complex ones can only execute on port 1, and they require two cycles on
114 // the port to read all inputs. We don't model that.
115 def : WriteRes<WriteLEA, [HWPort15]>;
117 // This is quite rough, latency depends on the dividend.
118 def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
120 let ResourceCycles = [1, 10];
122 def : WriteRes<WriteIDivLd, [HWPort23, HWPort0, HWDivider]> {
124 let ResourceCycles = [1, 1, 10];
127 // Scalar and vector floating point.
128 defm : HWWriteResPair<WriteFAdd, HWPort1, 3>;
129 defm : HWWriteResPair<WriteFMul, HWPort0, 5>;
130 defm : HWWriteResPair<WriteFDiv, HWPort0, 12>; // 10-14 cycles.
131 defm : HWWriteResPair<WriteFRcp, HWPort0, 5>;
132 defm : HWWriteResPair<WriteFSqrt, HWPort0, 15>;
133 defm : HWWriteResPair<WriteCvtF2I, HWPort1, 3>;
134 defm : HWWriteResPair<WriteCvtI2F, HWPort1, 4>;
135 defm : HWWriteResPair<WriteCvtF2F, HWPort1, 3>;
136 defm : HWWriteResPair<WriteFShuffle, HWPort5, 1>;
137 defm : HWWriteResPair<WriteFBlend, HWPort015, 1>;
138 defm : HWWriteResPair<WriteFShuffle256, HWPort5, 3>;
140 def : WriteRes<WriteFVarBlend, [HWPort5]> {
142 let ResourceCycles = [2];
144 def : WriteRes<WriteFVarBlendLd, [HWPort5, HWPort23]> {
146 let ResourceCycles = [2, 1];
149 // Vector integer operations.
150 defm : HWWriteResPair<WriteVecShift, HWPort0, 1>;
151 defm : HWWriteResPair<WriteVecLogic, HWPort015, 1>;
152 defm : HWWriteResPair<WriteVecALU, HWPort15, 1>;
153 defm : HWWriteResPair<WriteVecIMul, HWPort0, 5>;
154 defm : HWWriteResPair<WriteShuffle, HWPort5, 1>;
155 defm : HWWriteResPair<WriteBlend, HWPort15, 1>;
156 defm : HWWriteResPair<WriteShuffle256, HWPort5, 3>;
158 def : WriteRes<WriteVarBlend, [HWPort5]> {
160 let ResourceCycles = [2];
162 def : WriteRes<WriteVarBlendLd, [HWPort5, HWPort23]> {
164 let ResourceCycles = [2, 1];
167 def : WriteRes<WriteVarVecShift, [HWPort0, HWPort5]> {
169 let ResourceCycles = [2, 1];
171 def : WriteRes<WriteVarVecShiftLd, [HWPort0, HWPort5, HWPort23]> {
173 let ResourceCycles = [2, 1, 1];
176 def : WriteRes<WriteMPSAD, [HWPort0, HWPort5]> {
178 let ResourceCycles = [1, 2];
180 def : WriteRes<WriteMPSADLd, [HWPort23, HWPort0, HWPort5]> {
182 let ResourceCycles = [1, 1, 2];
185 // String instructions.
186 // Packed Compare Implicit Length Strings, Return Mask
187 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
189 let ResourceCycles = [3];
191 def : WriteRes<WritePCmpIStrMLd, [HWPort0, HWPort23]> {
193 let ResourceCycles = [3, 1];
196 // Packed Compare Explicit Length Strings, Return Mask
197 def : WriteRes<WritePCmpEStrM, [HWPort0, HWPort16, HWPort5]> {
199 let ResourceCycles = [3, 2, 4];
201 def : WriteRes<WritePCmpEStrMLd, [HWPort05, HWPort16, HWPort23]> {
203 let ResourceCycles = [6, 2, 1];
206 // Packed Compare Implicit Length Strings, Return Index
207 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
209 let ResourceCycles = [3];
211 def : WriteRes<WritePCmpIStrILd, [HWPort0, HWPort23]> {
213 let ResourceCycles = [3, 1];
216 // Packed Compare Explicit Length Strings, Return Index
217 def : WriteRes<WritePCmpEStrI, [HWPort05, HWPort16]> {
219 let ResourceCycles = [6, 2];
221 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort16, HWPort5, HWPort23]> {
223 let ResourceCycles = [3, 2, 2, 1];
227 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
229 let ResourceCycles = [1];
231 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
233 let ResourceCycles = [1, 1];
236 def : WriteRes<WriteAESIMC, [HWPort5]> {
238 let ResourceCycles = [2];
240 def : WriteRes<WriteAESIMCLd, [HWPort5, HWPort23]> {
242 let ResourceCycles = [2, 1];
245 def : WriteRes<WriteAESKeyGen, [HWPort0, HWPort5]> {
247 let ResourceCycles = [2, 8];
249 def : WriteRes<WriteAESKeyGenLd, [HWPort0, HWPort5, HWPort23]> {
251 let ResourceCycles = [2, 7, 1];
254 // Carry-less multiplication instructions.
255 def : WriteRes<WriteCLMul, [HWPort0, HWPort5]> {
257 let ResourceCycles = [2, 1];
259 def : WriteRes<WriteCLMulLd, [HWPort0, HWPort5, HWPort23]> {
261 let ResourceCycles = [2, 1, 1];
264 def : WriteRes<WriteSystem, [HWPort0156]> { let Latency = 100; }
265 def : WriteRes<WriteMicrocoded, [HWPort0156]> { let Latency = 100; }
266 def : WriteRes<WriteFence, [HWPort23, HWPort4]>;
267 def : WriteRes<WriteNop, []>;
269 //================ Exceptions ================//
271 //-- Specific Scheduling Models --//
272 def WriteP0 : SchedWriteRes<[HWPort0]>;
273 def WriteP1 : SchedWriteRes<[HWPort1]>;
274 def WriteP1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
277 def WriteP1_Lat3 : SchedWriteRes<[HWPort1]> {
280 def WriteP1_Lat3Ld : SchedWriteRes<[HWPort1, HWPort23]> {
284 def Write2P0156_Lat2 : SchedWriteRes<[HWPort0156]> {
286 let ResourceCycles = [2];
288 def Write2P0156_Lat2Ld : SchedWriteRes<[HWPort0156, HWPort23]> {
290 let ResourceCycles = [2, 1];
293 def Write5P0156 : SchedWriteRes<[HWPort0156]> {
295 let ResourceCycles = [5];
298 def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
300 let ResourceCycles = [2, 1];
303 def WriteP01 : SchedWriteRes<[HWPort01]>;
305 def Write2P01 : SchedWriteRes<[HWPort01]> {
308 def Write3P01 : SchedWriteRes<[HWPort01]> {
312 def WriteP015 : SchedWriteRes<[HWPort015]>;
314 def WriteP01_P5 : SchedWriteRes<[HWPort01, HWPort5]> {
317 def WriteP06 : SchedWriteRes<[HWPort06]>;
319 def Write2P06 : SchedWriteRes<[HWPort06]> {
322 let ResourceCycles = [2];
325 def Write2P1 : SchedWriteRes<[HWPort1]> {
327 let ResourceCycles = [2];
329 def Write2P1_P23 : SchedWriteRes<[HWPort1, HWPort23]> {
331 let ResourceCycles = [2, 1];
333 def WriteP15 : SchedWriteRes<[HWPort15]>;
334 def WriteP15Ld : SchedWriteRes<[HWPort15, HWPort23]> {
338 def Write3P06_Lat2 : SchedWriteRes<[HWPort06]> {
341 let ResourceCycles = [3];
344 def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
348 def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
350 let ResourceCycles = [1, 2, 1];
353 def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
355 let ResourceCycles = [2, 2, 1];
358 def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
360 let ResourceCycles = [2, 1];
363 def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
365 let ResourceCycles = [3, 2, 1];
368 def WriteP5 : SchedWriteRes<[HWPort5]>;
369 def WriteP5Ld : SchedWriteRes<[HWPort5, HWPort23]> {
372 let ResourceCycles = [1, 1];
375 def WriteP0_P1_Lat4 : SchedWriteRes<[HWPort0, HWPort1]> {
378 let ResourceCycles = [1, 1];
381 def WriteP0_P1_Lat4Ld : SchedWriteRes<[HWPort0, HWPort1, HWPort23]> {
384 let ResourceCycles = [1, 1, 1];
387 def WriteP1_P5_Lat4 : SchedWriteRes<[HWPort1, HWPort5]> {
390 let ResourceCycles = [1, 1];
393 def WriteP1_P5_Lat4Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
396 let ResourceCycles = [1, 1, 1];
399 def WriteP1_P5_Lat6 : SchedWriteRes<[HWPort1, HWPort5]> {
402 let ResourceCycles = [1, 1];
405 def WriteP1_P5_Lat6Ld : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
408 let ResourceCycles = [1, 1, 1];
413 // - mm: 64 bit mmx register.
414 // - x = 128 bit xmm register.
415 // - (x)mm = mmx or xmm register.
416 // - y = 256 bit ymm register.
417 // - v = any vector register.
420 //=== Integer Instructions ===//
421 //-- Move instructions --//
425 def : InstRW<[WriteALULd], (instregex "MOV16rm")>;
429 def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>;
433 def : InstRW<[Write2P0156_Lat2],
434 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rr")>;
436 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd],
437 (instregex "CMOV(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)(16|32|64)rm")>;
441 def WriteXCHG : SchedWriteRes<[HWPort0156]> {
443 let ResourceCycles = [3];
446 def : InstRW<[WriteXCHG], (instregex "XCHG(8|16|32|64)rr", "XCHG(16|32|64)ar")>;
449 def WriteXCHGrm : SchedWriteRes<[]> {
453 def : InstRW<[WriteXCHGrm], (instregex "XCHG(8|16|32|64)rm")>;
456 def WriteXLAT : SchedWriteRes<[]> {
460 def : InstRW<[WriteXLAT], (instregex "XLAT")>;
464 def : InstRW<[Write2P237_P4], (instregex "PUSH(16|32)rmm")>;
467 def WritePushF : SchedWriteRes<[HWPort1, HWPort4, HWPort237, HWPort06]> {
470 def : InstRW<[WritePushF], (instregex "PUSHF(16|32)")>;
473 def WritePushA : SchedWriteRes<[]> {
474 let NumMicroOps = 19;
476 def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
480 def : InstRW<[Write2P237_P4], (instregex "POP(16|32)rmm")>;
483 def WritePopF : SchedWriteRes<[]> {
486 def : InstRW<[WritePopF], (instregex "POPF(16|32)")>;
489 def WritePopA : SchedWriteRes<[]> {
490 let NumMicroOps = 18;
492 def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
495 def : InstRW<[WriteP06], (instregex "(S|L)AHF")>;
499 def WriteBSwap32 : SchedWriteRes<[HWPort15]>;
500 def : InstRW<[WriteBSwap32], (instregex "BSWAP32r")>;
503 def WriteBSwap64 : SchedWriteRes<[HWPort06, HWPort15]> {
506 def : InstRW<[WriteBSwap64], (instregex "BSWAP64r")>;
509 // r16,m16 / r64,m64.
510 def : InstRW<[Write2P0156_Lat2Ld], (instregex "MOVBE(16|64)rm")>;
513 def WriteMoveBE32rm : SchedWriteRes<[HWPort15, HWPort23]> {
516 def : InstRW<[WriteMoveBE32rm], (instregex "MOVBE32rm")>;
519 def WriteMoveBE16mr : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
522 def : InstRW<[WriteMoveBE16mr], (instregex "MOVBE16mr")>;
525 def WriteMoveBE32mr : SchedWriteRes<[HWPort15, HWPort237, HWPort4]> {
528 def : InstRW<[WriteMoveBE32mr], (instregex "MOVBE32mr")>;
531 def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
534 def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
536 //-- Arithmetic instructions --//
540 def : InstRW<[Write2P0156_2P237_P4],
541 (instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
542 "(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
546 def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
547 "(ADC|SBB)(16|32|64)ri8",
549 "(ADC|SBB)(8|16|32|64)rr_REV")>;
552 def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
555 def : InstRW<[Write3P0156_2P237_P4],
556 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
557 "(ADC|SBB)(16|32|64)mi8",
562 def : InstRW<[WriteP0156_2P237_P4],
563 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
564 "(INC|DEC)64(16|32)m")>;
568 def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
572 def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
575 def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
579 def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
582 def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
586 def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
589 def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
593 def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
596 def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
600 def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
603 def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
607 def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
610 def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
614 def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
617 def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
621 def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
625 def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
628 let ResourceCycles = [1, 2];
630 def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
633 def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
636 let ResourceCycles = [1, 2, 1];
638 def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
641 def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
645 def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
648 def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
652 def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
656 def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
660 def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
663 def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
665 let NumMicroOps = 10;
667 def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
670 def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
672 let NumMicroOps = 10;
674 def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
677 def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
679 let NumMicroOps = 36;
681 def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
685 def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
689 def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
692 def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
694 let NumMicroOps = 10;
696 def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
699 def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
703 def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
706 def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
708 let NumMicroOps = 59;
710 def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
712 //-- Logic instructions --//
716 def : InstRW<[Write2P0156_2P237_P4],
717 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)",
718 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>;
722 def WriteShiftRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
724 let ResourceCycles = [2, 1, 1];
726 def : InstRW<[WriteShiftRMW], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>;
729 def : InstRW<[Write3P06_Lat2], (instregex "S(A|H)(R|L)(8|16|32|64)rCL")>;
732 def WriteShiftClLdRMW : SchedWriteRes<[HWPort06, HWPort23, HWPort4]> {
734 let ResourceCycles = [3, 2, 1];
736 def : InstRW<[WriteShiftClLdRMW], (instregex "S(A|H)(R|L)(8|16|32|64)mCL")>;
740 def : InstRW<[Write2P06], (instregex "RO(R|L)(8|16|32|64)r1")>;
743 def WriteRotateRMW : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
745 let ResourceCycles = [2, 2, 1];
747 def : InstRW<[WriteRotateRMW], (instregex "RO(R|L)(8|16|32|64)mi")>;
750 def : InstRW<[Write3P06_Lat2], (instregex "RO(R|L)(8|16|32|64)rCL")>;
753 def WriteRotateRMWCL : SchedWriteRes<[]> {
756 def : InstRW<[WriteRotateRMWCL], (instregex "RO(R|L)(8|16|32|64)mCL")>;
760 def WriteRCr1 : SchedWriteRes<[HWPort06, HWPort0156]> {
763 let ResourceCycles = [2, 1];
765 def : InstRW<[WriteRCr1], (instregex "RC(R|L)(8|16|32|64)r1")>;
768 def WriteRCm1 : SchedWriteRes<[]> {
771 def : InstRW<[WriteRCm1], (instregex "RC(R|L)(8|16|32|64)m1")>;
774 def WriteRCri : SchedWriteRes<[HWPort0156]> {
778 def : InstRW<[WriteRCri], (instregex "RC(R|L)(8|16|32|64)r(i|CL)")>;
781 def WriteRCmi : SchedWriteRes<[]> {
782 let NumMicroOps = 11;
784 def : InstRW<[WriteRCmi], (instregex "RC(R|L)(8|16|32|64)m(i|CL)")>;
788 def WriteShDrr : SchedWriteRes<[HWPort1]> {
791 def : InstRW<[WriteShDrr], (instregex "SH(R|L)D(16|32|64)rri8")>;
794 def WriteShDmr : SchedWriteRes<[]> {
797 def : InstRW<[WriteShDmr], (instregex "SH(R|L)D(16|32|64)mri8")>;
800 def WriteShlDCL : SchedWriteRes<[HWPort0156]> {
804 def : InstRW<[WriteShlDCL], (instregex "SHLD(16|32|64)rrCL")>;
807 def WriteShrDCL : SchedWriteRes<[HWPort0156]> {
811 def : InstRW<[WriteShrDCL], (instregex "SHRD(16|32|64)rrCL")>;
814 def WriteShDmrCL : SchedWriteRes<[]> {
817 def : InstRW<[WriteShDmrCL], (instregex "SH(R|L)D(16|32|64)mrCL")>;
821 def : InstRW<[WriteShift], (instregex "BT(16|32|64)r(r|i8)")>;
824 def WriteBTmr : SchedWriteRes<[]> {
825 let NumMicroOps = 10;
827 def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
830 def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
834 def : InstRW<[WriteShift], (instregex "BT(R|S|C)(16|32|64)r(r|i8)")>;
837 def WriteBTRSCmr : SchedWriteRes<[]> {
838 let NumMicroOps = 11;
840 def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
843 def : InstRW<[WriteShiftLd], (instregex "BT(R|S|C)(16|32|64)mi8")>;
847 def : InstRW<[WriteP1_Lat3], (instregex "BS(R|F)(16|32|64)rr")>;
849 def : InstRW<[WriteP1_Lat3Ld], (instregex "BS(R|F)(16|32|64)rm")>;
853 def : InstRW<[WriteShift],
854 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)r")>;
856 def WriteSetCCm : SchedWriteRes<[HWPort06, HWPort237, HWPort4]> {
859 def : InstRW<[WriteSetCCm],
860 (instregex "SET(O|NO|B|AE|E|NE|BE|A|S|NS|P|NP|L|GE|LE|G)m")>;
863 def WriteCldStd : SchedWriteRes<[HWPort15, HWPort6]> {
866 def : InstRW<[WriteCldStd], (instregex "STD", "CLD")>;
870 def : InstRW<[WriteP1_Lat3], (instregex "(L|TZCNT)(16|32|64)rr")>;
872 def : InstRW<[WriteP1_Lat3Ld], (instregex "(L|TZCNT)(16|32|64)rm")>;
876 def : InstRW<[WriteP15], (instregex "ANDN(32|64)rr")>;
878 def : InstRW<[WriteP15Ld], (instregex "ANDN(32|64)rm")>;
882 def : InstRW<[WriteP15], (instregex "BLS(I|MSK|R)(32|64)rr")>;
884 def : InstRW<[WriteP15Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>;
888 def : InstRW<[Write2P0156_Lat2], (instregex "BEXTR(32|64)rr")>;
890 def : InstRW<[Write2P0156_Lat2Ld], (instregex "BEXTR(32|64)rm")>;
894 def : InstRW<[WriteP15], (instregex "BZHI(32|64)rr")>;
896 def : InstRW<[WriteP15Ld], (instregex "BZHI(32|64)rm")>;
900 def : InstRW<[WriteP1_Lat3], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>;
902 def : InstRW<[WriteP1_Lat3Ld], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>;
904 //-- Control transfer instructions --//
907 def WriteJCXZ : SchedWriteRes<[HWPort0156, HWPort6]> {
910 def : InstRW<[WriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>;
913 def WriteLOOP : SchedWriteRes<[]> {
916 def : InstRW<[WriteLOOP], (instregex "LOOP")>;
919 def WriteLOOPE : SchedWriteRes<[]> {
920 let NumMicroOps = 11;
922 def : InstRW<[WriteLOOPE], (instregex "LOOPE", "LOOPNE")>;
926 def WriteCALLr : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
929 def : InstRW<[WriteCALLr], (instregex "CALL(16|32)r")>;
932 def WriteCALLm : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
934 let ResourceCycles = [2, 1, 1];
936 def : InstRW<[WriteCALLm], (instregex "CALL(16|32)m")>;
939 def WriteRET : SchedWriteRes<[HWPort237, HWPort6]> {
942 def : InstRW<[WriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)")>;
945 def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
947 let ResourceCycles = [1, 2, 1];
949 def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
953 def WriteBOUND : SchedWriteRes<[]> {
954 let NumMicroOps = 15;
956 def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>;
959 def WriteINTO : SchedWriteRes<[]> {
962 def : InstRW<[WriteINTO], (instregex "INTO")>;
964 //-- String instructions --//
967 def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
970 def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
973 def WriteSTOS : SchedWriteRes<[HWPort23, HWPort0156, HWPort4]> {
976 def : InstRW<[WriteSTOS], (instregex "STOS(B|L|Q|W)")>;
979 def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
982 let ResourceCycles = [2, 1, 2];
984 def : InstRW<[WriteMOVS], (instregex "MOVS(B|L|Q|W)")>;
987 def : InstRW<[Write2P0156_P23], (instregex "SCAS(B|W|L|Q)")>;
990 def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
993 let ResourceCycles = [2, 3];
995 def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
997 //-- Synchronization instructions --//
1000 def WriteXADD : SchedWriteRes<[]> {
1001 let NumMicroOps = 5;
1003 def : InstRW<[WriteXADD], (instregex "XADD(8|16|32|64)rm")>;
1006 def WriteCMPXCHG : SchedWriteRes<[]> {
1007 let NumMicroOps = 6;
1009 def : InstRW<[WriteCMPXCHG], (instregex "CMPXCHG(8|16|32|64)rm")>;
1012 def WriteCMPXCHG8B : SchedWriteRes<[]> {
1013 let NumMicroOps = 15;
1015 def : InstRW<[WriteCMPXCHG8B], (instregex "CMPXCHG8B")>;
1018 def WriteCMPXCHG16B : SchedWriteRes<[]> {
1019 let NumMicroOps = 22;
1021 def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
1026 def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> {
1027 let NumMicroOps = 5;
1028 let ResourceCycles = [1, 3];
1030 def : InstRW<[WritePAUSE], (instregex "PAUSE")>;
1033 def : InstRW<[Write2P0156_P23], (instregex "LEAVE")>;
1036 def WriteXGETBV : SchedWriteRes<[]> {
1037 let NumMicroOps = 8;
1039 def : InstRW<[WriteXGETBV], (instregex "XGETBV")>;
1042 def WriteRDTSC : SchedWriteRes<[]> {
1043 let NumMicroOps = 15;
1045 def : InstRW<[WriteRDTSC], (instregex "RDTSC")>;
1048 def WriteRDPMC : SchedWriteRes<[]> {
1049 let NumMicroOps = 34;
1051 def : InstRW<[WriteRDPMC], (instregex "RDPMC")>;
1054 def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
1055 let NumMicroOps = 17;
1056 let ResourceCycles = [1, 16];
1058 def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
1060 //=== Floating Point x87 Instructions ===//
1061 //-- Move instructions --//
1065 def : InstRW<[WriteP01], (instregex "LD_Frr")>;
1067 def WriteLD_F80m : SchedWriteRes<[HWPort01, HWPort23]> {
1069 let NumMicroOps = 4;
1070 let ResourceCycles = [2, 2];
1072 def : InstRW<[WriteLD_F80m], (instregex "LD_F80m")>;
1076 def WriteFBLD : SchedWriteRes<[]> {
1078 let NumMicroOps = 43;
1080 def : InstRW<[WriteFBLD], (instregex "FBLDm")>;
1084 def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
1087 def WriteST_FP80m : SchedWriteRes<[HWPort0156, HWPort23, HWPort4]> {
1088 let NumMicroOps = 7;
1089 let ResourceCycles = [3, 2, 2];
1091 def : InstRW<[WriteST_FP80m], (instregex "ST_FP80m")>;
1095 def WriteFBSTP : SchedWriteRes<[]> {
1096 let NumMicroOps = 226;
1098 def : InstRW<[WriteFBSTP], (instregex "FBSTPm")>;
1101 def : InstRW<[WriteNop], (instregex "XCH_F")>;
1104 def WriteFILD : SchedWriteRes<[HWPort01, HWPort23]> {
1106 let NumMicroOps = 2;
1108 def : InstRW<[WriteFILD], (instregex "ILD_F(16|32|64)m")>;
1111 def WriteFIST : SchedWriteRes<[HWPort1, HWPort23, HWPort4]> {
1113 let NumMicroOps = 3;
1115 def : InstRW<[WriteFIST], (instregex "IST_(F|FP)(16|32)m")>;
1118 def : InstRW<[WriteP01], (instregex "LD_F0")>;
1121 def : InstRW<[Write2P01], (instregex "LD_F1")>;
1123 // FLDPI FLDL2E etc.
1124 def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)" "FLDL(G|N)2")>;
1127 def WriteFCMOVcc : SchedWriteRes<[HWPort0, HWPort5]> {
1129 let NumMicroOps = 3;
1130 let ResourceCycles = [2, 1];
1132 def : InstRW<[WriteFCMOVcc], (instregex "CMOV(B|BE|P|NB|NBE|NE|NP)_F")>;
1136 def WriteFNSTSW : SchedWriteRes<[HWPort0, HWPort0156]> {
1137 let NumMicroOps = 2;
1139 def : InstRW<[WriteFNSTSW], (instregex "FNSTSW16r")>;
1142 def WriteFNSTSWm : SchedWriteRes<[HWPort0, HWPort4, HWPort237]> {
1144 let NumMicroOps = 3;
1146 def : InstRW<[WriteFNSTSWm], (instregex "FNSTSWm")>;
1149 def WriteFLDCW : SchedWriteRes<[HWPort01, HWPort23, HWPort6]> {
1151 let NumMicroOps = 3;
1153 def : InstRW<[WriteFLDCW], (instregex "FLDCW16m")>;
1156 def WriteFNSTCW : SchedWriteRes<[HWPort237, HWPort4, HWPort6]> {
1157 let NumMicroOps = 3;
1159 def : InstRW<[WriteFNSTCW], (instregex "FNSTCW16m")>;
1162 def : InstRW<[WriteP01], (instregex "FINCSTP", "FDECSTP")>;
1165 def : InstRW<[WriteP01], (instregex "FFREE")>;
1168 def WriteFNSAVE : SchedWriteRes<[]> {
1169 let NumMicroOps = 147;
1171 def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>;
1174 def WriteFRSTOR : SchedWriteRes<[]> {
1175 let NumMicroOps = 90;
1177 def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>;
1179 //-- Arithmetic instructions --//
1182 def : InstRW<[WriteP0], (instregex "ABS_F")>;
1185 def : InstRW<[WriteP0], (instregex "CHS_F")>;
1187 // FCOM(P) FUCOM(P).
1189 def : InstRW<[WriteP1], (instregex "COM_FST0r", "COMP_FST0r", "UCOM_Fr",
1192 def : InstRW<[WriteP1_P23], (instregex "FCOM(32|64)m", "FCOMP(32|64)m")>;
1196 def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
1198 // FCOMI(P) FUCOMI(P).
1200 def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
1204 def : InstRW<[Write2P1_P23], (instregex "FICOM(16|32)m", "FICOMP(16|32)m")>;
1207 def : InstRW<[WriteP1], (instregex "TST_F")>;
1210 def : InstRW<[Write2P1], (instregex "FXAM")>;
1213 def WriteFPREM : SchedWriteRes<[]> {
1215 let NumMicroOps = 28;
1217 def : InstRW<[WriteFPREM], (instregex "FPREM")>;
1220 def WriteFPREM1 : SchedWriteRes<[]> {
1222 let NumMicroOps = 41;
1224 def : InstRW<[WriteFPREM1], (instregex "FPREM1")>;
1227 def WriteFRNDINT : SchedWriteRes<[]> {
1229 let NumMicroOps = 17;
1231 def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
1233 //-- Math instructions --//
1236 def WriteFSCALE : SchedWriteRes<[]> {
1237 let Latency = 75; // 49-125
1238 let NumMicroOps = 50; // 25-75
1240 def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
1243 def WriteFXTRACT : SchedWriteRes<[]> {
1245 let NumMicroOps = 17;
1247 def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;
1249 //-- Other instructions --//
1252 def : InstRW<[WriteP01], (instregex "FNOP")>;
1255 def : InstRW<[Write2P01], (instregex "WAIT")>;
1258 def : InstRW<[Write5P0156], (instregex "FNCLEX")>;
1261 def WriteFNINIT : SchedWriteRes<[]> {
1262 let NumMicroOps = 26;
1264 def : InstRW<[WriteFNINIT], (instregex "FNINIT")>;
1266 //=== Integer MMX and XMM Instructions ===//
1267 //-- Move instructions --//
1271 def : InstRW<[WriteP0], (instregex "MMX_MOVD64grr", "MMX_MOVD64from64rr",
1272 "VMOVPDI2DIrr", "MOVPDI2DIrr")>;
1275 def : InstRW<[WriteP5], (instregex "MMX_MOVD64rr", "MMX_MOVD64to64rr",
1276 "VMOVDI2PDIrr", "MOVDI2PDIrr")>;
1280 def : InstRW<[WriteP0], (instregex "VMOVPQIto64rr")>;
1283 def : InstRW<[WriteP5], (instregex "VMOV64toPQIrr", "VMOVZQI2PQIrr")>;
1286 def : InstRW<[WriteP015], (instregex "MMX_MOVQ64rr")>;
1290 def : InstRW<[WriteP015], (instregex "MOVDQ(A|U)rr", "VMOVDQ(A|U)rr",
1291 "MOVDQ(A|U)rr_REV", "VMOVDQ(A|U)rr_REV",
1292 "VMOVDQ(A|U)Yrr", "VMOVDQ(A|U)Yrr_REV")>;
1295 def : InstRW<[WriteP01_P5], (instregex "MMX_MOVDQ2Qrr")>;
1298 def : InstRW<[WriteP015], (instregex "MMX_MOVQ2DQrr")>;
1303 def WriteMMXPACKSSrr : SchedWriteRes<[HWPort5]> {
1305 let NumMicroOps = 3;
1306 let ResourceCycles = [3];
1308 def : InstRW<[WriteMMXPACKSSrr], (instregex "MMX_PACKSSDWirr",
1309 "MMX_PACKSSWBirr", "MMX_PACKUSWBirr")>;
1312 def WriteMMXPACKSSrm : SchedWriteRes<[HWPort23, HWPort5]> {
1314 let NumMicroOps = 3;
1315 let ResourceCycles = [1, 3];
1317 def : InstRW<[WriteMMXPACKSSrm], (instregex "MMX_PACKSSDWirm",
1318 "MMX_PACKSSWBirm", "MMX_PACKUSWBirm")>;
1320 // VPMOVSX/ZX BW BD BQ DW DQ.
1322 def WriteVPMOVSX : SchedWriteRes<[HWPort5]> {
1324 let NumMicroOps = 1;
1326 def : InstRW<[WriteVPMOVSX], (instregex "VPMOV(SX|ZX)(BW|BQ|DW|DQ)Yrr")>;
1330 def WritePBLENDWr : SchedWriteRes<[HWPort5]>;
1331 def : InstRW<[WritePBLENDWr], (instregex "(V?)PBLENDW(Y?)rri")>;
1334 def WritePBLENDWm : SchedWriteRes<[HWPort5, HWPort23]> {
1335 let NumMicroOps = 2;
1337 let ResourceCycles = [1, 1];
1339 def : InstRW<[WritePBLENDWm, ReadAfterLd], (instregex "(V?)PBLENDW(Y?)rmi")>;
1343 def WriteVPBLENDDr : SchedWriteRes<[HWPort015]>;
1344 def : InstRW<[WriteVPBLENDDr], (instregex "VPBLENDD(Y?)rri")>;
1347 def WriteVPBLENDDm : SchedWriteRes<[HWPort015, HWPort23]> {
1348 let NumMicroOps = 2;
1350 let ResourceCycles = [1, 1];
1352 def : InstRW<[WriteVPBLENDDm, ReadAfterLd], (instregex "VPBLENDD(Y?)rmi")>;
1355 def WriteMASKMOVQ : SchedWriteRes<[HWPort0, HWPort4, HWPort23]> {
1357 let NumMicroOps = 4;
1358 let ResourceCycles = [1, 1, 2];
1360 def : InstRW<[WriteMASKMOVQ], (instregex "MMX_MASKMOVQ(64)?")>;
1363 def WriteMASKMOVDQU : SchedWriteRes<[HWPort04, HWPort56, HWPort23]> {
1365 let NumMicroOps = 10;
1366 let ResourceCycles = [4, 2, 4];
1368 def : InstRW<[WriteMASKMOVDQU], (instregex "(V?)MASKMOVDQU(64)?")>;
1372 def WriteVPMASKMOVr : SchedWriteRes<[HWPort5, HWPort23]> {
1374 let NumMicroOps = 3;
1375 let ResourceCycles = [2, 1];
1377 def : InstRW<[WriteVPMASKMOVr, ReadAfterLd],
1378 (instregex "VPMASKMOV(D|Q)(Y?)rm")>;
1381 def WriteVPMASKMOVm : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1383 let NumMicroOps = 4;
1384 let ResourceCycles = [1, 1, 1, 1];
1386 def : InstRW<[WriteVPMASKMOVm], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
1389 def WritePMOVMSKB : SchedWriteRes<[HWPort0]> {
1392 def : InstRW<[WritePMOVMSKB], (instregex "(V|MMX_)?PMOVMSKB(Y?)rr")>;
1396 def WritePEXTRr : SchedWriteRes<[HWPort0, HWPort5]> {
1398 let NumMicroOps = 2;
1399 let ResourceCycles = [1, 1];
1401 def : InstRW<[WritePEXTRr], (instregex "PEXTR(B|W|D|Q)rr", "MMX_PEXTRWirri")>;
1404 def WritePEXTRm : SchedWriteRes<[HWPort23, HWPort4, HWPort5]> {
1405 let NumMicroOps = 3;
1406 let ResourceCycles = [1, 1, 1];
1408 def : InstRW<[WritePEXTRm], (instregex "PEXTR(B|W|D|Q)mr")>;
1412 def WriteVPBROADCAST128Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1414 let NumMicroOps = 3;
1415 let ResourceCycles = [1, 1, 1];
1417 def : InstRW<[WriteVPBROADCAST128Ld, ReadAfterLd],
1418 (instregex "VPBROADCAST(B|W)rm")>;
1421 def WriteVPBROADCAST256Ld : SchedWriteRes<[HWPort01, HWPort23, HWPort5]> {
1423 let NumMicroOps = 3;
1424 let ResourceCycles = [1, 1, 1];
1426 def : InstRW<[WriteVPBROADCAST256Ld, ReadAfterLd],
1427 (instregex "VPBROADCAST(B|W)Yrm")>;
1431 def WriteVPGATHERDD128 : SchedWriteRes<[]> {
1432 let NumMicroOps = 20;
1434 def : InstRW<[WriteVPGATHERDD128, ReadAfterLd], (instregex "VPGATHERDDrm")>;
1437 def WriteVPGATHERDD256 : SchedWriteRes<[]> {
1438 let NumMicroOps = 34;
1440 def : InstRW<[WriteVPGATHERDD256, ReadAfterLd], (instregex "VPGATHERDDYrm")>;
1444 def WriteVPGATHERQD128 : SchedWriteRes<[]> {
1445 let NumMicroOps = 15;
1447 def : InstRW<[WriteVPGATHERQD128, ReadAfterLd], (instregex "VPGATHERQDrm")>;
1450 def WriteVPGATHERQD256 : SchedWriteRes<[]> {
1451 let NumMicroOps = 22;
1453 def : InstRW<[WriteVPGATHERQD256, ReadAfterLd], (instregex "VPGATHERQDYrm")>;
1457 def WriteVPGATHERDQ128 : SchedWriteRes<[]> {
1458 let NumMicroOps = 12;
1460 def : InstRW<[WriteVPGATHERDQ128, ReadAfterLd], (instregex "VPGATHERDQrm")>;
1463 def WriteVPGATHERDQ256 : SchedWriteRes<[]> {
1464 let NumMicroOps = 20;
1466 def : InstRW<[WriteVPGATHERDQ256, ReadAfterLd], (instregex "VPGATHERDQYrm")>;
1470 def WriteVPGATHERQQ128 : SchedWriteRes<[]> {
1471 let NumMicroOps = 14;
1473 def : InstRW<[WriteVPGATHERQQ128, ReadAfterLd], (instregex "VPGATHERQQrm")>;
1476 def WriteVPGATHERQQ256 : SchedWriteRes<[]> {
1477 let NumMicroOps = 22;
1479 def : InstRW<[WriteVPGATHERQQ256, ReadAfterLd], (instregex "VPGATHERQQYrm")>;
1481 //-- Arithmetic instructions --//
1483 // PHADD|PHSUB (S) W/D.
1485 def WritePHADDSUBr : SchedWriteRes<[HWPort1, HWPort5]> {
1487 let NumMicroOps = 3;
1488 let ResourceCycles = [1, 2];
1490 def : InstRW<[WritePHADDSUBr], (instregex "MMX_PHADD(W?)rr64",
1492 "MMX_PHSUB(W|D)rr64",
1494 "(V?)PH(ADD|SUB)(W|D)(Y?)rr",
1495 "(V?)PH(ADD|SUB)SWrr(256)?")>;
1498 def WritePHADDSUBm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1500 let NumMicroOps = 3;
1501 let ResourceCycles = [1, 2, 1];
1503 def : InstRW<[WritePHADDSUBm, ReadAfterLd],
1504 (instregex "MMX_PHADD(W?)rm64",
1506 "MMX_PHSUB(W|D)rm64",
1508 "(V?)PH(ADD|SUB)(W|D)(Y?)rm",
1509 "(V?)PH(ADD|SUB)SWrm(128|256)?")>;
1513 def WritePCMPGTQr : SchedWriteRes<[HWPort0]> {
1515 let NumMicroOps = 1;
1517 def : InstRW<[WritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>;
1520 def WritePCMPGTQm : SchedWriteRes<[HWPort0, HWPort23]> {
1522 let NumMicroOps = 2;
1523 let ResourceCycles = [1, 1];
1525 def : InstRW<[WritePCMPGTQm, ReadAfterLd], (instregex "(V?)PCMPGTQ(Y?)rm")>;
1529 def WritePMULLDr : SchedWriteRes<[HWPort0]> {
1531 let NumMicroOps = 2;
1532 let ResourceCycles = [2];
1534 def : InstRW<[WritePMULLDr], (instregex "(V?)PMULLD(Y?)rr")>;
1537 def WritePMULLDm : SchedWriteRes<[HWPort0, HWPort23]> {
1539 let NumMicroOps = 3;
1540 let ResourceCycles = [2, 1];
1542 def : InstRW<[WritePMULLDm, ReadAfterLd], (instregex "(V?)PMULLD(Y?)rm")>;
1544 //-- Logic instructions --//
1548 def WritePTESTr : SchedWriteRes<[HWPort0, HWPort5]> {
1550 let NumMicroOps = 2;
1551 let ResourceCycles = [1, 1];
1553 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rr")>;
1556 def WritePTESTm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> {
1558 let NumMicroOps = 3;
1559 let ResourceCycles = [1, 1, 1];
1561 def : InstRW<[WritePTESTr], (instregex "(V?)PTEST(Y?)rm")>;
1563 // PSLL,PSRL,PSRA W/D/Q.
1565 def WritePShift : SchedWriteRes<[HWPort0, HWPort5]> {
1567 let NumMicroOps = 2;
1568 let ResourceCycles = [1, 1];
1570 def : InstRW<[WritePShift], (instregex "(V?)PS(LL|RL|RA)(W|D|Q)(Y?)rr")>;
1573 def : InstRW<[WriteP5], (instregex "(V?)PS(R|L)LDQ(Y?)ri")>;
1578 def WriteEMMS : SchedWriteRes<[]> {
1580 let NumMicroOps = 31;
1582 def : InstRW<[WriteEMMS], (instregex "MMX_EMMS")>;
1584 //=== Floating Point XMM and YMM Instructions ===//
1585 //-- Move instructions --//
1589 def WriteMOVMSKPr : SchedWriteRes<[HWPort0]> {
1592 def : InstRW<[WriteMOVMSKPr], (instregex "(V?)MOVMSKP(S|D)rr")>;
1595 def WriteVMOVMSKPYr : SchedWriteRes<[HWPort0]> {
1598 def : InstRW<[WriteVMOVMSKPYr], (instregex "VMOVMSKP(S|D)Yrr")>;
1601 def : InstRW<[WriteFShuffle256], (instregex "VPERM2F128rr")>;
1602 def : InstRW<[WriteFShuffle256Ld, ReadAfterLd], (instregex "VPERM2F128rm")>;
1605 def : InstRW<[WriteFVarBlend], (instregex "BLENDVP(S|D)rr0")>;
1606 def : InstRW<[WriteFVarBlendLd, ReadAfterLd], (instregex "BLENDVP(S|D)rm0")>;
1609 def : InstRW<[WriteLoad], (instregex "VBROADCASTF128")>;
1613 def WriteEXTRACTPSr : SchedWriteRes<[HWPort0, HWPort5]> {
1614 let NumMicroOps = 2;
1615 let ResourceCycles = [1, 1];
1617 def : InstRW<[WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
1620 def WriteEXTRACTPSm : SchedWriteRes<[HWPort0, HWPort5, HWPort23]> {
1622 let NumMicroOps = 3;
1623 let ResourceCycles = [1, 1, 1];
1625 def : InstRW<[WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
1629 def : InstRW<[WriteFShuffle256], (instregex "VEXTRACTF128rr")>;
1632 def WriteVEXTRACTF128m : SchedWriteRes<[HWPort23, HWPort4]> {
1634 let NumMicroOps = 2;
1635 let ResourceCycles = [1, 1];
1637 def : InstRW<[WriteVEXTRACTF128m], (instregex "VEXTRACTF128mr")>;
1641 def : InstRW<[WriteFShuffle256], (instregex "VINSERTF128rr")>;
1644 def WriteVINSERTF128m : SchedWriteRes<[HWPort015, HWPort23]> {
1646 let NumMicroOps = 2;
1647 let ResourceCycles = [1, 1];
1649 def : InstRW<[WriteFShuffle256, ReadAfterLd], (instregex "VINSERTF128rm")>;
1653 def WriteVMASKMOVPrm : SchedWriteRes<[HWPort5, HWPort23]> {
1655 let NumMicroOps = 3;
1656 let ResourceCycles = [2, 1];
1658 def : InstRW<[WriteVMASKMOVPrm], (instregex "VMASKMOVP(S|D)(Y?)rm")>;
1661 def WriteVMASKMOVPmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1663 let NumMicroOps = 4;
1664 let ResourceCycles = [1, 1, 1, 1];
1666 def : InstRW<[WriteVMASKMOVPmr], (instregex "VMASKMOVP(S|D)mr")>;
1669 def WriteVMASKMOVPYmr : SchedWriteRes<[HWPort0, HWPort1, HWPort4, HWPort23]> {
1671 let NumMicroOps = 4;
1672 let ResourceCycles = [1, 1, 1, 1];
1674 def : InstRW<[WriteVMASKMOVPYmr], (instregex "VMASKMOVP(S|D)Ymr")>;
1678 def WriteVGATHERDPS128 : SchedWriteRes<[]> {
1679 let NumMicroOps = 20;
1681 def : InstRW<[WriteVGATHERDPS128, ReadAfterLd], (instregex "VGATHERDPSrm")>;
1684 def WriteVGATHERDPS256 : SchedWriteRes<[]> {
1685 let NumMicroOps = 34;
1687 def : InstRW<[WriteVGATHERDPS256, ReadAfterLd], (instregex "VGATHERDPSYrm")>;
1691 def WriteVGATHERQPS128 : SchedWriteRes<[]> {
1692 let NumMicroOps = 15;
1694 def : InstRW<[WriteVGATHERQPS128, ReadAfterLd], (instregex "VGATHERQPSrm")>;
1697 def WriteVGATHERQPS256 : SchedWriteRes<[]> {
1698 let NumMicroOps = 22;
1700 def : InstRW<[WriteVGATHERQPS256, ReadAfterLd], (instregex "VGATHERQPSYrm")>;
1704 def WriteVGATHERDPD128 : SchedWriteRes<[]> {
1705 let NumMicroOps = 12;
1707 def : InstRW<[WriteVGATHERDPD128, ReadAfterLd], (instregex "VGATHERDPDrm")>;
1710 def WriteVGATHERDPD256 : SchedWriteRes<[]> {
1711 let NumMicroOps = 20;
1713 def : InstRW<[WriteVGATHERDPD256, ReadAfterLd], (instregex "VGATHERDPDYrm")>;
1717 def WriteVGATHERQPD128 : SchedWriteRes<[]> {
1718 let NumMicroOps = 14;
1720 def : InstRW<[WriteVGATHERQPD128, ReadAfterLd], (instregex "VGATHERQPDrm")>;
1723 def WriteVGATHERQPD256 : SchedWriteRes<[]> {
1724 let NumMicroOps = 22;
1726 def : InstRW<[WriteVGATHERQPD256, ReadAfterLd], (instregex "VGATHERQPDYrm")>;
1728 //-- Conversion instructions --//
1732 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVTPD2PSrr")>;
1735 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVTPD2PS(X?)rm")>;
1738 def WriteCVTPD2PSYrr : SchedWriteRes<[HWPort1, HWPort5]> {
1740 let NumMicroOps = 2;
1741 let ResourceCycles = [1, 1];
1743 def : InstRW<[WriteCVTPD2PSYrr], (instregex "(V?)CVTPD2PSYrr")>;
1746 def WriteCVTPD2PSYrm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1748 let NumMicroOps = 3;
1749 let ResourceCycles = [1, 1, 1];
1751 def : InstRW<[WriteCVTPD2PSYrm], (instregex "(V?)CVTPD2PSYrm")>;
1755 def : InstRW<[WriteP1_P5_Lat4], (instregex "(Int_)?(V)?CVTSD2SSrr")>;
1758 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(Int_)?(V)?CVTSD2SSrm")>;
1762 def WriteCVTPS2PDrr : SchedWriteRes<[HWPort0, HWPort5]> {
1764 let NumMicroOps = 2;
1765 let ResourceCycles = [1, 1];
1767 def : InstRW<[WriteCVTPS2PDrr], (instregex "(V?)CVTPS2PDrr")>;
1771 def WriteCVTPS2PDrm : SchedWriteRes<[HWPort0, HWPort23]> {
1773 let NumMicroOps = 2;
1774 let ResourceCycles = [1, 1];
1776 def : InstRW<[WriteCVTPS2PDrm], (instregex "(V?)CVTPS2PD(Y?)rm")>;
1779 def WriteVCVTPS2PDYrr : SchedWriteRes<[HWPort0, HWPort5]> {
1781 let NumMicroOps = 2;
1782 let ResourceCycles = [1, 1];
1784 def : InstRW<[WriteVCVTPS2PDYrr], (instregex "VCVTPS2PDYrr")>;
1788 def WriteCVTSS2SDrr : SchedWriteRes<[HWPort0, HWPort5]> {
1790 let NumMicroOps = 2;
1791 let ResourceCycles = [1, 1];
1793 def : InstRW<[WriteCVTSS2SDrr], (instregex "(Int_)?(V?)CVTSS2SDrr")>;
1796 def WriteCVTSS2SDrm : SchedWriteRes<[HWPort0, HWPort23]> {
1798 let NumMicroOps = 2;
1799 let ResourceCycles = [1, 1];
1801 def : InstRW<[WriteCVTSS2SDrm], (instregex "(Int_)?(V?)CVTSS2SDrm")>;
1805 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V)?CVTDQ2PDrr")>;
1808 def : InstRW<[WriteP1_P5_Lat6], (instregex "VCVTDQ2PDYrr")>;
1812 def : InstRW<[WriteP1_P5_Lat4], (instregex "(V?)CVT(T?)PD2DQrr")>;
1814 def : InstRW<[WriteP1_P5_Lat4Ld], (instregex "(V?)CVT(T?)PD2DQrm")>;
1816 def : InstRW<[WriteP1_P5_Lat6], (instregex "VCVT(T?)PD2DQYrr")>;
1818 def : InstRW<[WriteP1_P5_Lat6Ld], (instregex "VCVT(T?)PD2DQYrm")>;
1822 def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PS2PIirr")>;
1826 def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PI2PDirr")>;
1830 def : InstRW<[WriteP1_P5_Lat4], (instregex "MMX_CVT(T?)PD2PIirr")>;
1834 def : InstRW<[WriteP1_P5_Lat4], (instregex "(Int_)?(V?)CVT(T?)SI2SS(64)?rr")>;
1838 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rr")>;
1840 def : InstRW<[WriteP0_P1_Lat4Ld], (instregex "(Int_)?(V?)CVT(T?)SS2SI(64)?rm")>;
1844 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVTSI2SS(64)?rr")>;
1848 def : InstRW<[WriteP0_P1_Lat4], (instregex "(Int_)?(V?)CVT(T?)SD2SI(64)?rr")>;
1850 def : InstRW<[WriteP0_P1_Lat4Ld], (instregex "(Int_)?(V?)CVT(T?)SD2SI(64)?rm")>;
1854 def : InstRW<[WriteP1_P5_Lat4], (instregex "VCVTPS2PH(Y?)rr")>;
1856 def : InstRW<[WriteP1_P5_Lat4Ld, WriteRMW], (instregex "VCVTPS2PH(Y?)mr")>;
1860 def : InstRW<[WriteP1_P5_Lat4], (instregex "VCVTPH2PS(Y?)rr")>;
1862 //-- Arithmetic instructions --//
1866 def WriteHADDSUBPr : SchedWriteRes<[HWPort1, HWPort5]> {
1868 let NumMicroOps = 3;
1869 let ResourceCycles = [1, 2];
1871 def : InstRW<[WriteHADDSUBPr], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rr")>;
1874 def WriteHADDSUBPm : SchedWriteRes<[HWPort1, HWPort5, HWPort23]> {
1876 let NumMicroOps = 4;
1877 let ResourceCycles = [1, 2, 1];
1879 def : InstRW<[WriteHADDSUBPm], (instregex "(V?)H(ADD|SUB)P(S|D)(Y?)rm")>;
1881 // MULL SS/SD PS/PD.
1883 def WriteMULr : SchedWriteRes<[HWPort01]> {
1886 def : InstRW<[WriteMULr], (instregex "(V?)MUL(P|S)(S|D)rr")>;
1889 def WriteMULm : SchedWriteRes<[HWPort01, HWPort23]> {
1891 let NumMicroOps = 2;
1892 let ResourceCycles = [1, 1];
1894 def : InstRW<[WriteMULm], (instregex "(V?)MUL(P|S)(S|D)rm")>;
1898 def WriteVDIVPSYrr : SchedWriteRes<[HWPort0, HWPort15]> {
1899 let Latency = 19; // 18-21 cycles.
1900 let NumMicroOps = 3;
1901 let ResourceCycles = [2, 1];
1903 def : InstRW<[WriteVDIVPSYrr], (instregex "VDIVPSYrr")>;
1906 def WriteVDIVPSYrm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
1907 let Latency = 23; // 18-21 + 4 cycles.
1908 let NumMicroOps = 4;
1909 let ResourceCycles = [2, 1, 1];
1911 def : InstRW<[WriteVDIVPSYrm, ReadAfterLd], (instregex "VDIVPSYrm")>;
1915 def WriteVDIVPDYrr : SchedWriteRes<[HWPort0, HWPort15]> {
1916 let Latency = 27; // 19-35 cycles.
1917 let NumMicroOps = 3;
1918 let ResourceCycles = [2, 1];
1920 def : InstRW<[WriteVDIVPDYrr], (instregex "VDIVPDYrr")>;
1923 def WriteVDIVPDYrm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
1924 let Latency = 31; // 19-35 + 4 cycles.
1925 let NumMicroOps = 4;
1926 let ResourceCycles = [2, 1, 1];
1928 def : InstRW<[WriteVDIVPDYrm, ReadAfterLd], (instregex "VDIVPDYrm")>;
1932 def WriteVRCPPSr : SchedWriteRes<[HWPort0, HWPort15]> {
1934 let NumMicroOps = 3;
1935 let ResourceCycles = [2, 1];
1937 def : InstRW<[WriteVRCPPSr], (instregex "VRCPPSYr(_Int)?")>;
1940 def WriteVRCPPSm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
1942 let NumMicroOps = 4;
1943 let ResourceCycles = [2, 1, 1];
1945 def : InstRW<[WriteVRCPPSm], (instregex "VRCPPSYm(_Int)?")>;
1947 // ROUND SS/SD PS/PD.
1949 def WriteROUNDr : SchedWriteRes<[HWPort1]> {
1951 let NumMicroOps = 2;
1952 let ResourceCycles = [2];
1954 def : InstRW<[WriteROUNDr], (instregex "(V?)ROUND(Y?)(S|P)(S|D)r(_Int)?")>;
1957 def WriteROUNDm : SchedWriteRes<[HWPort1, HWPort23]> {
1959 let NumMicroOps = 3;
1960 let ResourceCycles = [2, 1];
1962 def : InstRW<[WriteROUNDm], (instregex "(V?)ROUND(Y?)(S|P)(S|D)m(_Int)?")>;
1966 def WriteDPPSr : SchedWriteRes<[HWPort0, HWPort1, HWPort5]> {
1968 let NumMicroOps = 4;
1969 let ResourceCycles = [2, 1, 1];
1971 def : InstRW<[WriteDPPSr], (instregex "(V?)DPPS(Y?)rri")>;
1974 def WriteDPPSm : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort23, HWPort6]> {
1976 let NumMicroOps = 6;
1977 let ResourceCycles = [2, 1, 1, 1, 1];
1979 def : InstRW<[WriteDPPSm, ReadAfterLd], (instregex "(V?)DPPS(Y?)rmi")>;
1983 def WriteDPPDr : SchedWriteRes<[HWPort0, HWPort1, HWPort5]> {
1985 let NumMicroOps = 3;
1986 let ResourceCycles = [1, 1, 1];
1988 def : InstRW<[WriteDPPDr], (instregex "(V?)DPPDrri")>;
1991 def WriteDPPDm : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort23]> {
1993 let NumMicroOps = 4;
1994 let ResourceCycles = [1, 1, 1, 1];
1996 def : InstRW<[WriteDPPDm], (instregex "(V?)DPPDrmi")>;
2000 def WriteFMADDr : SchedWriteRes<[HWPort01]> {
2002 let NumMicroOps = 1;
2004 def : InstRW<[WriteFMADDr],
2007 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)r(Y)?",
2009 "VF(N?)M(ADD|SUB)S(S|D)(r132|231|213)r",
2011 "VF(N?)M(ADD|SUB)S(S|D)4rr(_REV|_Int)?",
2013 "VF(N?)M(ADD|SUB)P(S|D)4rr(Y)?(_REV)?")>;
2016 def WriteFMADDm : SchedWriteRes<[HWPort01, HWPort23]> {
2018 let NumMicroOps = 2;
2019 let ResourceCycles = [1, 1];
2021 def : InstRW<[WriteFMADDm],
2024 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)m(Y)?",
2026 "VF(N?)M(ADD|SUB)S(S|D)(r132|231|213)m",
2028 "VF(N?)M(ADD|SUB)S(S|D)4(rm|mr)(_Int)?",
2030 "VF(N?)M(ADD|SUB)P(S|D)4(rm|mr)(Y)?")>;
2032 //-- Math instructions --//
2036 def WriteVSQRTPSYr : SchedWriteRes<[HWPort0, HWPort15]> {
2038 let NumMicroOps = 3;
2039 let ResourceCycles = [2, 1];
2041 def : InstRW<[WriteVSQRTPSYr], (instregex "VSQRTPSYr")>;
2044 def WriteVSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
2046 let NumMicroOps = 4;
2047 let ResourceCycles = [2, 1, 1];
2049 def : InstRW<[WriteVSQRTPSYm], (instregex "VSQRTPSYm")>;
2053 def WriteVSQRTPDYr : SchedWriteRes<[HWPort0, HWPort15]> {
2055 let NumMicroOps = 3;
2056 let ResourceCycles = [2, 1];
2058 def : InstRW<[WriteVSQRTPDYr], (instregex "VSQRTPDYr")>;
2061 def WriteVSQRTPDYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
2063 let NumMicroOps = 4;
2064 let ResourceCycles = [2, 1, 1];
2066 def : InstRW<[WriteVSQRTPDYm], (instregex "VSQRTPDYm")>;
2070 def WriteRSQRTr : SchedWriteRes<[HWPort0]> {
2073 def : InstRW<[WriteRSQRTr], (instregex "(V?)RSQRT(SS|PS)r(_Int)?")>;
2076 def WriteRSQRTm : SchedWriteRes<[HWPort0, HWPort23]> {
2078 let NumMicroOps = 2;
2079 let ResourceCycles = [1, 1];
2081 def : InstRW<[WriteRSQRTm], (instregex "(V?)RSQRT(SS|PS)m(_Int)?")>;
2085 def WriteRSQRTPSYr : SchedWriteRes<[HWPort0, HWPort15]> {
2087 let NumMicroOps = 3;
2088 let ResourceCycles = [2, 1];
2090 def : InstRW<[WriteRSQRTPSYr], (instregex "VRSQRTPSYr(_Int)?")>;
2093 def WriteRSQRTPSYm : SchedWriteRes<[HWPort0, HWPort15, HWPort23]> {
2095 let NumMicroOps = 4;
2096 let ResourceCycles = [2, 1, 1];
2098 def : InstRW<[WriteRSQRTPSYm], (instregex "VRSQRTPSYm(_Int)?")>;
2100 //-- Logic instructions --//
2102 // AND, ANDN, OR, XOR PS/PD.
2104 def : InstRW<[WriteP5], (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rr")>;
2106 def : InstRW<[WriteP5Ld, ReadAfterLd],
2107 (instregex "(V?)(AND|ANDN|OR|XOR)P(S|D)(Y?)rm")>;
2109 //-- Other instructions --//
2112 def WriteVZEROUPPER : SchedWriteRes<[]> {
2113 let NumMicroOps = 4;
2115 def : InstRW<[WriteVZEROUPPER], (instregex "VZEROUPPER")>;
2118 def WriteVZEROALL : SchedWriteRes<[]> {
2119 let NumMicroOps = 12;
2121 def : InstRW<[WriteVZEROALL], (instregex "VZEROALL")>;
2124 def WriteLDMXCSR : SchedWriteRes<[HWPort0, HWPort6, HWPort23]> {
2126 let NumMicroOps = 3;
2127 let ResourceCycles = [1, 1, 1];
2129 def : InstRW<[WriteLDMXCSR], (instregex "(V)?LDMXCSR")>;
2132 def WriteSTMXCSR : SchedWriteRes<[HWPort0, HWPort4, HWPort6, HWPort237]> {
2134 let NumMicroOps = 4;
2135 let ResourceCycles = [1, 1, 1, 1];
2137 def : InstRW<[WriteSTMXCSR], (instregex "(V)?STMXCSR")>;