1 //===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // FIXME: X86-64 have different Dwarf numbers.
27 // 64-bit registers, X86-64 only
28 def RAX : Register<"RAX">, DwarfRegNum<0>;
29 def RDX : Register<"RDX">, DwarfRegNum<1>;
30 def RCX : Register<"RCX">, DwarfRegNum<2>;
31 def RBX : Register<"RBX">, DwarfRegNum<3>;
32 def RSI : Register<"RSI">, DwarfRegNum<4>;
33 def RDI : Register<"RDI">, DwarfRegNum<5>;
34 def RBP : Register<"RBP">, DwarfRegNum<6>;
35 def RSP : Register<"RSP">, DwarfRegNum<7>;
37 def R8 : Register<"R8">, DwarfRegNum<8>;
38 def R9 : Register<"R9">, DwarfRegNum<9>;
39 def R10 : Register<"R10">, DwarfRegNum<10>;
40 def R11 : Register<"R11">, DwarfRegNum<11>;
41 def R12 : Register<"R12">, DwarfRegNum<12>;
42 def R13 : Register<"R13">, DwarfRegNum<13>;
43 def R14 : Register<"R14">, DwarfRegNum<14>;
44 def R15 : Register<"R15">, DwarfRegNum<15>;
47 def EAX : RegisterGroup<"EAX", [RAX]>, DwarfRegNum<0>;
48 def ECX : RegisterGroup<"ECX", [RCX]>, DwarfRegNum<1>;
49 def EDX : RegisterGroup<"EDX", [RDX]>, DwarfRegNum<2>;
50 def EBX : RegisterGroup<"EBX", [RBX]>, DwarfRegNum<3>;
51 def ESP : RegisterGroup<"ESP", [RSP]>, DwarfRegNum<4>;
52 def EBP : RegisterGroup<"EBP", [RBP]>, DwarfRegNum<5>;
53 def ESI : RegisterGroup<"ESI", [RSI]>, DwarfRegNum<6>;
54 def EDI : RegisterGroup<"EDI", [RDI]>, DwarfRegNum<7>;
57 def R8D : RegisterGroup<"R8D", [R8]>, DwarfRegNum<8>;
58 def R9D : RegisterGroup<"R9D", [R9]>, DwarfRegNum<9>;
59 def R10D : RegisterGroup<"R10D", [R10]>, DwarfRegNum<10>;
60 def R11D : RegisterGroup<"R11D", [R11]>, DwarfRegNum<11>;
61 def R12D : RegisterGroup<"R12D", [R12]>, DwarfRegNum<12>;
62 def R13D : RegisterGroup<"R13D", [R13]>, DwarfRegNum<13>;
63 def R14D : RegisterGroup<"R14D", [R14]>, DwarfRegNum<14>;
64 def R15D : RegisterGroup<"R15D", [R15]>, DwarfRegNum<15>;
67 def AX : RegisterGroup<"AX", [EAX,RAX]>, DwarfRegNum<0>;
68 def CX : RegisterGroup<"CX", [ECX,RCX]>, DwarfRegNum<1>;
69 def DX : RegisterGroup<"DX", [EDX,RDX]>, DwarfRegNum<2>;
70 def BX : RegisterGroup<"BX", [EBX,RBX]>, DwarfRegNum<3>;
71 def SP : RegisterGroup<"SP", [ESP,RSP]>, DwarfRegNum<4>;
72 def BP : RegisterGroup<"BP", [EBP,RBP]>, DwarfRegNum<5>;
73 def SI : RegisterGroup<"SI", [ESI,RSI]>, DwarfRegNum<6>;
74 def DI : RegisterGroup<"DI", [EDI,RDI]>, DwarfRegNum<7>;
77 def R8W : RegisterGroup<"R8W", [R8D,R8]>, DwarfRegNum<8>;
78 def R9W : RegisterGroup<"R9W", [R9D,R9]>, DwarfRegNum<9>;
79 def R10W : RegisterGroup<"R10W", [R10D,R10]>, DwarfRegNum<10>;
80 def R11W : RegisterGroup<"R11W", [R11D,R11]>, DwarfRegNum<11>;
81 def R12W : RegisterGroup<"R12W", [R12D,R12]>, DwarfRegNum<12>;
82 def R13W : RegisterGroup<"R13W", [R13D,R13]>, DwarfRegNum<13>;
83 def R14W : RegisterGroup<"R14W", [R14D,R14]>, DwarfRegNum<14>;
84 def R15W : RegisterGroup<"R15W", [R15D,R15]>, DwarfRegNum<15>;
88 def AL : RegisterGroup<"AL", [AX,EAX,RAX]>, DwarfRegNum<0>;
89 def CL : RegisterGroup<"CL", [CX,ECX,RCX]>, DwarfRegNum<1>;
90 def DL : RegisterGroup<"DL", [DX,EDX,RDX]>, DwarfRegNum<2>;
91 def BL : RegisterGroup<"BL", [BX,EBX,RBX]>, DwarfRegNum<3>;
94 def SIL : RegisterGroup<"SIL", [SI,ESI,RSI]>, DwarfRegNum<4>;
95 def DIL : RegisterGroup<"DIL", [DI,EDI,RDI]>, DwarfRegNum<5>;
96 def BPL : RegisterGroup<"BPL", [BP,EBP,RBP]>, DwarfRegNum<6>;
97 def SPL : RegisterGroup<"SPL", [SP,ESP,RSP]>, DwarfRegNum<7>;
98 def R8B : RegisterGroup<"R8B", [R8W,R8D,R8]>, DwarfRegNum<8>;
99 def R9B : RegisterGroup<"R9B", [R9W,R9D,R9]>, DwarfRegNum<9>;
100 def R10B : RegisterGroup<"R10B", [R10W,R10D,R10]>, DwarfRegNum<10>;
101 def R11B : RegisterGroup<"R11B", [R11W,R11D,R11]>, DwarfRegNum<11>;
102 def R12B : RegisterGroup<"R12B", [R12W,R12D,R12]>, DwarfRegNum<12>;
103 def R13B : RegisterGroup<"R13B", [R13W,R13D,R13]>, DwarfRegNum<13>;
104 def R14B : RegisterGroup<"R14B", [R14W,R14D,R14]>, DwarfRegNum<14>;
105 def R15B : RegisterGroup<"R15B", [R15W,R15D,R15]>, DwarfRegNum<15>;
107 // High registers X86-32 only
108 def AH : RegisterGroup<"AH", [AX,EAX,RAX]>, DwarfRegNum<0>;
109 def CH : RegisterGroup<"CH", [CX,ECX,RCX]>, DwarfRegNum<1>;
110 def DH : RegisterGroup<"DH", [DX,EDX,RDX]>, DwarfRegNum<2>;
111 def BH : RegisterGroup<"BH", [BX,EBX,RBX]>, DwarfRegNum<3>;
113 // MMX Registers. These are actually aliased to ST0 .. ST7
114 def MM0 : Register<"MM0">, DwarfRegNum<29>;
115 def MM1 : Register<"MM1">, DwarfRegNum<30>;
116 def MM2 : Register<"MM2">, DwarfRegNum<31>;
117 def MM3 : Register<"MM3">, DwarfRegNum<32>;
118 def MM4 : Register<"MM4">, DwarfRegNum<33>;
119 def MM5 : Register<"MM5">, DwarfRegNum<34>;
120 def MM6 : Register<"MM6">, DwarfRegNum<35>;
121 def MM7 : Register<"MM7">, DwarfRegNum<36>;
123 // Pseudo Floating Point registers
124 def FP0 : Register<"FP0">, DwarfRegNum<-1>;
125 def FP1 : Register<"FP1">, DwarfRegNum<-1>;
126 def FP2 : Register<"FP2">, DwarfRegNum<-1>;
127 def FP3 : Register<"FP3">, DwarfRegNum<-1>;
128 def FP4 : Register<"FP4">, DwarfRegNum<-1>;
129 def FP5 : Register<"FP5">, DwarfRegNum<-1>;
130 def FP6 : Register<"FP6">, DwarfRegNum<-1>;
132 // XMM Registers, used by the various SSE instruction set extensions
133 def XMM0: Register<"XMM0">, DwarfRegNum<17>;
134 def XMM1: Register<"XMM1">, DwarfRegNum<18>;
135 def XMM2: Register<"XMM2">, DwarfRegNum<19>;
136 def XMM3: Register<"XMM3">, DwarfRegNum<20>;
137 def XMM4: Register<"XMM4">, DwarfRegNum<21>;
138 def XMM5: Register<"XMM5">, DwarfRegNum<22>;
139 def XMM6: Register<"XMM6">, DwarfRegNum<23>;
140 def XMM7: Register<"XMM7">, DwarfRegNum<24>;
143 def XMM8: Register<"XMM8">, DwarfRegNum<25>;
144 def XMM9: Register<"XMM9">, DwarfRegNum<26>;
145 def XMM10: Register<"XMM10">, DwarfRegNum<27>;
146 def XMM11: Register<"XMM11">, DwarfRegNum<28>;
147 def XMM12: Register<"XMM12">, DwarfRegNum<29>;
148 def XMM13: Register<"XMM13">, DwarfRegNum<30>;
149 def XMM14: Register<"XMM14">, DwarfRegNum<31>;
150 def XMM15: Register<"XMM15">, DwarfRegNum<32>;
152 // Floating point stack registers
153 def ST0 : Register<"ST(0)">, DwarfRegNum<11>;
154 def ST1 : Register<"ST(1)">, DwarfRegNum<12>;
155 def ST2 : Register<"ST(2)">, DwarfRegNum<13>;
156 def ST3 : Register<"ST(3)">, DwarfRegNum<14>;
157 def ST4 : Register<"ST(4)">, DwarfRegNum<15>;
158 def ST5 : Register<"ST(5)">, DwarfRegNum<16>;
159 def ST6 : Register<"ST(6)">, DwarfRegNum<17>;
160 def ST7 : Register<"ST(7)">, DwarfRegNum<18>;
163 //===----------------------------------------------------------------------===//
164 // Register Class Definitions... now that we have all of the pieces, define the
165 // top-level register classes. The order specified in the register list is
166 // implicitly defined to be the register allocation order.
169 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
170 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
171 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
173 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
174 def GR8 : RegisterClass<"X86", [i8], 8,
175 [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
176 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
177 let MethodProtos = [{
178 iterator allocation_order_begin(const MachineFunction &MF) const;
179 iterator allocation_order_end(const MachineFunction &MF) const;
181 let MethodBodies = [{
182 // Does the function dedicate RBP / EBP to being a frame ptr?
183 // If so, don't allocate SPL or BPL.
184 static const unsigned X86_GR8_AO_64_fp[] =
185 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
186 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
187 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
188 // If not, just don't allocate SPL.
189 static const unsigned X86_GR8_AO_64[] =
190 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
191 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
192 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
193 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
194 static const unsigned X86_GR8_AO_32[] =
195 {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
198 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
199 const TargetMachine &TM = MF.getTarget();
200 const MRegisterInfo *RI = TM.getRegisterInfo();
201 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
202 if (!Subtarget.is64Bit())
203 return X86_GR8_AO_32;
204 else if (RI->hasFP(MF))
205 return X86_GR8_AO_64_fp;
207 return X86_GR8_AO_64;
211 GR8Class::allocation_order_end(const MachineFunction &MF) const {
212 const TargetMachine &TM = MF.getTarget();
213 const MRegisterInfo *RI = TM.getRegisterInfo();
214 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
215 if (!Subtarget.is64Bit())
216 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
217 else if (RI->hasFP(MF))
218 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
220 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
226 def GR16 : RegisterClass<"X86", [i16], 16,
227 [AX, CX, DX, SI, DI, BX, BP, SP,
228 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
229 let MethodProtos = [{
230 iterator allocation_order_begin(const MachineFunction &MF) const;
231 iterator allocation_order_end(const MachineFunction &MF) const;
233 let MethodBodies = [{
234 // Does the function dedicate RBP / EBP to being a frame ptr?
235 // If so, don't allocate SP or BP.
236 static const unsigned X86_GR16_AO_64_fp[] =
237 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
238 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
239 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
240 static const unsigned X86_GR16_AO_32_fp[] =
241 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
242 // If not, just don't allocate SPL.
243 static const unsigned X86_GR16_AO_64[] =
244 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
245 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
246 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
247 static const unsigned X86_GR16_AO_32[] =
248 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
251 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
252 const TargetMachine &TM = MF.getTarget();
253 const MRegisterInfo *RI = TM.getRegisterInfo();
254 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
255 if (Subtarget.is64Bit()) {
257 return X86_GR16_AO_64_fp;
259 return X86_GR16_AO_64;
262 return X86_GR16_AO_32_fp;
264 return X86_GR16_AO_32;
269 GR16Class::allocation_order_end(const MachineFunction &MF) const {
270 const TargetMachine &TM = MF.getTarget();
271 const MRegisterInfo *RI = TM.getRegisterInfo();
272 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
273 if (Subtarget.is64Bit()) {
275 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
277 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
280 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
282 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
289 def GR32 : RegisterClass<"X86", [i32], 32,
290 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
291 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
292 let MethodProtos = [{
293 iterator allocation_order_begin(const MachineFunction &MF) const;
294 iterator allocation_order_end(const MachineFunction &MF) const;
296 let MethodBodies = [{
297 // Does the function dedicate RBP / EBP to being a frame ptr?
298 // If so, don't allocate ESP or EBP.
299 static const unsigned X86_GR32_AO_64_fp[] =
300 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
301 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
302 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
303 static const unsigned X86_GR32_AO_32_fp[] =
304 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
305 // If not, just don't allocate SPL.
306 static const unsigned X86_GR32_AO_64[] =
307 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
308 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
309 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
310 static const unsigned X86_GR32_AO_32[] =
311 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
314 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
315 const TargetMachine &TM = MF.getTarget();
316 const MRegisterInfo *RI = TM.getRegisterInfo();
317 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
318 if (Subtarget.is64Bit()) {
320 return X86_GR32_AO_64_fp;
322 return X86_GR32_AO_64;
325 return X86_GR32_AO_32_fp;
327 return X86_GR32_AO_32;
332 GR32Class::allocation_order_end(const MachineFunction &MF) const {
333 const TargetMachine &TM = MF.getTarget();
334 const MRegisterInfo *RI = TM.getRegisterInfo();
335 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
336 if (Subtarget.is64Bit()) {
338 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
340 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
343 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
345 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
352 def GR64 : RegisterClass<"X86", [i64], 64,
353 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
354 RBX, R14, R15, R12, R13, RBP, RSP]> {
355 let MethodProtos = [{
356 iterator allocation_order_end(const MachineFunction &MF) const;
358 let MethodBodies = [{
360 GR64Class::allocation_order_end(const MachineFunction &MF) const {
361 const TargetMachine &TM = MF.getTarget();
362 const MRegisterInfo *RI = TM.getRegisterInfo();
363 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
364 return end()-2; // If so, don't allocate RSP or RBP
366 return end()-1; // If not, just don't allocate RSP
372 // GR16, GR32 subclasses which contain registers that have R8 sub-registers.
373 // These should only be used for 32-bit mode.
374 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>;
375 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>;
377 // Scalar SSE2 floating point registers.
378 def FR32 : RegisterClass<"X86", [f32], 32,
379 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
380 XMM8, XMM9, XMM10, XMM11,
381 XMM12, XMM13, XMM14, XMM15]> {
382 let MethodProtos = [{
383 iterator allocation_order_end(const MachineFunction &MF) const;
385 let MethodBodies = [{
387 FR32Class::allocation_order_end(const MachineFunction &MF) const {
388 const TargetMachine &TM = MF.getTarget();
389 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
390 if (!Subtarget.is64Bit())
391 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
398 def FR64 : RegisterClass<"X86", [f64], 64,
399 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
400 XMM8, XMM9, XMM10, XMM11,
401 XMM12, XMM13, XMM14, XMM15]> {
402 let MethodProtos = [{
403 iterator allocation_order_end(const MachineFunction &MF) const;
405 let MethodBodies = [{
407 FR64Class::allocation_order_end(const MachineFunction &MF) const {
408 const TargetMachine &TM = MF.getTarget();
409 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
410 if (!Subtarget.is64Bit())
411 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
419 // FIXME: This sets up the floating point register files as though they are f64
420 // values, though they really are f80 values. This will cause us to spill
421 // values as 64-bit quantities instead of 80-bit quantities, which is much much
422 // faster on common hardware. In reality, this should be controlled by a
423 // command line option or something.
425 def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
427 // Floating point stack registers (these are not allocatable by the
428 // register allocator - the floating point stackifier is responsible
429 // for transforming FPn allocations to STn registers)
430 def RST : RegisterClass<"X86", [f64], 32,
431 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
432 let MethodProtos = [{
433 iterator allocation_order_end(const MachineFunction &MF) const;
435 let MethodBodies = [{
437 RSTClass::allocation_order_end(const MachineFunction &MF) const {
443 // Generic vector registers: VR64 and VR128.
444 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
445 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
446 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
447 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
448 XMM8, XMM9, XMM10, XMM11,
449 XMM12, XMM13, XMM14, XMM15]> {
450 let MethodProtos = [{
451 iterator allocation_order_end(const MachineFunction &MF) const;
453 let MethodBodies = [{
455 VR128Class::allocation_order_end(const MachineFunction &MF) const {
456 const TargetMachine &TM = MF.getTarget();
457 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
458 if (!Subtarget.is64Bit())
459 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.