1 //===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 Register file, defining the registers themselves,
11 // aliases between the registers, and the register classes built out of the
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Register definitions...
19 let Namespace = "X86" in {
21 // In the register alias definitions below, we define which registers alias
22 // which others. We only specify which registers the small registers alias,
23 // because the register file generator is smart enough to figure out that
24 // AL aliases AX if we tell it that AX aliased AL (for example).
26 // FIXME: X86-64 have different Dwarf numbers.
27 // 64-bit registers, X86-64 only
28 def RAX : Register<"RAX">, DwarfRegNum<0>;
29 def RDX : Register<"RDX">, DwarfRegNum<1>;
30 def RCX : Register<"RCX">, DwarfRegNum<2>;
31 def RBX : Register<"RBX">, DwarfRegNum<3>;
32 def RSI : Register<"RSI">, DwarfRegNum<4>;
33 def RDI : Register<"RDI">, DwarfRegNum<5>;
34 def RBP : Register<"RBP">, DwarfRegNum<6>;
35 def RSP : Register<"RSP">, DwarfRegNum<7>;
37 def R8 : Register<"R8">, DwarfRegNum<8>;
38 def R9 : Register<"R9">, DwarfRegNum<9>;
39 def R10 : Register<"R10">, DwarfRegNum<10>;
40 def R11 : Register<"R11">, DwarfRegNum<11>;
41 def R12 : Register<"R12">, DwarfRegNum<12>;
42 def R13 : Register<"R13">, DwarfRegNum<13>;
43 def R14 : Register<"R14">, DwarfRegNum<14>;
44 def R15 : Register<"R15">, DwarfRegNum<15>;
47 def EAX : RegisterGroup<"EAX", [RAX]>, DwarfRegNum<0>;
48 def ECX : RegisterGroup<"ECX", [RCX]>, DwarfRegNum<1>;
49 def EDX : RegisterGroup<"EDX", [RDX]>, DwarfRegNum<2>;
50 def EBX : RegisterGroup<"EBX", [RBX]>, DwarfRegNum<3>;
51 def ESP : RegisterGroup<"ESP", [RSP]>, DwarfRegNum<4>;
52 def EBP : RegisterGroup<"EBP", [RBP]>, DwarfRegNum<5>;
53 def ESI : RegisterGroup<"ESI", [RSI]>, DwarfRegNum<6>;
54 def EDI : RegisterGroup<"EDI", [RDI]>, DwarfRegNum<7>;
57 def R8D : RegisterGroup<"R8D", [R8]>, DwarfRegNum<8>;
58 def R9D : RegisterGroup<"R9D", [R9]>, DwarfRegNum<9>;
59 def R10D : RegisterGroup<"R10D", [R10]>, DwarfRegNum<10>;
60 def R11D : RegisterGroup<"R11D", [R11]>, DwarfRegNum<11>;
61 def R12D : RegisterGroup<"R12D", [R12]>, DwarfRegNum<12>;
62 def R13D : RegisterGroup<"R13D", [R13]>, DwarfRegNum<13>;
63 def R14D : RegisterGroup<"R14D", [R14]>, DwarfRegNum<14>;
64 def R15D : RegisterGroup<"R15D", [R15]>, DwarfRegNum<15>;
67 def AX : RegisterGroup<"AX", [EAX,RAX]>, DwarfRegNum<0>;
68 def CX : RegisterGroup<"CX", [ECX,RCX]>, DwarfRegNum<1>;
69 def DX : RegisterGroup<"DX", [EDX,RDX]>, DwarfRegNum<2>;
70 def BX : RegisterGroup<"BX", [EBX,RBX]>, DwarfRegNum<3>;
71 def SP : RegisterGroup<"SP", [ESP,RSP]>, DwarfRegNum<4>;
72 def BP : RegisterGroup<"BP", [EBP,RBP]>, DwarfRegNum<5>;
73 def SI : RegisterGroup<"SI", [ESI,RSI]>, DwarfRegNum<6>;
74 def DI : RegisterGroup<"DI", [EDI,RDI]>, DwarfRegNum<7>;
77 def R8W : RegisterGroup<"R8W", [R8D,R8]>, DwarfRegNum<8>;
78 def R9W : RegisterGroup<"R9W", [R9D,R9]>, DwarfRegNum<9>;
79 def R10W : RegisterGroup<"R10W", [R10D,R10]>, DwarfRegNum<10>;
80 def R11W : RegisterGroup<"R11W", [R11D,R11]>, DwarfRegNum<11>;
81 def R12W : RegisterGroup<"R12W", [R12D,R12]>, DwarfRegNum<12>;
82 def R13W : RegisterGroup<"R13W", [R13D,R13]>, DwarfRegNum<13>;
83 def R14W : RegisterGroup<"R14W", [R14D,R14]>, DwarfRegNum<14>;
84 def R15W : RegisterGroup<"R15W", [R15D,R15]>, DwarfRegNum<15>;
88 def AL : RegisterGroup<"AL", [AX,EAX,RAX]>, DwarfRegNum<0>;
89 def CL : RegisterGroup<"CL", [CX,ECX,RCX]>, DwarfRegNum<1>;
90 def DL : RegisterGroup<"DL", [DX,EDX,RDX]>, DwarfRegNum<2>;
91 def BL : RegisterGroup<"BL", [BX,EBX,RBX]>, DwarfRegNum<3>;
94 def SIL : RegisterGroup<"SIL", [SI,ESI,RSI]>, DwarfRegNum<4>;
95 def DIL : RegisterGroup<"DIL", [DI,EDI,RDI]>, DwarfRegNum<5>;
96 def BPL : RegisterGroup<"BPL", [BP,EBP,RBP]>, DwarfRegNum<6>;
97 def SPL : RegisterGroup<"SPL", [SP,ESP,RSP]>, DwarfRegNum<7>;
98 def R8B : RegisterGroup<"R8B", [R8W,R8D,R8]>, DwarfRegNum<8>;
99 def R9B : RegisterGroup<"R9B", [R9W,R9D,R9]>, DwarfRegNum<9>;
100 def R10B : RegisterGroup<"R10B", [R10W,R10D,R10]>, DwarfRegNum<10>;
101 def R11B : RegisterGroup<"R11B", [R11W,R11D,R11]>, DwarfRegNum<11>;
102 def R12B : RegisterGroup<"R12B", [R12W,R12D,R12]>, DwarfRegNum<12>;
103 def R13B : RegisterGroup<"R13B", [R13W,R13D,R13]>, DwarfRegNum<13>;
104 def R14B : RegisterGroup<"R14B", [R14W,R14D,R14]>, DwarfRegNum<14>;
105 def R15B : RegisterGroup<"R15B", [R15W,R15D,R15]>, DwarfRegNum<15>;
107 // High registers X86-32 only
108 def AH : RegisterGroup<"AH", [AX,EAX,RAX]>, DwarfRegNum<0>;
109 def CH : RegisterGroup<"CH", [CX,ECX,RCX]>, DwarfRegNum<1>;
110 def DH : RegisterGroup<"DH", [DX,EDX,RDX]>, DwarfRegNum<2>;
111 def BH : RegisterGroup<"BH", [BX,EBX,RBX]>, DwarfRegNum<3>;
113 // MMX Registers. These are actually aliased to ST0 .. ST7
114 def MM0 : Register<"MM0">, DwarfRegNum<29>;
115 def MM1 : Register<"MM1">, DwarfRegNum<30>;
116 def MM2 : Register<"MM2">, DwarfRegNum<31>;
117 def MM3 : Register<"MM3">, DwarfRegNum<32>;
118 def MM4 : Register<"MM4">, DwarfRegNum<33>;
119 def MM5 : Register<"MM5">, DwarfRegNum<34>;
120 def MM6 : Register<"MM6">, DwarfRegNum<35>;
121 def MM7 : Register<"MM7">, DwarfRegNum<36>;
123 // Pseudo Floating Point registers
124 def FP0 : Register<"FP0">, DwarfRegNum<-1>;
125 def FP1 : Register<"FP1">, DwarfRegNum<-1>;
126 def FP2 : Register<"FP2">, DwarfRegNum<-1>;
127 def FP3 : Register<"FP3">, DwarfRegNum<-1>;
128 def FP4 : Register<"FP4">, DwarfRegNum<-1>;
129 def FP5 : Register<"FP5">, DwarfRegNum<-1>;
130 def FP6 : Register<"FP6">, DwarfRegNum<-1>;
132 // XMM Registers, used by the various SSE instruction set extensions
133 def XMM0: Register<"XMM0">, DwarfRegNum<17>;
134 def XMM1: Register<"XMM1">, DwarfRegNum<18>;
135 def XMM2: Register<"XMM2">, DwarfRegNum<19>;
136 def XMM3: Register<"XMM3">, DwarfRegNum<20>;
137 def XMM4: Register<"XMM4">, DwarfRegNum<21>;
138 def XMM5: Register<"XMM5">, DwarfRegNum<22>;
139 def XMM6: Register<"XMM6">, DwarfRegNum<23>;
140 def XMM7: Register<"XMM7">, DwarfRegNum<24>;
143 def XMM8: Register<"XMM8">, DwarfRegNum<25>;
144 def XMM9: Register<"XMM9">, DwarfRegNum<26>;
145 def XMM10: Register<"XMM10">, DwarfRegNum<27>;
146 def XMM11: Register<"XMM11">, DwarfRegNum<28>;
147 def XMM12: Register<"XMM12">, DwarfRegNum<29>;
148 def XMM13: Register<"XMM13">, DwarfRegNum<30>;
149 def XMM14: Register<"XMM14">, DwarfRegNum<31>;
150 def XMM15: Register<"XMM15">, DwarfRegNum<32>;
152 // Floating point stack registers
153 def ST0 : Register<"ST(0)">, DwarfRegNum<11>;
154 def ST1 : Register<"ST(1)">, DwarfRegNum<12>;
155 def ST2 : Register<"ST(2)">, DwarfRegNum<13>;
156 def ST3 : Register<"ST(3)">, DwarfRegNum<14>;
157 def ST4 : Register<"ST(4)">, DwarfRegNum<15>;
158 def ST5 : Register<"ST(5)">, DwarfRegNum<16>;
159 def ST6 : Register<"ST(6)">, DwarfRegNum<17>;
160 def ST7 : Register<"ST(7)">, DwarfRegNum<18>;
163 //===----------------------------------------------------------------------===//
164 // Register Class Definitions... now that we have all of the pieces, define the
165 // top-level register classes. The order specified in the register list is
166 // implicitly defined to be the register allocation order.
169 // List call-clobbered registers before callee-save registers. RBX, RBP, (and
170 // R12, R13, R14, and R15 for X86-64) are callee-save registers.
171 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
173 // FIXME: Allow AH, CH, DH, BH in 64-mode for non-REX instructions,
174 def GR8 : RegisterClass<"X86", [i8], 8,
175 [AL, CL, DL, BL, AH, CH, DH, BH, SIL, DIL, BPL, SPL,
176 R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]> {
177 let MethodProtos = [{
178 iterator allocation_order_begin(const MachineFunction &MF) const;
179 iterator allocation_order_end(const MachineFunction &MF) const;
181 let MethodBodies = [{
182 // Does the function dedicate RBP / EBP to being a frame ptr?
183 // If so, don't allocate SPL or BPL.
184 static const unsigned X86_GR8_AO_64_fp[] =
185 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
186 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
187 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B};
188 // If not, just don't allocate SPL.
189 static const unsigned X86_GR8_AO_64[] =
190 {X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
191 X86::R8B, X86::R9B, X86::R10B, X86::R11B,
192 X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL};
193 // In 32-mode, none of the 8-bit registers aliases EBP or ESP.
194 static const unsigned X86_GR8_AO_32[] =
195 {X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH};
198 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
199 const TargetMachine &TM = MF.getTarget();
200 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
201 if (!Subtarget.is64Bit())
202 return X86_GR8_AO_32;
204 return X86_GR8_AO_64_fp;
206 return X86_GR8_AO_64;
210 GR8Class::allocation_order_end(const MachineFunction &MF) const {
211 const TargetMachine &TM = MF.getTarget();
212 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
213 if (!Subtarget.is64Bit())
214 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
216 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
218 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
224 def GR16 : RegisterClass<"X86", [i16], 16,
225 [AX, CX, DX, SI, DI, BX, BP, SP,
226 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]> {
227 let MethodProtos = [{
228 iterator allocation_order_begin(const MachineFunction &MF) const;
229 iterator allocation_order_end(const MachineFunction &MF) const;
231 let MethodBodies = [{
232 // Does the function dedicate RBP / EBP to being a frame ptr?
233 // If so, don't allocate SP or BP.
234 static const unsigned X86_GR16_AO_64_fp[] =
235 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
236 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
237 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W};
238 static const unsigned X86_GR16_AO_32_fp[] =
239 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX};
240 // If not, just don't allocate SPL.
241 static const unsigned X86_GR16_AO_64[] =
242 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI,
243 X86::R8W, X86::R9W, X86::R10W, X86::R11W,
244 X86::BX, X86::R14W, X86::R15W, X86::R12W, X86::R13W, X86::BP};
245 static const unsigned X86_GR16_AO_32[] =
246 {X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP};
249 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
250 const TargetMachine &TM = MF.getTarget();
251 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
252 if (Subtarget.is64Bit()) {
254 return X86_GR16_AO_64_fp;
256 return X86_GR16_AO_64;
259 return X86_GR16_AO_32_fp;
261 return X86_GR16_AO_32;
266 GR16Class::allocation_order_end(const MachineFunction &MF) const {
267 const TargetMachine &TM = MF.getTarget();
268 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
269 if (Subtarget.is64Bit()) {
271 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
273 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
276 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
278 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
285 def GR32 : RegisterClass<"X86", [i32], 32,
286 [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
287 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D]> {
288 let MethodProtos = [{
289 iterator allocation_order_begin(const MachineFunction &MF) const;
290 iterator allocation_order_end(const MachineFunction &MF) const;
292 let MethodBodies = [{
293 // Does the function dedicate RBP / EBP to being a frame ptr?
294 // If so, don't allocate ESP or EBP.
295 static const unsigned X86_GR32_AO_64_fp[] =
296 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
297 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
298 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D};
299 static const unsigned X86_GR32_AO_32_fp[] =
300 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX};
301 // If not, just don't allocate SPL.
302 static const unsigned X86_GR32_AO_64[] =
303 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI,
304 X86::R8D, X86::R9D, X86::R10D, X86::R11D,
305 X86::EBX, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::EBP};
306 static const unsigned X86_GR32_AO_32[] =
307 {X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP};
310 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
311 const TargetMachine &TM = MF.getTarget();
312 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
313 if (Subtarget.is64Bit()) {
315 return X86_GR32_AO_64_fp;
317 return X86_GR32_AO_64;
320 return X86_GR32_AO_32_fp;
322 return X86_GR32_AO_32;
327 GR32Class::allocation_order_end(const MachineFunction &MF) const {
328 const TargetMachine &TM = MF.getTarget();
329 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
330 if (Subtarget.is64Bit()) {
332 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
334 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
337 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
339 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
346 def GR64 : RegisterClass<"X86", [i64], 64,
347 [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
348 RBX, R14, R15, R12, R13, RBP, RSP]> {
349 let MethodProtos = [{
350 iterator allocation_order_end(const MachineFunction &MF) const;
352 let MethodBodies = [{
354 GR64Class::allocation_order_end(const MachineFunction &MF) const {
355 if (hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
356 return end()-2; // If so, don't allocate RSP or RBP
358 return end()-1; // If not, just don't allocate RSP
364 // GR16, GR32 subclasses which contain registers that have R8 sub-registers.
365 // These should only be used for 32-bit mode.
366 def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]>;
367 def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]>;
369 // Scalar SSE2 floating point registers.
370 def FR32 : RegisterClass<"X86", [f32], 32,
371 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
372 XMM8, XMM9, XMM10, XMM11,
373 XMM12, XMM13, XMM14, XMM15]> {
374 let MethodProtos = [{
375 iterator allocation_order_end(const MachineFunction &MF) const;
377 let MethodBodies = [{
379 FR32Class::allocation_order_end(const MachineFunction &MF) const {
380 const TargetMachine &TM = MF.getTarget();
381 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
382 if (!Subtarget.is64Bit())
383 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
390 def FR64 : RegisterClass<"X86", [f64], 64,
391 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
392 XMM8, XMM9, XMM10, XMM11,
393 XMM12, XMM13, XMM14, XMM15]> {
394 let MethodProtos = [{
395 iterator allocation_order_end(const MachineFunction &MF) const;
397 let MethodBodies = [{
399 FR64Class::allocation_order_end(const MachineFunction &MF) const {
400 const TargetMachine &TM = MF.getTarget();
401 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
402 if (!Subtarget.is64Bit())
403 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.
411 // FIXME: This sets up the floating point register files as though they are f64
412 // values, though they really are f80 values. This will cause us to spill
413 // values as 64-bit quantities instead of 80-bit quantities, which is much much
414 // faster on common hardware. In reality, this should be controlled by a
415 // command line option or something.
417 def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
419 // Floating point stack registers (these are not allocatable by the
420 // register allocator - the floating point stackifier is responsible
421 // for transforming FPn allocations to STn registers)
422 def RST : RegisterClass<"X86", [f64], 32,
423 [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
424 let MethodProtos = [{
425 iterator allocation_order_end(const MachineFunction &MF) const;
427 let MethodBodies = [{
429 RSTClass::allocation_order_end(const MachineFunction &MF) const {
435 // Generic vector registers: VR64 and VR128.
436 def VR64 : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
437 [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
438 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
439 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
440 XMM8, XMM9, XMM10, XMM11,
441 XMM12, XMM13, XMM14, XMM15]> {
442 let MethodProtos = [{
443 iterator allocation_order_end(const MachineFunction &MF) const;
445 let MethodBodies = [{
447 VR128Class::allocation_order_end(const MachineFunction &MF) const {
448 const TargetMachine &TM = MF.getTarget();
449 const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
450 if (!Subtarget.is64Bit())
451 return end()-8; // Only XMM0 to XMM7 are available in 32-bit mode.