1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
68 // getDwarfRegNum - This function maps LLVM register identifiers to the
69 // Dwarf specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
74 if (!Subtarget->is64Bit()) {
75 if (Subtarget->isTargetDarwin()) {
77 Flavour = DWARFFlavour::X86_32_DarwinEH;
79 Flavour = DWARFFlavour::X86_32_Generic;
80 } else if (Subtarget->isTargetCygMing()) {
81 // Unsupported by now, just quick fallback
82 Flavour = DWARFFlavour::X86_32_Generic;
84 Flavour = DWARFFlavour::X86_32_Generic;
88 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
91 // getX86RegNum - This function maps LLVM register identifiers to their X86
92 // specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
148 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
149 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
154 const TargetRegisterClass *
155 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
156 if (RC == &X86::CCRRegClass) {
158 return &X86::GR64RegClass;
160 return &X86::GR32RegClass;
166 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
167 bool callsEHReturn = false;
170 const MachineFrameInfo *MFI = MF->getFrameInfo();
171 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
172 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
175 static const unsigned CalleeSavedRegs32Bit[] = {
176 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
179 static const unsigned CalleeSavedRegs32EHRet[] = {
180 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
183 static const unsigned CalleeSavedRegs64Bit[] = {
184 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
187 static const unsigned CalleeSavedRegs64EHRet[] = {
188 X86::RAX, X86::RDX, X86::RBX, X86::R12,
189 X86::R13, X86::R14, X86::R15, X86::RBP, 0
192 static const unsigned CalleeSavedRegsWin64[] = {
193 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
194 X86::R12, X86::R13, X86::R14, X86::R15,
195 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
196 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
197 X86::XMM14, X86::XMM15, 0
202 return CalleeSavedRegsWin64;
204 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
206 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
210 const TargetRegisterClass* const*
211 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
212 bool callsEHReturn = false;
215 const MachineFrameInfo *MFI = MF->getFrameInfo();
216 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
217 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
220 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
221 &X86::GR32RegClass, &X86::GR32RegClass,
222 &X86::GR32RegClass, &X86::GR32RegClass, 0
224 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
225 &X86::GR32RegClass, &X86::GR32RegClass,
226 &X86::GR32RegClass, &X86::GR32RegClass,
227 &X86::GR32RegClass, &X86::GR32RegClass, 0
229 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
230 &X86::GR64RegClass, &X86::GR64RegClass,
231 &X86::GR64RegClass, &X86::GR64RegClass,
232 &X86::GR64RegClass, &X86::GR64RegClass, 0
234 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
235 &X86::GR64RegClass, &X86::GR64RegClass,
236 &X86::GR64RegClass, &X86::GR64RegClass,
237 &X86::GR64RegClass, &X86::GR64RegClass,
238 &X86::GR64RegClass, &X86::GR64RegClass, 0
240 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
241 &X86::GR64RegClass, &X86::GR64RegClass,
242 &X86::GR64RegClass, &X86::GR64RegClass,
243 &X86::GR64RegClass, &X86::GR64RegClass,
244 &X86::GR64RegClass, &X86::GR64RegClass,
245 &X86::VR128RegClass, &X86::VR128RegClass,
246 &X86::VR128RegClass, &X86::VR128RegClass,
247 &X86::VR128RegClass, &X86::VR128RegClass,
248 &X86::VR128RegClass, &X86::VR128RegClass,
249 &X86::VR128RegClass, &X86::VR128RegClass, 0
254 return CalleeSavedRegClassesWin64;
256 return (callsEHReturn ?
257 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
259 return (callsEHReturn ?
260 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
264 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
265 BitVector Reserved(getNumRegs());
266 // Set the stack-pointer register and its aliases as reserved.
267 Reserved.set(X86::RSP);
268 Reserved.set(X86::ESP);
269 Reserved.set(X86::SP);
270 Reserved.set(X86::SPL);
271 // Set the frame-pointer register and its aliases as reserved if needed.
273 Reserved.set(X86::RBP);
274 Reserved.set(X86::EBP);
275 Reserved.set(X86::BP);
276 Reserved.set(X86::BPL);
278 // Mark the x87 stack registers as reserved, since they don't
279 // behave normally with respect to liveness. We don't fully
280 // model the effects of x87 stack pushes and pops after
282 Reserved.set(X86::ST0);
283 Reserved.set(X86::ST1);
284 Reserved.set(X86::ST2);
285 Reserved.set(X86::ST3);
286 Reserved.set(X86::ST4);
287 Reserved.set(X86::ST5);
288 Reserved.set(X86::ST6);
289 Reserved.set(X86::ST7);
293 //===----------------------------------------------------------------------===//
294 // Stack Frame Processing methods
295 //===----------------------------------------------------------------------===//
297 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
298 unsigned MaxAlign = 0;
299 for (int i = FFI->getObjectIndexBegin(),
300 e = FFI->getObjectIndexEnd(); i != e; ++i) {
301 if (FFI->isDeadObjectIndex(i))
303 unsigned Align = FFI->getObjectAlignment(i);
304 MaxAlign = std::max(MaxAlign, Align);
310 // hasFP - Return true if the specified function should have a dedicated frame
311 // pointer register. This is true if the function has variable sized allocas or
312 // if frame pointer elimination is disabled.
314 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
315 const MachineFrameInfo *MFI = MF.getFrameInfo();
316 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
318 return (NoFramePointerElim ||
319 needsStackRealignment(MF) ||
320 MFI->hasVarSizedObjects() ||
321 MFI->isFrameAddressTaken() ||
322 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
323 (MMI && MMI->callsUnwindInit()));
326 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
327 const MachineFrameInfo *MFI = MF.getFrameInfo();;
329 // FIXME: Currently we don't support stack realignment for functions with
330 // variable-sized allocas
331 return (RealignStack &&
332 (MFI->getMaxAlignment() > StackAlign &&
333 !MFI->hasVarSizedObjects()));
336 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
337 return !MF.getFrameInfo()->hasVarSizedObjects();
341 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
342 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
343 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
345 if (needsStackRealignment(MF)) {
347 // Skip the saved EBP
350 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
351 assert( (-(Offset + StackSize)) % Align == 0);
352 return Offset + StackSize;
355 // FIXME: Support tail calls
358 return Offset + StackSize;
360 // Skip the saved EBP
363 // Skip the RETADDR move area
364 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
365 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
366 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
372 void X86RegisterInfo::
373 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
374 MachineBasicBlock::iterator I) const {
375 if (!hasReservedCallFrame(MF)) {
376 // If the stack pointer can be changed after prologue, turn the
377 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
378 // adjcallstackdown instruction into 'add ESP, <amt>'
379 // TODO: consider using push / pop instead of sub + store / add
380 MachineInstr *Old = I;
381 uint64_t Amount = Old->getOperand(0).getImm();
383 // We need to keep the stack aligned properly. To do this, we round the
384 // amount of space needed for the outgoing arguments up to the next
385 // alignment boundary.
386 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
388 MachineInstr *New = 0;
389 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
390 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
391 StackPtr).addReg(StackPtr).addImm(Amount);
393 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
394 // factor out the amount the callee already popped.
395 uint64_t CalleeAmt = Old->getOperand(1).getImm();
398 unsigned Opc = (Amount < 128) ?
399 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
400 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
401 New = BuildMI(MF, TII.get(Opc), StackPtr)
402 .addReg(StackPtr).addImm(Amount);
406 // Replace the pseudo instruction with a new instruction...
407 if (New) MBB.insert(I, New);
409 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
410 // If we are performing frame pointer elimination and if the callee pops
411 // something off the stack pointer, add it back. We do this until we have
412 // more advanced stack pointer tracking ability.
413 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
414 unsigned Opc = (CalleeAmt < 128) ?
415 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
416 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
418 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
426 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
427 int SPAdj, RegScavenger *RS) const{
428 assert(SPAdj == 0 && "Unexpected");
431 MachineInstr &MI = *II;
432 MachineFunction &MF = *MI.getParent()->getParent();
433 while (!MI.getOperand(i).isFI()) {
435 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
438 int FrameIndex = MI.getOperand(i).getIndex();
441 if (needsStackRealignment(MF))
442 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
444 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
446 // This must be part of a four operand memory reference. Replace the
447 // FrameIndex with base register with EBP. Add an offset to the offset.
448 MI.getOperand(i).ChangeToRegister(BasePtr, false);
450 // Now add the frame object offset to the offset from EBP. Offset is a
452 int Offset = getFrameIndexOffset(MF, FrameIndex) +
453 (int)(MI.getOperand(i+3).getImm());
455 MI.getOperand(i+3).ChangeToImmediate(Offset);
459 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
460 RegScavenger *RS) const {
461 MachineFrameInfo *FFI = MF.getFrameInfo();
463 // Calculate and set max stack object alignment early, so we can decide
464 // whether we will need stack realignment (and thus FP).
465 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
466 calculateMaxStackAlignment(FFI));
468 FFI->setMaxAlignment(MaxAlign);
472 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
473 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
474 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
475 if (TailCallReturnAddrDelta < 0) {
476 // create RETURNADDR area
486 CreateFixedObject(-TailCallReturnAddrDelta,
487 (-1*SlotSize)+TailCallReturnAddrDelta);
490 assert((TailCallReturnAddrDelta <= 0) &&
491 "The Delta should always be zero or negative");
492 // Create a frame entry for the EBP register that must be saved.
493 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
495 TailCallReturnAddrDelta);
496 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
497 "Slot for EBP register must be last in order to be found!");
501 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
502 /// stack pointer by a constant value.
504 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
505 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
506 const TargetInstrInfo &TII) {
507 bool isSub = NumBytes < 0;
508 uint64_t Offset = isSub ? -NumBytes : NumBytes;
511 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
512 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
514 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
515 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
516 uint64_t Chunk = (1LL << 31) - 1;
519 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
520 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
525 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
527 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
528 unsigned StackPtr, uint64_t *NumBytes = NULL) {
529 if (MBBI == MBB.begin()) return;
531 MachineBasicBlock::iterator PI = prior(MBBI);
532 unsigned Opc = PI->getOpcode();
533 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
534 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
535 PI->getOperand(0).getReg() == StackPtr) {
537 *NumBytes += PI->getOperand(2).getImm();
539 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
540 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
541 PI->getOperand(0).getReg() == StackPtr) {
543 *NumBytes -= PI->getOperand(2).getImm();
548 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
550 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
551 MachineBasicBlock::iterator &MBBI,
552 unsigned StackPtr, uint64_t *NumBytes = NULL) {
555 if (MBBI == MBB.end()) return;
557 MachineBasicBlock::iterator NI = next(MBBI);
558 if (NI == MBB.end()) return;
560 unsigned Opc = NI->getOpcode();
561 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
562 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
563 NI->getOperand(0).getReg() == StackPtr) {
565 *NumBytes -= NI->getOperand(2).getImm();
568 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
569 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
570 NI->getOperand(0).getReg() == StackPtr) {
572 *NumBytes += NI->getOperand(2).getImm();
578 /// mergeSPUpdates - Checks the instruction before/after the passed
579 /// instruction. If it is an ADD/SUB instruction it is deleted
580 /// argument and the stack adjustment is returned as a positive value for ADD
581 /// and a negative for SUB.
582 static int mergeSPUpdates(MachineBasicBlock &MBB,
583 MachineBasicBlock::iterator &MBBI,
585 bool doMergeWithPrevious) {
587 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
588 (!doMergeWithPrevious && MBBI == MBB.end()))
593 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
594 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
595 unsigned Opc = PI->getOpcode();
596 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
597 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
598 PI->getOperand(0).getReg() == StackPtr){
599 Offset += PI->getOperand(2).getImm();
601 if (!doMergeWithPrevious) MBBI = NI;
602 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
603 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
604 PI->getOperand(0).getReg() == StackPtr) {
605 Offset -= PI->getOperand(2).getImm();
607 if (!doMergeWithPrevious) MBBI = NI;
613 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
614 unsigned FrameLabelId,
615 unsigned ReadyLabelId) const {
616 MachineFrameInfo *MFI = MF.getFrameInfo();
617 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
621 uint64_t StackSize = MFI->getStackSize();
622 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
623 const TargetData *TD = MF.getTarget().getTargetData();
625 // Calculate amount of bytes used for return address storing
627 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
628 TargetFrameInfo::StackGrowsUp ?
629 TD->getPointerSize() : -TD->getPointerSize());
632 // Show update of SP.
635 MachineLocation SPDst(MachineLocation::VirtualFP);
636 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
637 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
639 MachineLocation SPDst(MachineLocation::VirtualFP);
640 MachineLocation SPSrc(MachineLocation::VirtualFP,
641 -StackSize+stackGrowth);
642 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
645 //FIXME: Verify & implement for FP
646 MachineLocation SPDst(StackPtr);
647 MachineLocation SPSrc(StackPtr, stackGrowth);
648 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
651 // Add callee saved registers to move list.
652 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
654 // FIXME: This is dirty hack. The code itself is pretty mess right now.
655 // It should be rewritten from scratch and generalized sometimes.
657 // Determine maximum offset (minumum due to stack growth)
658 int64_t MaxOffset = 0;
659 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
660 MaxOffset = std::min(MaxOffset,
661 MFI->getObjectOffset(CSI[I].getFrameIdx()));
664 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
665 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
666 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
667 unsigned Reg = CSI[I].getReg();
668 Offset = (MaxOffset-Offset+saveAreaOffset);
669 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
670 MachineLocation CSSrc(Reg);
671 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
676 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
677 MachineLocation FPSrc(FramePtr);
678 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
681 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
682 MachineLocation FPSrc(MachineLocation::VirtualFP);
683 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
687 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
688 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
689 MachineFrameInfo *MFI = MF.getFrameInfo();
690 const Function* Fn = MF.getFunction();
691 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
692 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
693 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
694 MachineBasicBlock::iterator MBBI = MBB.begin();
695 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
696 !Fn->doesNotThrow() ||
697 UnwindTablesMandatory;
698 // Prepare for frame info.
699 unsigned FrameLabelId = 0;
701 // Get the number of bytes to allocate from the FrameInfo.
702 uint64_t StackSize = MFI->getStackSize();
703 // Get desired stack alignment
704 uint64_t MaxAlign = MFI->getMaxAlignment();
706 // Add RETADDR move area to callee saved frame size.
707 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
708 if (TailCallReturnAddrDelta < 0)
709 X86FI->setCalleeSavedFrameSize(
710 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
712 // Insert stack pointer adjustment for later moving of return addr. Only
713 // applies to tail call optimized functions where the callee argument stack
714 // size is bigger than the callers.
715 if (TailCallReturnAddrDelta < 0) {
716 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
717 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
720 uint64_t NumBytes = 0;
722 // Calculate required stack adjustment
723 uint64_t FrameSize = StackSize - SlotSize;
724 if (needsStackRealignment(MF))
725 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
727 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
729 // Get the offset of the stack slot for the EBP register... which is
730 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
731 // Update the frame offset adjustment.
732 MFI->setOffsetAdjustment(-NumBytes);
734 // Save EBP into the appropriate stack slot...
735 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
736 .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
738 if (needsFrameMoves) {
739 // Mark effective beginning of when frame pointer becomes valid.
740 FrameLabelId = MMI->NextLabelID();
741 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
744 // Update EBP with the new base value...
745 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
749 if (needsStackRealignment(MF))
751 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
752 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
754 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
756 unsigned ReadyLabelId = 0;
757 if (needsFrameMoves) {
758 // Mark effective beginning of when frame pointer is ready.
759 ReadyLabelId = MMI->NextLabelID();
760 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
763 // Skip the callee-saved push instructions.
764 while (MBBI != MBB.end() &&
765 (MBBI->getOpcode() == X86::PUSH32r ||
766 MBBI->getOpcode() == X86::PUSH64r))
769 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
770 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
771 // Check, whether EAX is livein for this function
772 bool isEAXAlive = false;
773 for (MachineRegisterInfo::livein_iterator
774 II = MF.getRegInfo().livein_begin(),
775 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
776 unsigned Reg = II->first;
777 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
778 Reg == X86::AH || Reg == X86::AL);
781 // Function prologue calls _alloca to probe the stack when allocating
782 // more than 4k bytes in one go. Touching the stack at 4K increments is
783 // necessary to ensure that the guard pages used by the OS virtual memory
784 // manager are allocated in correct sequence.
786 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
787 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
788 .addExternalSymbol("_alloca");
791 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r))
792 .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true);
793 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
794 // allocated bytes for EAX.
795 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
796 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
797 .addExternalSymbol("_alloca");
799 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
800 StackPtr, false, NumBytes-4);
801 MBB.insert(MBBI, MI);
804 // If there is an SUB32ri of ESP immediately before this instruction,
805 // merge the two. This can be the case when tail call elimination is
806 // enabled and the callee has more arguments then the caller.
807 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
808 // If there is an ADD32ri or SUB32ri of ESP immediately after this
809 // instruction, merge the two instructions.
810 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
813 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
818 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
821 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
822 MachineBasicBlock &MBB) const {
823 const MachineFrameInfo *MFI = MF.getFrameInfo();
824 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
825 MachineBasicBlock::iterator MBBI = prior(MBB.end());
826 unsigned RetOpcode = MBBI->getOpcode();
831 case X86::TCRETURNdi:
832 case X86::TCRETURNri:
833 case X86::TCRETURNri64:
834 case X86::TCRETURNdi64:
836 case X86::EH_RETURN64:
839 case X86::TAILJMPm: break; // These are ok
841 assert(0 && "Can only insert epilog into returning blocks");
844 // Get the number of bytes to allocate from the FrameInfo
845 uint64_t StackSize = MFI->getStackSize();
846 uint64_t MaxAlign = MFI->getMaxAlignment();
847 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
848 uint64_t NumBytes = 0;
851 // Calculate required stack adjustment
852 uint64_t FrameSize = StackSize - SlotSize;
853 if (needsStackRealignment(MF))
854 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
856 NumBytes = FrameSize - CSSize;
859 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
861 NumBytes = StackSize - CSSize;
863 // Skip the callee-saved pop instructions.
864 MachineBasicBlock::iterator LastCSPop = MBBI;
865 while (MBBI != MBB.begin()) {
866 MachineBasicBlock::iterator PI = prior(MBBI);
867 unsigned Opc = PI->getOpcode();
868 if (Opc != X86::POP32r && Opc != X86::POP64r &&
869 !PI->getDesc().isTerminator())
874 // If there is an ADD32ri or SUB32ri of ESP immediately before this
875 // instruction, merge the two instructions.
876 if (NumBytes || MFI->hasVarSizedObjects())
877 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
879 // If dynamic alloca is used, then reset esp to point to the last callee-saved
880 // slot before popping them off! Same applies for the case, when stack was
882 if (needsStackRealignment(MF)) {
883 // We cannot use LEA here, because stack pointer was realigned. We need to
884 // deallocate local frame back
886 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
887 MBBI = prior(LastCSPop);
891 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
892 StackPtr).addReg(FramePtr);
893 } else if (MFI->hasVarSizedObjects()) {
895 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
896 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
897 FramePtr, false, -CSSize);
898 MBB.insert(MBBI, MI);
900 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
901 StackPtr).addReg(FramePtr);
904 // adjust stack pointer back: ESP += numbytes
906 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
909 // We're returning from function via eh_return.
910 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
911 MBBI = prior(MBB.end());
912 MachineOperand &DestAddr = MBBI->getOperand(0);
913 assert(DestAddr.isReg() && "Offset should be in register!");
915 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
916 StackPtr).addReg(DestAddr.getReg());
917 // Tail call return: adjust the stack pointer and jump to callee
918 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
919 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
920 MBBI = prior(MBB.end());
921 MachineOperand &JumpTarget = MBBI->getOperand(0);
922 MachineOperand &StackAdjust = MBBI->getOperand(1);
923 assert(StackAdjust.isImm() && "Expecting immediate value.");
925 // Adjust stack pointer.
926 int StackAdj = StackAdjust.getImm();
927 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
929 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
930 // Incoporate the retaddr area.
931 Offset = StackAdj-MaxTCDelta;
932 assert(Offset >= 0 && "Offset should never be negative");
934 // Check for possible merge with preceeding ADD instruction.
935 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
936 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
938 // Jump to label or value in register.
939 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
940 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
941 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
942 else if (RetOpcode== X86::TCRETURNri64) {
943 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
945 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
946 // Delete the pseudo instruction TCRETURN.
948 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
949 (X86FI->getTCReturnAddrDelta() < 0)) {
950 // Add the return addr area delta back since we are not tail calling.
951 int delta = -1*X86FI->getTCReturnAddrDelta();
952 MBBI = prior(MBB.end());
953 // Check for possible merge with preceeding ADD instruction.
954 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
955 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
959 unsigned X86RegisterInfo::getRARegister() const {
961 return X86::RIP; // Should have dwarf #16
963 return X86::EIP; // Should have dwarf #8
966 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
967 return hasFP(MF) ? FramePtr : StackPtr;
970 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
972 // Calculate amount of bytes used for return address storing
973 int stackGrowth = (Is64Bit ? -8 : -4);
975 // Initial state of the frame pointer is esp+4.
976 MachineLocation Dst(MachineLocation::VirtualFP);
977 MachineLocation Src(StackPtr, stackGrowth);
978 Moves.push_back(MachineMove(0, Dst, Src));
980 // Add return address to move list
981 MachineLocation CSDst(StackPtr, stackGrowth);
982 MachineLocation CSSrc(getRARegister());
983 Moves.push_back(MachineMove(0, CSDst, CSSrc));
986 unsigned X86RegisterInfo::getEHExceptionRegister() const {
987 assert(0 && "What is the exception register");
991 unsigned X86RegisterInfo::getEHHandlerRegister() const {
992 assert(0 && "What is the exception handler register");
997 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
998 switch (VT.getSimpleVT()) {
1004 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1006 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1008 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1010 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1016 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1018 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1020 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1022 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1024 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1026 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1028 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1030 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1032 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1034 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1036 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1038 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1040 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1042 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1044 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1046 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1052 default: return Reg;
1053 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1055 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1057 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1059 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1061 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1063 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1065 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1067 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1069 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1071 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1073 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1075 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1077 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1079 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1081 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1083 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1088 default: return Reg;
1089 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1091 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1093 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1095 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1097 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1099 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1101 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1103 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1105 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1107 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1109 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1111 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1113 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1115 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1117 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1119 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1124 default: return Reg;
1125 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1127 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1129 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1131 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1133 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1135 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1137 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1139 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1141 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1143 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1145 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1147 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1149 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1151 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1153 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1155 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1164 #include "X86GenRegisterInfo.inc"
1167 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1169 MSAC() : MachineFunctionPass(&ID) {}
1171 virtual bool runOnMachineFunction(MachineFunction &MF) {
1172 MachineFrameInfo *FFI = MF.getFrameInfo();
1173 MachineRegisterInfo &RI = MF.getRegInfo();
1175 // Calculate max stack alignment of all already allocated stack objects.
1176 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1178 // Be over-conservative: scan over all vreg defs and find, whether vector
1179 // registers are used. If yes - there is probability, that vector register
1180 // will be spilled and thus stack needs to be aligned properly.
1181 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1182 RegNum < RI.getLastVirtReg(); ++RegNum)
1183 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1185 FFI->setMaxAlignment(MaxAlign);
1190 virtual const char *getPassName() const {
1191 return "X86 Maximal Stack Alignment Calculator";
1199 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }