1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 // getDwarfRegNum - This function maps LLVM register identifiers to the
70 // Dwarf specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 // getX86RegNum - This function maps LLVM register identifiers to their X86
93 // specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass)
169 return &X86::GR64_ABCDRegClass;
170 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
171 A == &X86::GR32_NOREXRegClass)
172 return &X86::GR32_ABCDRegClass;
173 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
174 A == &X86::GR16_NOREXRegClass)
175 return &X86::GR16_ABCDRegClass;
176 } else if (B == &X86::GR8_NOREXRegClass) {
177 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
178 return &X86::GR64_NOREXRegClass;
179 else if (A == &X86::GR64_ABCDRegClass)
180 return &X86::GR64_ABCDRegClass;
181 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass)
182 return &X86::GR32_NOREXRegClass;
183 else if (A == &X86::GR32_ABCDRegClass)
184 return &X86::GR32_ABCDRegClass;
185 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
186 return &X86::GR16_NOREXRegClass;
187 else if (A == &X86::GR16_ABCDRegClass)
188 return &X86::GR16_ABCDRegClass;
193 if (B == &X86::GR8_ABCD_HRegClass) {
194 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
195 A == &X86::GR64_NOREXRegClass)
196 return &X86::GR64_ABCDRegClass;
197 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
198 A == &X86::GR32_NOREXRegClass)
199 return &X86::GR32_ABCDRegClass;
200 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
201 A == &X86::GR16_NOREXRegClass)
202 return &X86::GR16_ABCDRegClass;
207 if (B == &X86::GR16RegClass) {
208 if (A->getSize() == 4 || A->getSize() == 8)
210 } else if (B == &X86::GR16_ABCDRegClass) {
211 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
212 A == &X86::GR64_NOREXRegClass)
213 return &X86::GR64_ABCDRegClass;
214 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
215 A == &X86::GR32_NOREXRegClass)
216 return &X86::GR32_ABCDRegClass;
217 } else if (B == &X86::GR16_NOREXRegClass) {
218 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
219 return &X86::GR64_NOREXRegClass;
220 else if (A == &X86::GR64_ABCDRegClass)
221 return &X86::GR64_ABCDRegClass;
222 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass)
223 return &X86::GR32_NOREXRegClass;
224 else if (A == &X86::GR32_ABCDRegClass)
225 return &X86::GR64_ABCDRegClass;
230 if (B == &X86::GR32RegClass) {
231 if (A->getSize() == 8)
233 } else if (B == &X86::GR32_ABCDRegClass) {
234 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
235 A == &X86::GR64_NOREXRegClass)
236 return &X86::GR64_ABCDRegClass;
237 } else if (B == &X86::GR32_NOREXRegClass) {
238 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
239 return &X86::GR64_NOREXRegClass;
240 else if (A == &X86::GR64_ABCDRegClass)
241 return &X86::GR64_ABCDRegClass;
248 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
249 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
250 if (Subtarget->is64Bit())
251 return &X86::GR64RegClass;
253 return &X86::GR32RegClass;
256 const TargetRegisterClass *
257 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
258 if (RC == &X86::CCRRegClass) {
260 return &X86::GR64RegClass;
262 return &X86::GR32RegClass;
268 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
269 bool callsEHReturn = false;
272 const MachineFrameInfo *MFI = MF->getFrameInfo();
273 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
274 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
277 static const unsigned CalleeSavedRegs32Bit[] = {
278 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
281 static const unsigned CalleeSavedRegs32EHRet[] = {
282 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
285 static const unsigned CalleeSavedRegs64Bit[] = {
286 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
289 static const unsigned CalleeSavedRegs64EHRet[] = {
290 X86::RAX, X86::RDX, X86::RBX, X86::R12,
291 X86::R13, X86::R14, X86::R15, X86::RBP, 0
294 static const unsigned CalleeSavedRegsWin64[] = {
295 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
296 X86::R12, X86::R13, X86::R14, X86::R15,
297 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
298 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
299 X86::XMM14, X86::XMM15, 0
304 return CalleeSavedRegsWin64;
306 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
308 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
312 const TargetRegisterClass* const*
313 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
314 bool callsEHReturn = false;
317 const MachineFrameInfo *MFI = MF->getFrameInfo();
318 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
319 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
322 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
323 &X86::GR32RegClass, &X86::GR32RegClass,
324 &X86::GR32RegClass, &X86::GR32RegClass, 0
326 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
327 &X86::GR32RegClass, &X86::GR32RegClass,
328 &X86::GR32RegClass, &X86::GR32RegClass,
329 &X86::GR32RegClass, &X86::GR32RegClass, 0
331 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
332 &X86::GR64RegClass, &X86::GR64RegClass,
333 &X86::GR64RegClass, &X86::GR64RegClass,
334 &X86::GR64RegClass, &X86::GR64RegClass, 0
336 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
337 &X86::GR64RegClass, &X86::GR64RegClass,
338 &X86::GR64RegClass, &X86::GR64RegClass,
339 &X86::GR64RegClass, &X86::GR64RegClass,
340 &X86::GR64RegClass, &X86::GR64RegClass, 0
342 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
343 &X86::GR64RegClass, &X86::GR64RegClass,
344 &X86::GR64RegClass, &X86::GR64RegClass,
345 &X86::GR64RegClass, &X86::GR64RegClass,
346 &X86::GR64RegClass, &X86::GR64RegClass,
347 &X86::VR128RegClass, &X86::VR128RegClass,
348 &X86::VR128RegClass, &X86::VR128RegClass,
349 &X86::VR128RegClass, &X86::VR128RegClass,
350 &X86::VR128RegClass, &X86::VR128RegClass,
351 &X86::VR128RegClass, &X86::VR128RegClass, 0
356 return CalleeSavedRegClassesWin64;
358 return (callsEHReturn ?
359 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
361 return (callsEHReturn ?
362 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
366 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
367 BitVector Reserved(getNumRegs());
368 // Set the stack-pointer register and its aliases as reserved.
369 Reserved.set(X86::RSP);
370 Reserved.set(X86::ESP);
371 Reserved.set(X86::SP);
372 Reserved.set(X86::SPL);
373 // Set the frame-pointer register and its aliases as reserved if needed.
375 Reserved.set(X86::RBP);
376 Reserved.set(X86::EBP);
377 Reserved.set(X86::BP);
378 Reserved.set(X86::BPL);
380 // Mark the x87 stack registers as reserved, since they don't
381 // behave normally with respect to liveness. We don't fully
382 // model the effects of x87 stack pushes and pops after
384 Reserved.set(X86::ST0);
385 Reserved.set(X86::ST1);
386 Reserved.set(X86::ST2);
387 Reserved.set(X86::ST3);
388 Reserved.set(X86::ST4);
389 Reserved.set(X86::ST5);
390 Reserved.set(X86::ST6);
391 Reserved.set(X86::ST7);
395 //===----------------------------------------------------------------------===//
396 // Stack Frame Processing methods
397 //===----------------------------------------------------------------------===//
399 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
400 unsigned MaxAlign = 0;
401 for (int i = FFI->getObjectIndexBegin(),
402 e = FFI->getObjectIndexEnd(); i != e; ++i) {
403 if (FFI->isDeadObjectIndex(i))
405 unsigned Align = FFI->getObjectAlignment(i);
406 MaxAlign = std::max(MaxAlign, Align);
412 // hasFP - Return true if the specified function should have a dedicated frame
413 // pointer register. This is true if the function has variable sized allocas or
414 // if frame pointer elimination is disabled.
416 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
417 const MachineFrameInfo *MFI = MF.getFrameInfo();
418 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
420 return (NoFramePointerElim ||
421 needsStackRealignment(MF) ||
422 MFI->hasVarSizedObjects() ||
423 MFI->isFrameAddressTaken() ||
424 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
425 (MMI && MMI->callsUnwindInit()));
428 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
429 const MachineFrameInfo *MFI = MF.getFrameInfo();
431 // FIXME: Currently we don't support stack realignment for functions with
432 // variable-sized allocas
433 return (RealignStack &&
434 (MFI->getMaxAlignment() > StackAlign &&
435 !MFI->hasVarSizedObjects()));
438 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
439 return !MF.getFrameInfo()->hasVarSizedObjects();
442 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
443 int &FrameIdx) const {
444 if (Reg == FramePtr && hasFP(MF)) {
445 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
453 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
454 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
455 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
457 if (needsStackRealignment(MF)) {
459 // Skip the saved EBP
462 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
463 assert( (-(Offset + StackSize)) % Align == 0);
465 return Offset + StackSize;
468 // FIXME: Support tail calls
471 return Offset + StackSize;
473 // Skip the saved EBP
476 // Skip the RETADDR move area
477 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
478 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
479 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
485 void X86RegisterInfo::
486 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
487 MachineBasicBlock::iterator I) const {
488 if (!hasReservedCallFrame(MF)) {
489 // If the stack pointer can be changed after prologue, turn the
490 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
491 // adjcallstackdown instruction into 'add ESP, <amt>'
492 // TODO: consider using push / pop instead of sub + store / add
493 MachineInstr *Old = I;
494 uint64_t Amount = Old->getOperand(0).getImm();
496 // We need to keep the stack aligned properly. To do this, we round the
497 // amount of space needed for the outgoing arguments up to the next
498 // alignment boundary.
499 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
501 MachineInstr *New = 0;
502 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
503 New = BuildMI(MF, Old->getDebugLoc(),
504 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
505 StackPtr).addReg(StackPtr).addImm(Amount);
507 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
508 // factor out the amount the callee already popped.
509 uint64_t CalleeAmt = Old->getOperand(1).getImm();
512 unsigned Opc = (Amount < 128) ?
513 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
514 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
515 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
516 .addReg(StackPtr).addImm(Amount);
521 // The EFLAGS implicit def is dead.
522 New->getOperand(3).setIsDead();
524 // Replace the pseudo instruction with a new instruction...
528 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
529 // If we are performing frame pointer elimination and if the callee pops
530 // something off the stack pointer, add it back. We do this until we have
531 // more advanced stack pointer tracking ability.
532 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
533 unsigned Opc = (CalleeAmt < 128) ?
534 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
535 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
536 MachineInstr *Old = I;
538 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
539 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
540 // The EFLAGS implicit def is dead.
541 New->getOperand(3).setIsDead();
550 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
551 int SPAdj, RegScavenger *RS) const{
552 assert(SPAdj == 0 && "Unexpected");
555 MachineInstr &MI = *II;
556 MachineFunction &MF = *MI.getParent()->getParent();
557 while (!MI.getOperand(i).isFI()) {
559 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
562 int FrameIndex = MI.getOperand(i).getIndex();
565 if (needsStackRealignment(MF))
566 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
568 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
570 // This must be part of a four operand memory reference. Replace the
571 // FrameIndex with base register with EBP. Add an offset to the offset.
572 MI.getOperand(i).ChangeToRegister(BasePtr, false);
574 // Now add the frame object offset to the offset from EBP.
575 if (MI.getOperand(i+3).isImm()) {
576 // Offset is a 32-bit integer.
577 int Offset = getFrameIndexOffset(MF, FrameIndex) +
578 (int)(MI.getOperand(i+3).getImm());
580 MI.getOperand(i+3).ChangeToImmediate(Offset);
582 // Offset is symbolic. This is extremely rare.
583 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
584 (uint64_t)MI.getOperand(i+3).getOffset();
585 MI.getOperand(i+3).setOffset(Offset);
590 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
591 RegScavenger *RS) const {
592 MachineFrameInfo *FFI = MF.getFrameInfo();
594 // Calculate and set max stack object alignment early, so we can decide
595 // whether we will need stack realignment (and thus FP).
596 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
597 calculateMaxStackAlignment(FFI));
599 FFI->setMaxAlignment(MaxAlign);
601 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
602 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
603 if (TailCallReturnAddrDelta < 0) {
604 // create RETURNADDR area
614 CreateFixedObject(-TailCallReturnAddrDelta,
615 (-1*SlotSize)+TailCallReturnAddrDelta);
618 assert((TailCallReturnAddrDelta <= 0) &&
619 "The Delta should always be zero or negative");
620 // Create a frame entry for the EBP register that must be saved.
621 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
623 TailCallReturnAddrDelta);
624 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
625 "Slot for EBP register must be last in order to be found!");
630 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
631 /// stack pointer by a constant value.
633 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
634 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
635 const TargetInstrInfo &TII) {
636 bool isSub = NumBytes < 0;
637 uint64_t Offset = isSub ? -NumBytes : NumBytes;
640 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
641 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
643 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
644 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
645 uint64_t Chunk = (1LL << 31) - 1;
646 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
647 DebugLoc::getUnknownLoc());
650 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
652 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
653 .addReg(StackPtr).addImm(ThisVal);
654 // The EFLAGS implicit def is dead.
655 MI->getOperand(3).setIsDead();
660 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
662 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
663 unsigned StackPtr, uint64_t *NumBytes = NULL) {
664 if (MBBI == MBB.begin()) return;
666 MachineBasicBlock::iterator PI = prior(MBBI);
667 unsigned Opc = PI->getOpcode();
668 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
669 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
670 PI->getOperand(0).getReg() == StackPtr) {
672 *NumBytes += PI->getOperand(2).getImm();
674 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
675 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
676 PI->getOperand(0).getReg() == StackPtr) {
678 *NumBytes -= PI->getOperand(2).getImm();
683 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
685 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
686 MachineBasicBlock::iterator &MBBI,
687 unsigned StackPtr, uint64_t *NumBytes = NULL) {
690 if (MBBI == MBB.end()) return;
692 MachineBasicBlock::iterator NI = next(MBBI);
693 if (NI == MBB.end()) return;
695 unsigned Opc = NI->getOpcode();
696 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
697 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
698 NI->getOperand(0).getReg() == StackPtr) {
700 *NumBytes -= NI->getOperand(2).getImm();
703 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
704 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
705 NI->getOperand(0).getReg() == StackPtr) {
707 *NumBytes += NI->getOperand(2).getImm();
713 /// mergeSPUpdates - Checks the instruction before/after the passed
714 /// instruction. If it is an ADD/SUB instruction it is deleted
715 /// argument and the stack adjustment is returned as a positive value for ADD
716 /// and a negative for SUB.
717 static int mergeSPUpdates(MachineBasicBlock &MBB,
718 MachineBasicBlock::iterator &MBBI,
720 bool doMergeWithPrevious) {
722 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
723 (!doMergeWithPrevious && MBBI == MBB.end()))
728 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
729 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
730 unsigned Opc = PI->getOpcode();
731 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
732 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
733 PI->getOperand(0).getReg() == StackPtr){
734 Offset += PI->getOperand(2).getImm();
736 if (!doMergeWithPrevious) MBBI = NI;
737 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
738 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
739 PI->getOperand(0).getReg() == StackPtr) {
740 Offset -= PI->getOperand(2).getImm();
742 if (!doMergeWithPrevious) MBBI = NI;
748 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
750 unsigned FramePtr) const {
751 MachineFrameInfo *MFI = MF.getFrameInfo();
752 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
755 // Add callee saved registers to move list.
756 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
757 if (CSI.empty()) return;
759 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
760 const TargetData *TD = MF.getTarget().getTargetData();
761 bool HasFP = hasFP(MF);
763 // Calculate amount of bytes used for return address storing
765 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
766 TargetFrameInfo::StackGrowsUp ?
767 TD->getPointerSize() : -TD->getPointerSize());
769 // FIXME: This is dirty hack. The code itself is pretty mess right now.
770 // It should be rewritten from scratch and generalized sometimes.
772 // Determine maximum offset (minumum due to stack growth)
773 int64_t MaxOffset = 0;
774 for (std::vector<CalleeSavedInfo>::const_iterator
775 I = CSI.begin(), E = CSI.end(); I != E; ++I)
776 MaxOffset = std::min(MaxOffset,
777 MFI->getObjectOffset(I->getFrameIdx()));
779 // Calculate offsets.
780 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
781 for (std::vector<CalleeSavedInfo>::const_iterator
782 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
783 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
784 unsigned Reg = I->getReg();
785 Offset = MaxOffset - Offset + saveAreaOffset;
787 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
788 MachineLocation CSSrc(Reg);
789 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
793 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
794 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
795 MachineFrameInfo *MFI = MF.getFrameInfo();
796 const Function* Fn = MF.getFunction();
797 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
798 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
799 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
800 MachineBasicBlock::iterator MBBI = MBB.begin();
801 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
802 !Fn->doesNotThrow() ||
803 UnwindTablesMandatory;
804 bool HasFP = hasFP(MF);
807 // Get the number of bytes to allocate from the FrameInfo.
808 uint64_t StackSize = MFI->getStackSize();
810 // Get desired stack alignment
811 uint64_t MaxAlign = MFI->getMaxAlignment();
813 // Add RETADDR move area to callee saved frame size.
814 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
815 if (TailCallReturnAddrDelta < 0)
816 X86FI->setCalleeSavedFrameSize(
817 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
819 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
820 // function, and use up to 128 bytes of stack space, don't have a frame
821 // pointer, calls, or dynamic alloca then we do not need to adjust the
822 // stack pointer (we fit in the Red Zone).
823 bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
824 if (Is64Bit && !DisableRedZone &&
825 !needsStackRealignment(MF) &&
826 !MFI->hasVarSizedObjects() && // No dynamic alloca.
827 !MFI->hasCalls() && // No calls.
828 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
829 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
830 if (HasFP) MinSize += SlotSize;
831 StackSize = std::max(MinSize,
832 StackSize > 128 ? StackSize - 128 : 0);
833 MFI->setStackSize(StackSize);
836 // Insert stack pointer adjustment for later moving of return addr. Only
837 // applies to tail call optimized functions where the callee argument stack
838 // size is bigger than the callers.
839 if (TailCallReturnAddrDelta < 0) {
841 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
842 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
843 // The EFLAGS implicit def is dead.
844 MI->getOperand(3).setIsDead();
847 // uint64_t StackSize = MFI->getStackSize();
848 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
849 const TargetData *TD = MF.getTarget().getTargetData();
851 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
852 TargetFrameInfo::StackGrowsUp ?
853 TD->getPointerSize() : -TD->getPointerSize());
855 uint64_t NumBytes = 0;
857 // Calculate required stack adjustment
858 uint64_t FrameSize = StackSize - SlotSize;
859 if (needsStackRealignment(MF))
860 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
862 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
864 // Get the offset of the stack slot for the EBP register, which is
865 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
866 // Update the frame offset adjustment.
867 MFI->setOffsetAdjustment(-NumBytes);
869 // Save EBP/RBP into the appropriate stack slot...
870 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
871 .addReg(FramePtr, RegState::Kill);
873 if (needsFrameMoves) {
874 // Mark effective beginning of when frame pointer becomes valid.
875 unsigned FrameLabelId = MMI->NextLabelID();
876 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
878 // Define the current CFA rule to use the provided offset.
880 MachineLocation SPDst(MachineLocation::VirtualFP);
881 MachineLocation SPSrc(MachineLocation::VirtualFP,
882 HasFP ? 2 * stackGrowth :
883 -StackSize + stackGrowth);
884 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
886 // FIXME: Verify & implement for FP
887 MachineLocation SPDst(StackPtr);
888 MachineLocation SPSrc(StackPtr, stackGrowth);
889 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
892 // Change the rule for the FramePtr to be an "offset" rule.
893 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
894 MachineLocation FPSrc(FramePtr);
895 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
898 // Update EBP with the new base value...
899 BuildMI(MBB, MBBI, DL,
900 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
903 if (needsFrameMoves) {
904 unsigned FrameLabelId = MMI->NextLabelID();
905 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
907 // Define the current CFA to use the EBP/RBP register.
908 MachineLocation FPDst(FramePtr);
909 MachineLocation FPSrc(MachineLocation::VirtualFP);
910 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
913 // Mark the FramePtr as live-in in every block except the entry.
914 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
916 I->addLiveIn(FramePtr);
919 if (needsStackRealignment(MF)) {
921 BuildMI(MBB, MBBI, DL,
922 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
923 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
925 // The EFLAGS implicit def is dead.
926 MI->getOperand(3).setIsDead();
929 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
932 // Skip the callee-saved push instructions.
933 bool RegsSaved = false;
934 while (MBBI != MBB.end() &&
935 (MBBI->getOpcode() == X86::PUSH32r ||
936 MBBI->getOpcode() == X86::PUSH64r)) {
941 if (RegsSaved && needsFrameMoves) {
942 // Mark end of callee-saved push instructions.
943 unsigned LabelId = MMI->NextLabelID();
944 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
946 // Emit DWARF info specifying the offsets of the callee-saved registers.
947 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
950 if (MBBI != MBB.end())
951 DL = MBBI->getDebugLoc();
953 // Adjust stack pointer: ESP -= numbytes.
954 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
955 // Check, whether EAX is livein for this function.
956 bool isEAXAlive = false;
957 for (MachineRegisterInfo::livein_iterator
958 II = MF.getRegInfo().livein_begin(),
959 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
960 unsigned Reg = II->first;
961 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
962 Reg == X86::AH || Reg == X86::AL);
965 // Function prologue calls _alloca to probe the stack when allocating more
966 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
967 // to ensure that the guard pages used by the OS virtual memory manager are
968 // allocated in correct sequence.
970 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
972 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
973 .addExternalSymbol("_alloca");
976 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
977 .addReg(X86::EAX, RegState::Kill);
979 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
980 // allocated bytes for EAX.
981 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
982 .addImm(NumBytes - 4);
983 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
984 .addExternalSymbol("_alloca");
987 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
989 StackPtr, false, NumBytes - 4);
990 MBB.insert(MBBI, MI);
992 } else if (NumBytes) {
993 // If there is an SUB32ri of ESP immediately before this instruction, merge
994 // the two. This can be the case when tail call elimination is enabled and
995 // the callee has more arguments then the caller.
996 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
998 // If there is an ADD32ri or SUB32ri of ESP immediately after this
999 // instruction, merge the two instructions.
1000 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1003 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1006 if (!HasFP && needsFrameMoves && NumBytes) {
1007 // Mark end of stack pointer adjustment.
1008 unsigned LabelId = MMI->NextLabelID();
1009 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1011 // Define the current CFA rule to use the provided offset.
1013 MachineLocation SPDst(MachineLocation::VirtualFP);
1014 MachineLocation SPSrc(MachineLocation::VirtualFP,
1015 -StackSize + stackGrowth);
1016 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1018 // FIXME: Verify & implement for FP
1019 MachineLocation SPDst(StackPtr);
1020 MachineLocation SPSrc(StackPtr, stackGrowth);
1021 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1026 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1027 MachineBasicBlock &MBB) const {
1028 const MachineFrameInfo *MFI = MF.getFrameInfo();
1029 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1030 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1031 unsigned RetOpcode = MBBI->getOpcode();
1032 DebugLoc DL = MBBI->getDebugLoc();
1034 switch (RetOpcode) {
1037 case X86::TCRETURNdi:
1038 case X86::TCRETURNri:
1039 case X86::TCRETURNri64:
1040 case X86::TCRETURNdi64:
1041 case X86::EH_RETURN:
1042 case X86::EH_RETURN64:
1045 case X86::TAILJMPm: break; // These are ok
1047 llvm_unreachable("Can only insert epilog into returning blocks");
1050 // Get the number of bytes to allocate from the FrameInfo
1051 uint64_t StackSize = MFI->getStackSize();
1052 uint64_t MaxAlign = MFI->getMaxAlignment();
1053 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1054 uint64_t NumBytes = 0;
1057 // Calculate required stack adjustment
1058 uint64_t FrameSize = StackSize - SlotSize;
1059 if (needsStackRealignment(MF))
1060 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1062 NumBytes = FrameSize - CSSize;
1065 BuildMI(MBB, MBBI, DL,
1066 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1068 NumBytes = StackSize - CSSize;
1071 // Skip the callee-saved pop instructions.
1072 MachineBasicBlock::iterator LastCSPop = MBBI;
1073 while (MBBI != MBB.begin()) {
1074 MachineBasicBlock::iterator PI = prior(MBBI);
1075 unsigned Opc = PI->getOpcode();
1076 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1077 !PI->getDesc().isTerminator())
1082 DL = MBBI->getDebugLoc();
1084 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1085 // instruction, merge the two instructions.
1086 if (NumBytes || MFI->hasVarSizedObjects())
1087 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1089 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1090 // slot before popping them off! Same applies for the case, when stack was
1092 if (needsStackRealignment(MF)) {
1093 // We cannot use LEA here, because stack pointer was realigned. We need to
1094 // deallocate local frame back
1096 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1097 MBBI = prior(LastCSPop);
1100 BuildMI(MBB, MBBI, DL,
1101 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1102 StackPtr).addReg(FramePtr);
1103 } else if (MFI->hasVarSizedObjects()) {
1105 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1106 MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1107 FramePtr, false, -CSSize);
1108 MBB.insert(MBBI, MI);
1110 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1111 StackPtr).addReg(FramePtr);
1114 // adjust stack pointer back: ESP += numbytes
1116 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1119 // We're returning from function via eh_return.
1120 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1121 MBBI = prior(MBB.end());
1122 MachineOperand &DestAddr = MBBI->getOperand(0);
1123 assert(DestAddr.isReg() && "Offset should be in register!");
1124 BuildMI(MBB, MBBI, DL,
1125 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1126 StackPtr).addReg(DestAddr.getReg());
1127 // Tail call return: adjust the stack pointer and jump to callee
1128 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1129 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1130 MBBI = prior(MBB.end());
1131 MachineOperand &JumpTarget = MBBI->getOperand(0);
1132 MachineOperand &StackAdjust = MBBI->getOperand(1);
1133 assert(StackAdjust.isImm() && "Expecting immediate value.");
1135 // Adjust stack pointer.
1136 int StackAdj = StackAdjust.getImm();
1137 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1139 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1140 // Incoporate the retaddr area.
1141 Offset = StackAdj-MaxTCDelta;
1142 assert(Offset >= 0 && "Offset should never be negative");
1145 // Check for possible merge with preceeding ADD instruction.
1146 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1147 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1150 // Jump to label or value in register.
1151 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1152 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1153 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1154 else if (RetOpcode== X86::TCRETURNri64)
1155 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1157 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1159 // Delete the pseudo instruction TCRETURN.
1161 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1162 (X86FI->getTCReturnAddrDelta() < 0)) {
1163 // Add the return addr area delta back since we are not tail calling.
1164 int delta = -1*X86FI->getTCReturnAddrDelta();
1165 MBBI = prior(MBB.end());
1166 // Check for possible merge with preceeding ADD instruction.
1167 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1168 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1172 unsigned X86RegisterInfo::getRARegister() const {
1174 return X86::RIP; // Should have dwarf #16
1176 return X86::EIP; // Should have dwarf #8
1179 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1180 return hasFP(MF) ? FramePtr : StackPtr;
1183 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1185 // Calculate amount of bytes used for return address storing
1186 int stackGrowth = (Is64Bit ? -8 : -4);
1188 // Initial state of the frame pointer is esp+4.
1189 MachineLocation Dst(MachineLocation::VirtualFP);
1190 MachineLocation Src(StackPtr, stackGrowth);
1191 Moves.push_back(MachineMove(0, Dst, Src));
1193 // Add return address to move list
1194 MachineLocation CSDst(StackPtr, stackGrowth);
1195 MachineLocation CSSrc(getRARegister());
1196 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1199 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1200 llvm_unreachable("What is the exception register");
1204 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1205 llvm_unreachable("What is the exception handler register");
1210 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1211 switch (VT.getSimpleVT()) {
1212 default: return Reg;
1217 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1219 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1221 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1223 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1229 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1231 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1233 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1235 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1237 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1239 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1241 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1243 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1245 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1247 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1249 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1251 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1253 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1255 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1257 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1259 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1265 default: return Reg;
1266 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1268 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1270 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1272 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1274 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1276 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1278 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1280 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1282 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1284 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1286 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1288 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1290 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1292 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1294 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1296 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1301 default: return Reg;
1302 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1304 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1306 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1308 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1310 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1312 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1314 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1316 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1318 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1320 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1322 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1324 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1326 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1328 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1330 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1332 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1337 default: return Reg;
1338 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1340 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1342 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1344 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1346 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1348 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1350 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1352 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1354 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1356 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1358 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1360 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1362 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1364 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1366 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1368 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1377 #include "X86GenRegisterInfo.inc"
1380 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1382 MSAC() : MachineFunctionPass(&ID) {}
1384 virtual bool runOnMachineFunction(MachineFunction &MF) {
1385 MachineFrameInfo *FFI = MF.getFrameInfo();
1386 MachineRegisterInfo &RI = MF.getRegInfo();
1388 // Calculate max stack alignment of all already allocated stack objects.
1389 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1391 // Be over-conservative: scan over all vreg defs and find, whether vector
1392 // registers are used. If yes - there is probability, that vector register
1393 // will be spilled and thus stack needs to be aligned properly.
1394 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1395 RegNum < RI.getLastVirtReg(); ++RegNum)
1396 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1398 FFI->setMaxAlignment(MaxAlign);
1403 virtual const char *getPassName() const {
1404 return "X86 Maximal Stack Alignment Calculator";
1412 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }