1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/Function.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/ADT/STLExtras.h"
40 NoFusing("disable-spill-fusing",
41 cl::desc("Disable fusing of spill code into instructions"));
43 PrintFailedFusing("print-failed-fuse-candidates",
44 cl::desc("Print instructions that the allocator wants to"
45 " fuse, but the X86 backend currently can't"),
49 X86RegisterInfo::X86RegisterInfo()
50 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
52 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MI,
54 unsigned SrcReg, int FrameIdx,
55 const TargetRegisterClass *RC) const {
57 if (RC == &X86::GR32RegClass) {
59 } else if (RC == &X86::GR16RegClass) {
61 } else if (RC == &X86::GR8RegClass) {
63 } else if (RC == &X86::GR32_RegClass) {
65 } else if (RC == &X86::GR16_RegClass) {
67 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
69 } else if (RC == &X86::FR32RegClass) {
71 } else if (RC == &X86::FR64RegClass) {
73 } else if (RC == &X86::VR128RegClass) {
76 assert(0 && "Unknown regclass");
79 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
82 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MI,
84 unsigned DestReg, int FrameIdx,
85 const TargetRegisterClass *RC) const{
87 if (RC == &X86::GR32RegClass) {
89 } else if (RC == &X86::GR16RegClass) {
91 } else if (RC == &X86::GR8RegClass) {
93 } else if (RC == &X86::GR32_RegClass) {
95 } else if (RC == &X86::GR16_RegClass) {
97 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
99 } else if (RC == &X86::FR32RegClass) {
101 } else if (RC == &X86::FR64RegClass) {
103 } else if (RC == &X86::VR128RegClass) {
106 assert(0 && "Unknown regclass");
109 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
112 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MI,
114 unsigned DestReg, unsigned SrcReg,
115 const TargetRegisterClass *RC) const {
117 if (RC == &X86::GR32RegClass) {
119 } else if (RC == &X86::GR16RegClass) {
121 } else if (RC == &X86::GR8RegClass) {
123 } else if (RC == &X86::GR32_RegClass) {
125 } else if (RC == &X86::GR16_RegClass) {
127 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
129 } else if (RC == &X86::FR32RegClass) {
130 Opc = X86::FsMOVAPSrr;
131 } else if (RC == &X86::FR64RegClass) {
132 Opc = X86::FsMOVAPDrr;
133 } else if (RC == &X86::VR128RegClass) {
136 assert(0 && "Unknown regclass");
139 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
143 static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex,
145 return addFrameReference(BuildMI(Opcode, 4), FrameIndex);
148 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
150 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
151 .addReg(MI->getOperand(1).getReg());
154 static MachineInstr *MakeMRIInst(unsigned Opcode, unsigned FrameIndex,
156 return addFrameReference(BuildMI(Opcode, 6), FrameIndex)
157 .addReg(MI->getOperand(1).getReg())
158 .addImm(MI->getOperand(2).getImmedValue());
161 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
163 if (MI->getOperand(1).isImmediate())
164 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
165 .addImm(MI->getOperand(1).getImmedValue());
166 else if (MI->getOperand(1).isGlobalAddress())
167 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
168 .addGlobalAddress(MI->getOperand(1).getGlobal(),
169 MI->getOperand(1).getOffset());
170 else if (MI->getOperand(1).isJumpTableIndex())
171 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
172 .addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());
173 assert(0 && "Unknown operand for MakeMI!");
177 static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
179 return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
182 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
184 const MachineOperand& op = MI->getOperand(0);
185 return addFrameReference(BuildMI(Opcode, 5, op.getReg(), op.getUseType()),
189 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
191 const MachineOperand& op = MI->getOperand(0);
192 return addFrameReference(BuildMI(Opcode, 6, op.getReg(), op.getUseType()),
193 FrameIndex).addImm(MI->getOperand(2).getImmedValue());
197 //===----------------------------------------------------------------------===//
198 // Efficient Lookup Table Support
199 //===----------------------------------------------------------------------===//
202 /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
205 unsigned from; // Original opcode.
206 unsigned to; // New opcode.
207 unsigned make; // Form of make required to produce the
210 // less operators used by STL search.
211 bool operator<(const TableEntry &TE) const { return from < TE.from; }
212 friend bool operator<(const TableEntry &TE, unsigned V) {
215 friend bool operator<(unsigned V, const TableEntry &TE) {
221 /// TableIsSorted - Return true if the table is in 'from' opcode order.
223 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
224 for (unsigned i = 1; i != NumEntries; ++i)
225 if (!(Table[i-1] < Table[i])) {
226 std::cerr << "Entries out of order" << Table[i-1].from
227 << " " << Table[i].from << "\n";
233 /// TableLookup - Return the table entry matching the specified opcode.
234 /// Otherwise return NULL.
235 static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
237 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
238 if (I != Table+N && I->from == Opcode)
243 #define ARRAY_SIZE(TABLE) \
244 (sizeof(TABLE)/sizeof(TABLE[0]))
247 #define ASSERT_SORTED(TABLE)
249 #define ASSERT_SORTED(TABLE) \
250 { static bool TABLE##Checked = false; \
251 if (!TABLE##Checked) { \
252 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
253 "All lookup tables must be sorted for efficient access!"); \
254 TABLE##Checked = true; \
260 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
262 int FrameIndex) const {
264 if (NoFusing) return NULL;
266 // Selection of instruction makes
277 // Table (and size) to search
278 const TableEntry *OpcodeTablePtr = NULL;
279 unsigned OpcodeTableSize = 0;
281 if (i == 0) { // If operand 0
282 static const TableEntry OpcodeTable[] = {
283 { X86::ADC32ri, X86::ADC32mi, makeMIInst },
284 { X86::ADC32ri8, X86::ADC32mi8, makeMIInst },
285 { X86::ADC32rr, X86::ADC32mr, makeMRInst },
286 { X86::ADD16ri, X86::ADD16mi, makeMIInst },
287 { X86::ADD16ri8, X86::ADD16mi8, makeMIInst },
288 { X86::ADD16rr, X86::ADD16mr, makeMRInst },
289 { X86::ADD32ri, X86::ADD32mi, makeMIInst },
290 { X86::ADD32ri8, X86::ADD32mi8, makeMIInst },
291 { X86::ADD32rr, X86::ADD32mr, makeMRInst },
292 { X86::ADD8ri, X86::ADD8mi, makeMIInst },
293 { X86::ADD8rr, X86::ADD8mr, makeMRInst },
294 { X86::AND16ri, X86::AND16mi, makeMIInst },
295 { X86::AND16ri8, X86::AND16mi8, makeMIInst },
296 { X86::AND16rr, X86::AND16mr, makeMRInst },
297 { X86::AND32ri, X86::AND32mi, makeMIInst },
298 { X86::AND32ri8, X86::AND32mi8, makeMIInst },
299 { X86::AND32rr, X86::AND32mr, makeMRInst },
300 { X86::AND8ri, X86::AND8mi, makeMIInst },
301 { X86::AND8rr, X86::AND8mr, makeMRInst },
302 { X86::DEC16r, X86::DEC16m, makeMInst },
303 { X86::DEC32r, X86::DEC32m, makeMInst },
304 { X86::DEC8r, X86::DEC8m, makeMInst },
305 { X86::DIV16r, X86::DIV16m, makeMInst },
306 { X86::DIV32r, X86::DIV32m, makeMInst },
307 { X86::DIV8r, X86::DIV8m, makeMInst },
308 { X86::FsMOVAPDrr, X86::MOVSDmr, makeMRInst },
309 { X86::FsMOVAPSrr, X86::MOVSSmr, makeMRInst },
310 { X86::IDIV16r, X86::IDIV16m, makeMInst },
311 { X86::IDIV32r, X86::IDIV32m, makeMInst },
312 { X86::IDIV8r, X86::IDIV8m, makeMInst },
313 { X86::IMUL16r, X86::IMUL16m, makeMInst },
314 { X86::IMUL32r, X86::IMUL32m, makeMInst },
315 { X86::IMUL8r, X86::IMUL8m, makeMInst },
316 { X86::INC16r, X86::INC16m, makeMInst },
317 { X86::INC32r, X86::INC32m, makeMInst },
318 { X86::INC8r, X86::INC8m, makeMInst },
319 { X86::MOV16r0, X86::MOV16mi, makeM0Inst },
320 { X86::MOV16ri, X86::MOV16mi, makeMIInst },
321 { X86::MOV16rr, X86::MOV16mr, makeMRInst },
322 { X86::MOV32r0, X86::MOV32mi, makeM0Inst },
323 { X86::MOV32ri, X86::MOV32mi, makeMIInst },
324 { X86::MOV32rr, X86::MOV32mr, makeMRInst },
325 { X86::MOV8r0, X86::MOV8mi, makeM0Inst },
326 { X86::MOV8ri, X86::MOV8mi, makeMIInst },
327 { X86::MOV8rr, X86::MOV8mr, makeMRInst },
328 { X86::MOVAPDrr, X86::MOVAPDmr, makeMRInst },
329 { X86::MOVAPSrr, X86::MOVAPSmr, makeMRInst },
330 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, makeMRInst },
331 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, makeMRInst },
332 { X86::MOVSDrr, X86::MOVSDmr, makeMRInst },
333 { X86::MOVSSrr, X86::MOVSSmr, makeMRInst },
334 { X86::MOVUPDrr, X86::MOVUPDmr, makeMRInst },
335 { X86::MOVUPSrr, X86::MOVUPSmr, makeMRInst },
336 { X86::MUL16r, X86::MUL16m, makeMInst },
337 { X86::MUL32r, X86::MUL32m, makeMInst },
338 { X86::MUL8r, X86::MUL8m, makeMInst },
339 { X86::NEG16r, X86::NEG16m, makeMInst },
340 { X86::NEG32r, X86::NEG32m, makeMInst },
341 { X86::NEG8r, X86::NEG8m, makeMInst },
342 { X86::NOT16r, X86::NOT16m, makeMInst },
343 { X86::NOT32r, X86::NOT32m, makeMInst },
344 { X86::NOT8r, X86::NOT8m, makeMInst },
345 { X86::OR16ri, X86::OR16mi, makeMIInst },
346 { X86::OR16ri8, X86::OR16mi8, makeMIInst },
347 { X86::OR16rr, X86::OR16mr, makeMRInst },
348 { X86::OR32ri, X86::OR32mi, makeMIInst },
349 { X86::OR32ri8, X86::OR32mi8, makeMIInst },
350 { X86::OR32rr, X86::OR32mr, makeMRInst },
351 { X86::OR8ri, X86::OR8mi, makeMIInst },
352 { X86::OR8rr, X86::OR8mr, makeMRInst },
353 { X86::ROL16r1, X86::ROL16m1, makeMInst },
354 { X86::ROL16rCL, X86::ROL16mCL, makeMInst },
355 { X86::ROL16ri, X86::ROL16mi, makeMIInst },
356 { X86::ROL32r1, X86::ROL32m1, makeMInst },
357 { X86::ROL32rCL, X86::ROL32mCL, makeMInst },
358 { X86::ROL32ri, X86::ROL32mi, makeMIInst },
359 { X86::ROL8r1, X86::ROL8m1, makeMInst },
360 { X86::ROL8rCL, X86::ROL8mCL, makeMInst },
361 { X86::ROL8ri, X86::ROL8mi, makeMIInst },
362 { X86::ROR16r1, X86::ROR16m1, makeMInst },
363 { X86::ROR16rCL, X86::ROR16mCL, makeMInst },
364 { X86::ROR16ri, X86::ROR16mi, makeMIInst },
365 { X86::ROR32r1, X86::ROR32m1, makeMInst },
366 { X86::ROR32rCL, X86::ROR32mCL, makeMInst },
367 { X86::ROR32ri, X86::ROR32mi, makeMIInst },
368 { X86::ROR8r1, X86::ROR8m1, makeMInst },
369 { X86::ROR8rCL, X86::ROR8mCL, makeMInst },
370 { X86::ROR8ri, X86::ROR8mi, makeMIInst },
371 { X86::SAR16r1, X86::SAR16m1, makeMInst },
372 { X86::SAR16rCL, X86::SAR16mCL, makeMInst },
373 { X86::SAR16ri, X86::SAR16mi, makeMIInst },
374 { X86::SAR32r1, X86::SAR32m1, makeMInst },
375 { X86::SAR32rCL, X86::SAR32mCL, makeMInst },
376 { X86::SAR32ri, X86::SAR32mi, makeMIInst },
377 { X86::SAR8r1, X86::SAR8m1, makeMInst },
378 { X86::SAR8rCL, X86::SAR8mCL, makeMInst },
379 { X86::SAR8ri, X86::SAR8mi, makeMIInst },
380 { X86::SBB32ri, X86::SBB32mi, makeMIInst },
381 { X86::SBB32ri8, X86::SBB32mi8, makeMIInst },
382 { X86::SBB32rr, X86::SBB32mr, makeMRInst },
383 { X86::SETAEr, X86::SETAEm, makeMInst },
384 { X86::SETAr, X86::SETAm, makeMInst },
385 { X86::SETBEr, X86::SETBEm, makeMInst },
386 { X86::SETBr, X86::SETBm, makeMInst },
387 { X86::SETEr, X86::SETEm, makeMInst },
388 { X86::SETGEr, X86::SETGEm, makeMInst },
389 { X86::SETGr, X86::SETGm, makeMInst },
390 { X86::SETLEr, X86::SETLEm, makeMInst },
391 { X86::SETLr, X86::SETLm, makeMInst },
392 { X86::SETNEr, X86::SETNEm, makeMInst },
393 { X86::SETNPr, X86::SETNPm, makeMInst },
394 { X86::SETNSr, X86::SETNSm, makeMInst },
395 { X86::SETPr, X86::SETPm, makeMInst },
396 { X86::SETSr, X86::SETSm, makeMInst },
397 { X86::SHL16r1, X86::SHL16m1, makeMInst },
398 { X86::SHL16rCL, X86::SHL16mCL, makeMInst },
399 { X86::SHL16ri, X86::SHL16mi, makeMIInst },
400 { X86::SHL32r1, X86::SHL32m1, makeMInst },
401 { X86::SHL32rCL, X86::SHL32mCL, makeMInst },
402 { X86::SHL32ri, X86::SHL32mi, makeMIInst },
403 { X86::SHL8r1, X86::SHL8m1, makeMInst },
404 { X86::SHL8rCL, X86::SHL8mCL, makeMInst },
405 { X86::SHL8ri, X86::SHL8mi, makeMIInst },
406 { X86::SHLD16rrCL, X86::SHLD16mrCL, makeMRInst },
407 { X86::SHLD16rri8, X86::SHLD16mri8, makeMRIInst },
408 { X86::SHLD32rrCL, X86::SHLD32mrCL, makeMRInst },
409 { X86::SHLD32rri8, X86::SHLD32mri8, makeMRIInst },
410 { X86::SHR16r1, X86::SHR16m1, makeMInst },
411 { X86::SHR16rCL, X86::SHR16mCL, makeMInst },
412 { X86::SHR16ri, X86::SHR16mi, makeMIInst },
413 { X86::SHR32r1, X86::SHR32m1, makeMInst },
414 { X86::SHR32rCL, X86::SHR32mCL, makeMInst },
415 { X86::SHR32ri, X86::SHR32mi, makeMIInst },
416 { X86::SHR8r1, X86::SHR8m1, makeMInst },
417 { X86::SHR8rCL, X86::SHR8mCL, makeMInst },
418 { X86::SHR8ri, X86::SHR8mi, makeMIInst },
419 { X86::SHRD16rrCL, X86::SHRD16mrCL, makeMRInst },
420 { X86::SHRD16rri8, X86::SHRD16mri8, makeMRIInst },
421 { X86::SHRD32rrCL, X86::SHRD32mrCL, makeMRInst },
422 { X86::SHRD32rri8, X86::SHRD32mri8, makeMRIInst },
423 { X86::SUB16ri, X86::SUB16mi, makeMIInst },
424 { X86::SUB16ri8, X86::SUB16mi8, makeMIInst },
425 { X86::SUB16rr, X86::SUB16mr, makeMRInst },
426 { X86::SUB32ri, X86::SUB32mi, makeMIInst },
427 { X86::SUB32ri8, X86::SUB32mi8, makeMIInst },
428 { X86::SUB32rr, X86::SUB32mr, makeMRInst },
429 { X86::SUB8ri, X86::SUB8mi, makeMIInst },
430 { X86::SUB8rr, X86::SUB8mr, makeMRInst },
431 { X86::XCHG16rr, X86::XCHG16mr, makeMRInst },
432 { X86::XCHG32rr, X86::XCHG32mr, makeMRInst },
433 { X86::XCHG8rr, X86::XCHG8mr, makeMRInst },
434 { X86::XOR16ri, X86::XOR16mi, makeMIInst },
435 { X86::XOR16ri8, X86::XOR16mi8, makeMIInst },
436 { X86::XOR16rr, X86::XOR16mr, makeMRInst },
437 { X86::XOR32ri, X86::XOR32mi, makeMIInst },
438 { X86::XOR32ri8, X86::XOR32mi8, makeMIInst },
439 { X86::XOR32rr, X86::XOR32mr, makeMRInst },
440 { X86::XOR8ri, X86::XOR8mi, makeMIInst },
441 { X86::XOR8rr, X86::XOR8mr, makeMRInst }
443 ASSERT_SORTED(OpcodeTable);
444 OpcodeTablePtr = OpcodeTable;
445 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
447 static const TableEntry OpcodeTable[] = {
448 { X86::ADC32rr, X86::ADC32rm, makeRMInst },
449 { X86::ADD16rr, X86::ADD16rm, makeRMInst },
450 { X86::ADD32rr, X86::ADD32rm, makeRMInst },
451 { X86::ADD8rr, X86::ADD8rm, makeRMInst },
452 { X86::ADDPDrr, X86::ADDPDrm, makeRMInst },
453 { X86::ADDPSrr, X86::ADDPSrm, makeRMInst },
454 { X86::ADDSDrr, X86::ADDSDrm, makeRMInst },
455 { X86::ADDSSrr, X86::ADDSSrm, makeRMInst },
456 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, makeRMInst },
457 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, makeRMInst },
458 { X86::AND16rr, X86::AND16rm, makeRMInst },
459 { X86::AND32rr, X86::AND32rm, makeRMInst },
460 { X86::AND8rr, X86::AND8rm, makeRMInst },
461 { X86::ANDNPDrr, X86::ANDNPDrm, makeRMInst },
462 { X86::ANDNPSrr, X86::ANDNPSrm, makeRMInst },
463 { X86::ANDPDrr, X86::ANDPDrm, makeRMInst },
464 { X86::ANDPSrr, X86::ANDPSrm, makeRMInst },
465 { X86::CMOVA16rr, X86::CMOVA16rm, makeRMInst },
466 { X86::CMOVA32rr, X86::CMOVA32rm, makeRMInst },
467 { X86::CMOVAE16rr, X86::CMOVAE16rm, makeRMInst },
468 { X86::CMOVAE32rr, X86::CMOVAE32rm, makeRMInst },
469 { X86::CMOVB16rr, X86::CMOVB16rm, makeRMInst },
470 { X86::CMOVB32rr, X86::CMOVB32rm, makeRMInst },
471 { X86::CMOVBE16rr, X86::CMOVBE16rm, makeRMInst },
472 { X86::CMOVBE32rr, X86::CMOVBE32rm, makeRMInst },
473 { X86::CMOVE16rr, X86::CMOVE16rm, makeRMInst },
474 { X86::CMOVE32rr, X86::CMOVE32rm, makeRMInst },
475 { X86::CMOVG16rr, X86::CMOVG16rm, makeRMInst },
476 { X86::CMOVG32rr, X86::CMOVG32rm, makeRMInst },
477 { X86::CMOVGE16rr, X86::CMOVGE16rm, makeRMInst },
478 { X86::CMOVGE32rr, X86::CMOVGE32rm, makeRMInst },
479 { X86::CMOVL16rr, X86::CMOVL16rm, makeRMInst },
480 { X86::CMOVL32rr, X86::CMOVL32rm, makeRMInst },
481 { X86::CMOVLE16rr, X86::CMOVLE16rm, makeRMInst },
482 { X86::CMOVLE32rr, X86::CMOVLE32rm, makeRMInst },
483 { X86::CMOVNE16rr, X86::CMOVNE16rm, makeRMInst },
484 { X86::CMOVNE32rr, X86::CMOVNE32rm, makeRMInst },
485 { X86::CMOVNP16rr, X86::CMOVNP16rm, makeRMInst },
486 { X86::CMOVNP32rr, X86::CMOVNP32rm, makeRMInst },
487 { X86::CMOVNS16rr, X86::CMOVNS16rm, makeRMInst },
488 { X86::CMOVNS32rr, X86::CMOVNS32rm, makeRMInst },
489 { X86::CMOVP16rr, X86::CMOVP16rm, makeRMInst },
490 { X86::CMOVP32rr, X86::CMOVP32rm, makeRMInst },
491 { X86::CMOVS16rr, X86::CMOVS16rm, makeRMInst },
492 { X86::CMOVS32rr, X86::CMOVS32rm, makeRMInst },
493 { X86::CMP16ri, X86::CMP16mi, makeMIInst },
494 { X86::CMP16ri8, X86::CMP16mi8, makeMIInst },
495 { X86::CMP16rr, X86::CMP16rm, makeRMInst },
496 { X86::CMP32ri, X86::CMP32mi, makeMIInst },
497 { X86::CMP32ri8, X86::CMP32mi8, makeRMInst },
498 { X86::CMP32rr, X86::CMP32rm, makeRMInst },
499 { X86::CMP8ri, X86::CMP8mi, makeRMInst },
500 { X86::CMP8rr, X86::CMP8rm, makeRMInst },
501 { X86::CMPPDrri, X86::CMPPDrmi, makeRMIInst },
502 { X86::CMPPSrri, X86::CMPPSrmi, makeRMIInst },
503 { X86::CMPSDrr, X86::CMPSDrm, makeRMInst },
504 { X86::CMPSSrr, X86::CMPSSrm, makeRMInst },
505 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, makeRMInst },
506 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, makeRMInst },
507 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, makeRMInst },
508 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, makeRMInst },
509 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, makeRMInst },
510 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, makeRMInst },
511 { X86::DIVPDrr, X86::DIVPDrm, makeRMInst },
512 { X86::DIVPSrr, X86::DIVPSrm, makeRMInst },
513 { X86::DIVSDrr, X86::DIVSDrm, makeRMInst },
514 { X86::DIVSSrr, X86::DIVSSrm, makeRMInst },
515 { X86::FsMOVAPDrr, X86::MOVSDrm, makeRMInst },
516 { X86::FsMOVAPSrr, X86::MOVSSrm, makeRMInst },
517 { X86::HADDPDrr, X86::HADDPDrm, makeRMInst },
518 { X86::HADDPSrr, X86::HADDPSrm, makeRMInst },
519 { X86::HSUBPDrr, X86::HSUBPDrm, makeRMInst },
520 { X86::HSUBPSrr, X86::HSUBPSrm, makeRMInst },
521 { X86::IMUL16rr, X86::IMUL16rm, makeRMInst },
522 { X86::IMUL16rri, X86::IMUL16rmi, makeRMIInst },
523 { X86::IMUL16rri8, X86::IMUL16rmi8, makeRMIInst },
524 { X86::IMUL32rr, X86::IMUL32rm, makeRMInst },
525 { X86::IMUL32rri, X86::IMUL32rmi, makeRMIInst },
526 { X86::IMUL32rri8, X86::IMUL32rmi8, makeRMIInst },
527 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, makeRMInst },
528 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, makeRMInst },
529 { X86::Int_COMISDrr, X86::Int_COMISDrm, makeRMInst },
530 { X86::Int_COMISSrr, X86::Int_COMISSrm, makeRMInst },
531 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, makeRMInst },
532 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, makeRMInst },
533 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, makeRMInst },
534 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, makeRMInst },
535 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, makeRMInst },
536 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, makeRMInst },
537 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, makeRMInst },
538 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, makeRMInst },
539 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, makeRMInst },
540 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, makeRMInst },
541 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, makeRMInst },
542 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, makeRMInst },
543 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, makeRMInst },
544 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, makeRMInst },
545 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, makeRMInst },
546 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, makeRMInst },
547 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, makeRMInst },
548 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, makeRMInst },
549 { X86::MAXPDrr, X86::MAXPDrm, makeRMInst },
550 { X86::MAXPSrr, X86::MAXPSrm, makeRMInst },
551 { X86::MINPDrr, X86::MINPDrm, makeRMInst },
552 { X86::MINPSrr, X86::MINPSrm, makeRMInst },
553 { X86::MOV16rr, X86::MOV16rm, makeRMInst },
554 { X86::MOV32rr, X86::MOV32rm, makeRMInst },
555 { X86::MOV8rr, X86::MOV8rm, makeRMInst },
556 { X86::MOVAPDrr, X86::MOVAPDrm, makeRMInst },
557 { X86::MOVAPSrr, X86::MOVAPSrm, makeRMInst },
558 { X86::MOVDDUPrr, X86::MOVDDUPrm, makeRMInst },
559 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, makeRMInst },
560 { X86::MOVQI2PQIrr, X86::MOVQI2PQIrm, makeRMInst },
561 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, makeRMInst },
562 { X86::MOVSDrr, X86::MOVSDrm, makeRMInst },
563 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, makeRMInst },
564 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, makeRMInst },
565 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, makeRMInst },
566 { X86::MOVSSrr, X86::MOVSSrm, makeRMInst },
567 { X86::MOVSX16rr8, X86::MOVSX16rm8, makeRMInst },
568 { X86::MOVSX32rr16, X86::MOVSX32rm16, makeRMInst },
569 { X86::MOVSX32rr8, X86::MOVSX32rm8, makeRMInst },
570 { X86::MOVUPDrr, X86::MOVUPDrm, makeRMInst },
571 { X86::MOVUPSrr, X86::MOVUPSrm, makeRMInst },
572 { X86::MOVZX16rr8, X86::MOVZX16rm8, makeRMInst },
573 { X86::MOVZX32rr16, X86::MOVZX32rm16, makeRMInst },
574 { X86::MOVZX32rr8, X86::MOVZX32rm8, makeRMInst },
575 { X86::MULPDrr, X86::MULPDrm, makeRMInst },
576 { X86::MULPSrr, X86::MULPSrm, makeRMInst },
577 { X86::MULSDrr, X86::MULSDrm, makeRMInst },
578 { X86::MULSSrr, X86::MULSSrm, makeRMInst },
579 { X86::OR16rr, X86::OR16rm, makeRMInst },
580 { X86::OR32rr, X86::OR32rm, makeRMInst },
581 { X86::OR8rr, X86::OR8rm, makeRMInst },
582 { X86::ORPDrr, X86::ORPDrm, makeRMInst },
583 { X86::ORPSrr, X86::ORPSrm, makeRMInst },
584 { X86::PACKSSDWrr, X86::PACKSSDWrm, makeRMInst },
585 { X86::PACKSSWBrr, X86::PACKSSWBrm, makeRMInst },
586 { X86::PACKUSWBrr, X86::PACKUSWBrm, makeRMInst },
587 { X86::PADDBrr, X86::PADDBrm, makeRMInst },
588 { X86::PADDDrr, X86::PADDDrm, makeRMInst },
589 { X86::PADDSBrr, X86::PADDSBrm, makeRMInst },
590 { X86::PADDSWrr, X86::PADDSWrm, makeRMInst },
591 { X86::PADDWrr, X86::PADDWrm, makeRMInst },
592 { X86::PANDNrr, X86::PANDNrm, makeRMInst },
593 { X86::PANDrr, X86::PANDrm, makeRMInst },
594 { X86::PAVGBrr, X86::PAVGBrm, makeRMInst },
595 { X86::PAVGWrr, X86::PAVGWrm, makeRMInst },
596 { X86::PCMPEQBrr, X86::PCMPEQBrm, makeRMInst },
597 { X86::PCMPEQDrr, X86::PCMPEQDrm, makeRMInst },
598 { X86::PCMPEQWrr, X86::PCMPEQWrm, makeRMInst },
599 { X86::PCMPGTBrr, X86::PCMPGTBrm, makeRMInst },
600 { X86::PCMPGTDrr, X86::PCMPGTDrm, makeRMInst },
601 { X86::PCMPGTWrr, X86::PCMPGTWrm, makeRMInst },
602 { X86::PINSRWrri, X86::PINSRWrmi, makeRMIInst },
603 { X86::PMADDWDrr, X86::PMADDWDrm, makeRMInst },
604 { X86::PMAXSWrr, X86::PMAXSWrm, makeRMInst },
605 { X86::PMAXUBrr, X86::PMAXUBrm, makeRMInst },
606 { X86::PMINSWrr, X86::PMINSWrm, makeRMInst },
607 { X86::PMINUBrr, X86::PMINUBrm, makeRMInst },
608 { X86::PMULHUWrr, X86::PMULHUWrm, makeRMInst },
609 { X86::PMULHWrr, X86::PMULHWrm, makeRMInst },
610 { X86::PMULLWrr, X86::PMULLWrm, makeRMInst },
611 { X86::PMULUDQrr, X86::PMULUDQrm, makeRMInst },
612 { X86::PORrr, X86::PORrm, makeRMInst },
613 { X86::PSADBWrr, X86::PSADBWrm, makeRMInst },
614 { X86::PSHUFDri, X86::PSHUFDmi, makeRMIInst },
615 { X86::PSHUFHWri, X86::PSHUFHWmi, makeRMIInst },
616 { X86::PSHUFLWri, X86::PSHUFLWmi, makeRMIInst },
617 { X86::PSLLDrr, X86::PSLLDrm, makeRMInst },
618 { X86::PSLLQrr, X86::PSLLQrm, makeRMInst },
619 { X86::PSLLWrr, X86::PSLLWrm, makeRMInst },
620 { X86::PSRADrr, X86::PSRADrm, makeRMInst },
621 { X86::PSRAWrr, X86::PSRAWrm, makeRMInst },
622 { X86::PSRLDrr, X86::PSRLDrm, makeRMInst },
623 { X86::PSRLQrr, X86::PSRLQrm, makeRMInst },
624 { X86::PSRLWrr, X86::PSRLWrm, makeRMInst },
625 { X86::PSUBBrr, X86::PSUBBrm, makeRMInst },
626 { X86::PSUBDrr, X86::PSUBDrm, makeRMInst },
627 { X86::PSUBSBrr, X86::PSUBSBrm, makeRMInst },
628 { X86::PSUBSWrr, X86::PSUBSWrm, makeRMInst },
629 { X86::PSUBWrr, X86::PSUBWrm, makeRMInst },
630 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, makeRMInst },
631 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, makeRMInst },
632 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, makeRMInst },
633 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, makeRMInst },
634 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, makeRMInst },
635 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, makeRMInst },
636 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, makeRMInst },
637 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, makeRMInst },
638 { X86::PXORrr, X86::PXORrm, makeRMInst },
639 { X86::RCPPSr, X86::RCPPSm, makeRMInst },
640 { X86::RSQRTPSr, X86::RSQRTPSm, makeRMInst },
641 { X86::SBB32rr, X86::SBB32rm, makeRMInst },
642 { X86::SHUFPDrri, X86::SHUFPDrmi, makeRMIInst },
643 { X86::SHUFPSrri, X86::SHUFPSrmi, makeRMIInst },
644 { X86::SQRTPDr, X86::SQRTPDm, makeRMInst },
645 { X86::SQRTPSr, X86::SQRTPSm, makeRMInst },
646 { X86::SQRTSDr, X86::SQRTSDm, makeRMInst },
647 { X86::SQRTSSr, X86::SQRTSSm, makeRMInst },
648 { X86::SUB16rr, X86::SUB16rm, makeRMInst },
649 { X86::SUB32rr, X86::SUB32rm, makeRMInst },
650 { X86::SUB8rr, X86::SUB8rm, makeRMInst },
651 { X86::SUBPDrr, X86::SUBPDrm, makeRMInst },
652 { X86::SUBPSrr, X86::SUBPSrm, makeRMInst },
653 { X86::SUBSDrr, X86::SUBSDrm, makeRMInst },
654 { X86::SUBSSrr, X86::SUBSSrm, makeRMInst },
655 { X86::TEST16ri, X86::TEST16mi, makeMIInst },
656 { X86::TEST16rr, X86::TEST16rm, makeRMInst },
657 { X86::TEST32ri, X86::TEST32mi, makeMIInst },
658 { X86::TEST32rr, X86::TEST32rm, makeRMInst },
659 { X86::TEST8ri, X86::TEST8mi, makeMIInst },
660 { X86::TEST8rr, X86::TEST8rm, makeRMInst },
661 { X86::UCOMISDrr, X86::UCOMISDrm, makeRMInst },
662 { X86::UCOMISSrr, X86::UCOMISSrm, makeRMInst },
663 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, makeRMInst },
664 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, makeRMInst },
665 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, makeRMInst },
666 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, makeRMInst },
667 { X86::XCHG16rr, X86::XCHG16rm, makeRMInst },
668 { X86::XCHG32rr, X86::XCHG32rm, makeRMInst },
669 { X86::XCHG8rr, X86::XCHG8rm, makeRMInst },
670 { X86::XOR16rr, X86::XOR16rm, makeRMInst },
671 { X86::XOR32rr, X86::XOR32rm, makeRMInst },
672 { X86::XOR8rr, X86::XOR8rm, makeRMInst },
673 { X86::XORPDrr, X86::XORPDrm, makeRMInst },
674 { X86::XORPSrr, X86::XORPSrm, makeRMInst }
676 ASSERT_SORTED(OpcodeTable);
677 OpcodeTablePtr = OpcodeTable;
678 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
682 if (OpcodeTablePtr) {
684 unsigned fromOpcode = MI->getOpcode();
685 // Lookup fromOpcode in table
686 const TableEntry *entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
689 // If opcode found in table
692 unsigned toOpcode = entry->to;
694 // Make new instruction
695 switch (entry->make) {
696 case makeM0Inst: return MakeM0Inst(toOpcode, FrameIndex, MI);
697 case makeMIInst: return MakeMIInst(toOpcode, FrameIndex, MI);
698 case makeMInst: return MakeMInst(toOpcode, FrameIndex, MI);
699 case makeMRIInst: return MakeMRIInst(toOpcode, FrameIndex, MI);
700 case makeMRInst: return MakeMRInst(toOpcode, FrameIndex, MI);
701 case makeRMIInst: return MakeRMIInst(toOpcode, FrameIndex, MI);
702 case makeRMInst: return MakeRMInst(toOpcode, FrameIndex, MI);
703 default: assert(0 && "Unknown instruction make");
709 if (PrintFailedFusing)
710 std::cerr << "We failed to fuse ("
711 << ((i == 1) ? "r" : "s") << "): " << *MI;
716 const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
717 static const unsigned CalleeSaveRegs[] = {
718 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
720 return CalleeSaveRegs;
723 const TargetRegisterClass* const*
724 X86RegisterInfo::getCalleeSaveRegClasses() const {
725 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
726 &X86::GR32RegClass, &X86::GR32RegClass,
727 &X86::GR32RegClass, &X86::GR32RegClass, 0
729 return CalleeSaveRegClasses;
732 //===----------------------------------------------------------------------===//
733 // Stack Frame Processing methods
734 //===----------------------------------------------------------------------===//
736 // hasFP - Return true if the specified function should have a dedicated frame
737 // pointer register. This is true if the function has variable sized allocas or
738 // if frame pointer elimination is disabled.
740 static bool hasFP(MachineFunction &MF) {
741 return (NoFramePointerElim ||
742 MF.getFrameInfo()->hasVarSizedObjects() ||
743 MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
746 void X86RegisterInfo::
747 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
748 MachineBasicBlock::iterator I) const {
750 // If we have a frame pointer, turn the adjcallstackup instruction into a
751 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
753 MachineInstr *Old = I;
754 unsigned Amount = Old->getOperand(0).getImmedValue();
756 // We need to keep the stack aligned properly. To do this, we round the
757 // amount of space needed for the outgoing arguments up to the next
758 // alignment boundary.
759 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
760 Amount = (Amount+Align-1)/Align*Align;
762 MachineInstr *New = 0;
763 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
764 New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
767 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
768 // factor out the amount the callee already popped.
769 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
772 unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
773 New = BuildMI(Opc, 1, X86::ESP,
774 MachineOperand::UseAndDef).addImm(Amount);
778 // Replace the pseudo instruction with a new instruction...
779 if (New) MBB.insert(I, New);
781 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
782 // If we are performing frame pointer elimination and if the callee pops
783 // something off the stack pointer, add it back. We do this until we have
784 // more advanced stack pointer tracking ability.
785 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
786 unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
788 BuildMI(Opc, 1, X86::ESP,
789 MachineOperand::UseAndDef).addImm(CalleeAmt);
797 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
799 MachineInstr &MI = *II;
800 MachineFunction &MF = *MI.getParent()->getParent();
801 while (!MI.getOperand(i).isFrameIndex()) {
803 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
806 int FrameIndex = MI.getOperand(i).getFrameIndex();
808 // This must be part of a four operand memory reference. Replace the
809 // FrameIndex with base register with EBP. Add add an offset to the offset.
810 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
812 // Now add the frame object offset to the offset from EBP.
813 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
814 MI.getOperand(i+3).getImmedValue()+4;
817 Offset += MF.getFrameInfo()->getStackSize();
819 Offset += 4; // Skip the saved EBP
821 MI.getOperand(i+3).ChangeToImmediate(Offset);
825 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
827 // Create a frame entry for the EBP register that must be saved.
828 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
829 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
830 "Slot for EBP register must be last in order to be found!");
834 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
835 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
836 MachineBasicBlock::iterator MBBI = MBB.begin();
837 MachineFrameInfo *MFI = MF.getFrameInfo();
838 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
839 const Function* Fn = MF.getFunction();
840 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
843 // Get the number of bytes to allocate from the FrameInfo
844 unsigned NumBytes = MFI->getStackSize();
845 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
846 // When we have no frame pointer, we reserve argument space for call sites
847 // in the function immediately on entry to the current function. This
848 // eliminates the need for add/sub ESP brackets around call sites.
851 NumBytes += MFI->getMaxCallFrameSize();
853 // Round the size to a multiple of the alignment (don't forget the 4 byte
855 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
858 // Update frame info to pretend that this is part of the stack...
859 MFI->setStackSize(NumBytes);
861 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
862 if (NumBytes >= 4096 && Subtarget->TargetType == X86Subtarget::isCygwin) {
863 // Function prologue calls _alloca to probe the stack when allocating
864 // more than 4k bytes in one go. Touching the stack at 4K increments is
865 // necessary to ensure that the guard pages used by the OS virtual memory
866 // manager are allocated in correct sequence.
867 MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
868 MBB.insert(MBBI, MI);
869 MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
870 MBB.insert(MBBI, MI);
872 unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
873 MI = BuildMI(Opc, 1, X86::ESP,MachineOperand::UseAndDef).addImm(NumBytes);
874 MBB.insert(MBBI, MI);
879 // Get the offset of the stack slot for the EBP register... which is
880 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
881 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
883 // Save EBP into the appropriate stack slot...
884 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
885 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
886 MBB.insert(MBBI, MI);
888 // Update EBP with the new base value...
889 if (NumBytes == 4) // mov EBP, ESP
890 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
891 else // lea EBP, [ESP+StackSize]
892 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
894 MBB.insert(MBBI, MI);
897 // If it's main() on Cygwin\Mingw32 we should align stack as well
898 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
899 Subtarget->TargetType == X86Subtarget::isCygwin) {
900 MI = BuildMI(X86::AND32ri, 2, X86::ESP).addImm(-Align);
901 MBB.insert(MBBI, MI);
904 MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
905 MBB.insert(MBBI, MI);
906 MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
907 MBB.insert(MBBI, MI);
911 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
912 MachineBasicBlock &MBB) const {
913 const MachineFrameInfo *MFI = MF.getFrameInfo();
914 MachineBasicBlock::iterator MBBI = prior(MBB.end());
916 switch (MBBI->getOpcode()) {
921 case X86::TAILJMPm: break; // These are ok
923 assert(0 && "Can only insert epilog into returning blocks");
927 // Get the offset of the stack slot for the EBP register... which is
928 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
929 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
932 BuildMI(MBB, MBBI, X86::MOV32rr, 1,X86::ESP).addReg(X86::EBP);
935 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
937 // Get the number of bytes allocated from the FrameInfo...
938 unsigned NumBytes = MFI->getStackSize();
940 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
941 // If there is an ADD32ri or SUB32ri of ESP immediately before this
942 // instruction, merge the two instructions.
943 if (MBBI != MBB.begin()) {
944 MachineBasicBlock::iterator PI = prior(MBBI);
945 if ((PI->getOpcode() == X86::ADD32ri ||
946 PI->getOpcode() == X86::ADD32ri8) &&
947 PI->getOperand(0).getReg() == X86::ESP) {
948 NumBytes += PI->getOperand(1).getImmedValue();
950 } else if ((PI->getOpcode() == X86::SUB32ri ||
951 PI->getOpcode() == X86::SUB32ri8) &&
952 PI->getOperand(0).getReg() == X86::ESP) {
953 NumBytes -= PI->getOperand(1).getImmedValue();
955 } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
956 NumBytes += PI->getOperand(1).getImmedValue();
962 unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
963 BuildMI(MBB, MBBI, Opc, 2)
964 .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(NumBytes);
965 } else if ((int)NumBytes < 0) {
966 unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
967 BuildMI(MBB, MBBI, Opc, 2)
968 .addReg(X86::ESP, MachineOperand::UseAndDef).addImm(-NumBytes);
974 unsigned X86RegisterInfo::getRARegister() const {
975 return X86::ST0; // use a non-register register
978 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
979 return hasFP(MF) ? X86::EBP : X86::ESP;
983 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
990 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
992 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
994 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
996 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
1001 default: return Reg;
1002 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
1004 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
1006 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
1008 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
1014 default: return Reg;
1015 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
1017 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
1019 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
1021 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
1034 default: return true;
1035 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
1037 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
1039 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
1041 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
1058 #include "X86GenRegisterInfo.inc"