1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "Support/CommandLine.h"
27 #include "Support/STLExtras.h"
32 NoFPElim("disable-fp-elim",
33 cl::desc("Disable frame pointer elimination optimization"));
36 X86RegisterInfo::X86RegisterInfo()
37 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
39 static unsigned getIdx(const TargetRegisterClass *RC) {
40 switch (RC->getSize()) {
41 default: assert(0 && "Invalid data size!");
49 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI,
51 unsigned SrcReg, int FrameIdx,
52 const TargetRegisterClass *RC) const {
53 static const unsigned Opcode[] =
54 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
55 MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
56 FrameIdx).addReg(SrcReg);
61 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MI,
63 unsigned DestReg, int FrameIdx,
64 const TargetRegisterClass *RC) const{
65 static const unsigned Opcode[] =
66 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
67 unsigned OC = Opcode[getIdx(RC)];
68 MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
72 int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI,
74 unsigned DestReg, unsigned SrcReg,
75 const TargetRegisterClass *RC) const {
76 static const unsigned Opcode[] =
77 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
78 MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
82 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
84 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
85 .addReg(MI->getOperand(1).getReg());
88 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
90 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
91 .addZImm(MI->getOperand(1).getImmedValue());
94 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
96 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
100 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
102 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
103 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
107 bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
108 unsigned i, int FrameIndex) const {
109 /// FIXME: This should obviously be autogenerated by tablegen when patterns
111 MachineBasicBlock& MBB = *MI->getParent();
112 MachineInstr* NI = 0;
114 switch(MI->getOpcode()) {
115 case X86::MOVrr8: NI = MakeMRInst(X86::MOVmr8 , FrameIndex, MI); break;
116 case X86::MOVrr16: NI = MakeMRInst(X86::MOVmr16, FrameIndex, MI); break;
117 case X86::MOVrr32: NI = MakeMRInst(X86::MOVmr32, FrameIndex, MI); break;
118 case X86::ADDrr8: NI = MakeMRInst(X86::ADDmr8 , FrameIndex, MI); break;
119 case X86::ADDrr16: NI = MakeMRInst(X86::ADDmr16, FrameIndex, MI); break;
120 case X86::ADDrr32: NI = MakeMRInst(X86::ADDmr32, FrameIndex, MI); break;
121 case X86::ADDri8: NI = MakeMIInst(X86::ADDmi8 , FrameIndex, MI); break;
122 case X86::ADDri16: NI = MakeMIInst(X86::ADDmi16, FrameIndex, MI); break;
123 case X86::ADDri32: NI = MakeMIInst(X86::ADDmi32, FrameIndex, MI); break;
124 case X86::ANDrr8: NI = MakeMRInst(X86::ANDmr8 , FrameIndex, MI); break;
125 case X86::ANDrr16: NI = MakeMRInst(X86::ANDmr16, FrameIndex, MI); break;
126 case X86::ANDrr32: NI = MakeMRInst(X86::ANDmr32, FrameIndex, MI); break;
127 case X86::ANDri8: NI = MakeMIInst(X86::ANDmi8 , FrameIndex, MI); break;
128 case X86::ANDri16: NI = MakeMIInst(X86::ANDmi16, FrameIndex, MI); break;
129 case X86::ANDri32: NI = MakeMIInst(X86::ANDmi32, FrameIndex, MI); break;
130 default: return false; // Cannot fold
133 switch(MI->getOpcode()) {
134 case X86::MOVrr8: NI = MakeRMInst(X86::MOVrm8 , FrameIndex, MI); break;
135 case X86::MOVrr16: NI = MakeRMInst(X86::MOVrm16, FrameIndex, MI); break;
136 case X86::MOVrr32: NI = MakeRMInst(X86::MOVrm32, FrameIndex, MI); break;
137 case X86::ADDrr8: NI = MakeRMInst(X86::ADDrm8 , FrameIndex, MI); break;
138 case X86::ADDrr16: NI = MakeRMInst(X86::ADDrm16, FrameIndex, MI); break;
139 case X86::ADDrr32: NI = MakeRMInst(X86::ADDrm32, FrameIndex, MI); break;
140 case X86::ANDrr8: NI = MakeRMInst(X86::ANDrm8 , FrameIndex, MI); break;
141 case X86::ANDrr16: NI = MakeRMInst(X86::ANDrm16, FrameIndex, MI); break;
142 case X86::ANDrr32: NI = MakeRMInst(X86::ANDrm32, FrameIndex, MI); break;
143 case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break;
144 case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break;
145 case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI); break;
146 case X86::IMULrri32: NI = MakeRMIInst(X86::IMULrmi32, FrameIndex, MI); break;
147 default: return false; // cannot fold.
150 return false; // cannot fold.
153 MI = MBB.insert(MBB.erase(MI), NI);
157 //===----------------------------------------------------------------------===//
158 // Stack Frame Processing methods
159 //===----------------------------------------------------------------------===//
161 // hasFP - Return true if the specified function should have a dedicated frame
162 // pointer register. This is true if the function has variable sized allocas or
163 // if frame pointer elimination is disabled.
165 static bool hasFP(MachineFunction &MF) {
166 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
169 void X86RegisterInfo::
170 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
171 MachineBasicBlock::iterator I) const {
173 // If we have a frame pointer, turn the adjcallstackup instruction into a
174 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
176 MachineInstr *Old = I;
177 unsigned Amount = Old->getOperand(0).getImmedValue();
179 // We need to keep the stack aligned properly. To do this, we round the
180 // amount of space needed for the outgoing arguments up to the next
181 // alignment boundary.
182 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
183 Amount = (Amount+Align-1)/Align*Align;
186 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
187 New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
189 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
190 New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
193 // Replace the pseudo instruction with a new instruction...
201 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
202 MachineBasicBlock::iterator II) const {
204 MachineInstr &MI = *II;
205 while (!MI.getOperand(i).isFrameIndex()) {
207 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
210 int FrameIndex = MI.getOperand(i).getFrameIndex();
212 // This must be part of a four operand memory reference. Replace the
213 // FrameIndex with base register with EBP. Add add an offset to the offset.
214 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
216 // Now add the frame object offset to the offset from EBP.
217 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
218 MI.getOperand(i+3).getImmedValue()+4;
221 Offset += MF.getFrameInfo()->getStackSize();
223 Offset += 4; // Skip the saved EBP
225 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
229 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
231 // Create a frame entry for the EBP register that must be saved.
232 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
233 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
234 "Slot for EBP register must be last in order to be found!");
238 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
239 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
240 MachineBasicBlock::iterator MBBI = MBB.begin();
241 MachineFrameInfo *MFI = MF.getFrameInfo();
244 // Get the number of bytes to allocate from the FrameInfo
245 unsigned NumBytes = MFI->getStackSize();
247 // Get the offset of the stack slot for the EBP register... which is
248 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
249 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
251 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
252 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
253 MBB.insert(MBBI, MI);
256 // Save EBP into the appropriate stack slot...
257 MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
258 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
259 MBB.insert(MBBI, MI);
261 // Update EBP with the new base value...
262 if (NumBytes == 4) // mov EBP, ESP
263 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
264 else // lea EBP, [ESP+StackSize]
265 MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP,NumBytes-4);
267 MBB.insert(MBBI, MI);
270 if (MFI->hasCalls()) {
271 // When we have no frame pointer, we reserve argument space for call sites
272 // in the function immediately on entry to the current function. This
273 // eliminates the need for add/sub ESP brackets around call sites.
275 NumBytes += MFI->getMaxCallFrameSize();
277 // Round the size to a multiple of the alignment (don't forget the 4 byte
279 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
280 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
283 // Update frame info to pretend that this is part of the stack...
284 MFI->setStackSize(NumBytes);
287 // adjust stack pointer: ESP -= numbytes
288 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
289 MBB.insert(MBBI, MI);
294 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
295 MachineBasicBlock &MBB) const {
296 const MachineFrameInfo *MFI = MF.getFrameInfo();
297 MachineBasicBlock::iterator MBBI = prior(MBB.end());
299 assert(MBBI->getOpcode() == X86::RET &&
300 "Can only insert epilog into returning blocks");
303 // Get the offset of the stack slot for the EBP register... which is
304 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
305 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
308 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
309 MBB.insert(MBBI, MI);
312 MI = BuildMI(X86::POPr32, 0, X86::EBP);
313 MBB.insert(MBBI, MI);
315 // Get the number of bytes allocated from the FrameInfo...
316 unsigned NumBytes = MFI->getStackSize();
318 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
319 MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
320 MBB.insert(MBBI, MI);
325 #include "X86GenRegisterInfo.inc"
327 const TargetRegisterClass*
328 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
329 switch (Ty->getPrimitiveID()) {
331 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
332 default: assert(0 && "Invalid type to getClass!");
334 case Type::SByteTyID:
335 case Type::UByteTyID: return &R8Instance;
336 case Type::ShortTyID:
337 case Type::UShortTyID: return &R16Instance;
340 case Type::PointerTyID: return &R32Instance;
342 case Type::FloatTyID:
343 case Type::DoubleTyID: return &RFPInstance;