1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71 /// specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 /// getX86RegNum - This function maps LLVM register identifiers to their X86
94 /// specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass ||
169 A == &X86::GR64_NOSPRegClass ||
170 A == &X86::GR64_NOREX_NOSPRegClass)
171 return &X86::GR64_ABCDRegClass;
172 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173 A == &X86::GR32_NOREXRegClass ||
174 A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177 A == &X86::GR16_NOREXRegClass)
178 return &X86::GR16_ABCDRegClass;
179 } else if (B == &X86::GR8_NOREXRegClass) {
180 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_NOREXRegClass;
183 else if (A == &X86::GR64_ABCDRegClass)
184 return &X86::GR64_ABCDRegClass;
185 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186 A == &X86::GR32_NOSPRegClass)
187 return &X86::GR32_NOREXRegClass;
188 else if (A == &X86::GR32_ABCDRegClass)
189 return &X86::GR32_ABCDRegClass;
190 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191 return &X86::GR16_NOREXRegClass;
192 else if (A == &X86::GR16_ABCDRegClass)
193 return &X86::GR16_ABCDRegClass;
198 if (B == &X86::GR8_ABCD_HRegClass) {
199 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
200 A == &X86::GR64_NOREXRegClass ||
201 A == &X86::GR64_NOSPRegClass ||
202 A == &X86::GR64_NOREX_NOSPRegClass)
203 return &X86::GR64_ABCDRegClass;
204 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
205 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
206 return &X86::GR32_ABCDRegClass;
207 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
208 A == &X86::GR16_NOREXRegClass)
209 return &X86::GR16_ABCDRegClass;
214 if (B == &X86::GR16RegClass) {
215 if (A->getSize() == 4 || A->getSize() == 8)
217 } else if (B == &X86::GR16_ABCDRegClass) {
218 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
219 A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass ||
221 A == &X86::GR64_NOREX_NOSPRegClass)
222 return &X86::GR64_ABCDRegClass;
223 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
224 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
225 return &X86::GR32_ABCDRegClass;
226 } else if (B == &X86::GR16_NOREXRegClass) {
227 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
228 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
229 return &X86::GR64_NOREXRegClass;
230 else if (A == &X86::GR64_ABCDRegClass)
231 return &X86::GR64_ABCDRegClass;
232 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
233 A == &X86::GR32_NOSPRegClass)
234 return &X86::GR32_NOREXRegClass;
235 else if (A == &X86::GR32_ABCDRegClass)
236 return &X86::GR64_ABCDRegClass;
241 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
242 if (A->getSize() == 8)
244 } else if (B == &X86::GR32_ABCDRegClass) {
245 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
246 A == &X86::GR64_NOREXRegClass ||
247 A == &X86::GR64_NOSPRegClass ||
248 A == &X86::GR64_NOREX_NOSPRegClass)
249 return &X86::GR64_ABCDRegClass;
250 } else if (B == &X86::GR32_NOREXRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
252 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
253 return &X86::GR64_NOREXRegClass;
254 else if (A == &X86::GR64_ABCDRegClass)
255 return &X86::GR64_ABCDRegClass;
262 const TargetRegisterClass *
263 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
265 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
266 case 0: // Normal GPRs.
267 if (TM.getSubtarget<X86Subtarget>().is64Bit())
268 return &X86::GR64RegClass;
269 return &X86::GR32RegClass;
270 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
271 if (TM.getSubtarget<X86Subtarget>().is64Bit())
272 return &X86::GR64_NOSPRegClass;
273 return &X86::GR32_NOSPRegClass;
277 const TargetRegisterClass *
278 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
279 if (RC == &X86::CCRRegClass) {
281 return &X86::GR64RegClass;
283 return &X86::GR32RegClass;
289 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
290 bool callsEHReturn = false;
293 const MachineFrameInfo *MFI = MF->getFrameInfo();
294 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
295 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
298 static const unsigned CalleeSavedRegs32Bit[] = {
299 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
302 static const unsigned CalleeSavedRegs32EHRet[] = {
303 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
306 static const unsigned CalleeSavedRegs64Bit[] = {
307 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
310 static const unsigned CalleeSavedRegs64EHRet[] = {
311 X86::RAX, X86::RDX, X86::RBX, X86::R12,
312 X86::R13, X86::R14, X86::R15, X86::RBP, 0
315 static const unsigned CalleeSavedRegsWin64[] = {
316 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
317 X86::R12, X86::R13, X86::R14, X86::R15,
318 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
319 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
320 X86::XMM14, X86::XMM15, 0
325 return CalleeSavedRegsWin64;
327 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
329 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
333 const TargetRegisterClass* const*
334 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
335 bool callsEHReturn = false;
338 const MachineFrameInfo *MFI = MF->getFrameInfo();
339 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
340 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
343 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
344 &X86::GR32RegClass, &X86::GR32RegClass,
345 &X86::GR32RegClass, &X86::GR32RegClass, 0
347 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
348 &X86::GR32RegClass, &X86::GR32RegClass,
349 &X86::GR32RegClass, &X86::GR32RegClass,
350 &X86::GR32RegClass, &X86::GR32RegClass, 0
352 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
353 &X86::GR64RegClass, &X86::GR64RegClass,
354 &X86::GR64RegClass, &X86::GR64RegClass,
355 &X86::GR64RegClass, &X86::GR64RegClass, 0
357 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
358 &X86::GR64RegClass, &X86::GR64RegClass,
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass, 0
363 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
364 &X86::GR64RegClass, &X86::GR64RegClass,
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::VR128RegClass, &X86::VR128RegClass,
369 &X86::VR128RegClass, &X86::VR128RegClass,
370 &X86::VR128RegClass, &X86::VR128RegClass,
371 &X86::VR128RegClass, &X86::VR128RegClass,
372 &X86::VR128RegClass, &X86::VR128RegClass, 0
377 return CalleeSavedRegClassesWin64;
379 return (callsEHReturn ?
380 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
382 return (callsEHReturn ?
383 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
387 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
388 BitVector Reserved(getNumRegs());
389 // Set the stack-pointer register and its aliases as reserved.
390 Reserved.set(X86::RSP);
391 Reserved.set(X86::ESP);
392 Reserved.set(X86::SP);
393 Reserved.set(X86::SPL);
395 // Set the instruction pointer register and its aliases as reserved.
396 Reserved.set(X86::RIP);
397 Reserved.set(X86::EIP);
398 Reserved.set(X86::IP);
400 // Set the frame-pointer register and its aliases as reserved if needed.
402 Reserved.set(X86::RBP);
403 Reserved.set(X86::EBP);
404 Reserved.set(X86::BP);
405 Reserved.set(X86::BPL);
408 // Mark the x87 stack registers as reserved, since they don't behave normally
409 // with respect to liveness. We don't fully model the effects of x87 stack
410 // pushes and pops after stackification.
411 Reserved.set(X86::ST0);
412 Reserved.set(X86::ST1);
413 Reserved.set(X86::ST2);
414 Reserved.set(X86::ST3);
415 Reserved.set(X86::ST4);
416 Reserved.set(X86::ST5);
417 Reserved.set(X86::ST6);
418 Reserved.set(X86::ST7);
422 //===----------------------------------------------------------------------===//
423 // Stack Frame Processing methods
424 //===----------------------------------------------------------------------===//
426 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
427 unsigned MaxAlign = 0;
429 for (int i = FFI->getObjectIndexBegin(),
430 e = FFI->getObjectIndexEnd(); i != e; ++i) {
431 if (FFI->isDeadObjectIndex(i))
434 unsigned Align = FFI->getObjectAlignment(i);
435 MaxAlign = std::max(MaxAlign, Align);
441 /// hasFP - Return true if the specified function should have a dedicated frame
442 /// pointer register. This is true if the function has variable sized allocas
443 /// or if frame pointer elimination is disabled.
444 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
445 const MachineFrameInfo *MFI = MF.getFrameInfo();
446 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
448 return (NoFramePointerElim ||
449 needsStackRealignment(MF) ||
450 MFI->hasVarSizedObjects() ||
451 MFI->isFrameAddressTaken() ||
452 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
453 (MMI && MMI->callsUnwindInit()));
456 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
457 const MachineFrameInfo *MFI = MF.getFrameInfo();
458 bool requiresRealignment =
459 RealignStack && (MFI->getMaxAlignment() > StackAlign);
461 // FIXME: Currently we don't support stack realignment for functions with
462 // variable-sized allocas
463 if (requiresRealignment && MFI->hasVarSizedObjects())
465 "Stack realignment in presense of dynamic allocas is not supported");
467 return requiresRealignment;
470 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
471 return !MF.getFrameInfo()->hasVarSizedObjects();
474 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
475 int &FrameIdx) const {
476 if (Reg == FramePtr && hasFP(MF)) {
477 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
484 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
485 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
486 MachineFrameInfo *MFI = MF.getFrameInfo();
487 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
488 uint64_t StackSize = MFI->getStackSize();
490 if (needsStackRealignment(MF)) {
492 // Skip the saved EBP.
495 unsigned Align = MFI->getObjectAlignment(FI);
496 assert( (-(Offset + StackSize)) % Align == 0);
498 return Offset + StackSize;
500 // FIXME: Support tail calls
503 return Offset + StackSize;
505 // Skip the saved EBP.
508 // Skip the RETADDR move area
509 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
510 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
511 if (TailCallReturnAddrDelta < 0)
512 Offset -= TailCallReturnAddrDelta;
518 void X86RegisterInfo::
519 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
520 MachineBasicBlock::iterator I) const {
521 if (!hasReservedCallFrame(MF)) {
522 // If the stack pointer can be changed after prologue, turn the
523 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
524 // adjcallstackdown instruction into 'add ESP, <amt>'
525 // TODO: consider using push / pop instead of sub + store / add
526 MachineInstr *Old = I;
527 uint64_t Amount = Old->getOperand(0).getImm();
529 // We need to keep the stack aligned properly. To do this, we round the
530 // amount of space needed for the outgoing arguments up to the next
531 // alignment boundary.
532 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
534 MachineInstr *New = 0;
535 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
536 New = BuildMI(MF, Old->getDebugLoc(),
537 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
542 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
544 // Factor out the amount the callee already popped.
545 uint64_t CalleeAmt = Old->getOperand(1).getImm();
549 unsigned Opc = (Amount < 128) ?
550 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
551 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
552 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
559 // The EFLAGS implicit def is dead.
560 New->getOperand(3).setIsDead();
562 // Replace the pseudo instruction with a new instruction.
566 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
567 // If we are performing frame pointer elimination and if the callee pops
568 // something off the stack pointer, add it back. We do this until we have
569 // more advanced stack pointer tracking ability.
570 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
571 unsigned Opc = (CalleeAmt < 128) ?
572 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
573 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
574 MachineInstr *Old = I;
576 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
581 // The EFLAGS implicit def is dead.
582 New->getOperand(3).setIsDead();
591 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
592 int SPAdj, int *Value,
593 RegScavenger *RS) const{
594 assert(SPAdj == 0 && "Unexpected");
597 MachineInstr &MI = *II;
598 MachineFunction &MF = *MI.getParent()->getParent();
600 while (!MI.getOperand(i).isFI()) {
602 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
605 int FrameIndex = MI.getOperand(i).getIndex();
608 if (needsStackRealignment(MF))
609 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
611 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
613 // This must be part of a four operand memory reference. Replace the
614 // FrameIndex with base register with EBP. Add an offset to the offset.
615 MI.getOperand(i).ChangeToRegister(BasePtr, false);
617 // Now add the frame object offset to the offset from EBP.
618 if (MI.getOperand(i+3).isImm()) {
619 // Offset is a 32-bit integer.
620 int Offset = getFrameIndexOffset(MF, FrameIndex) +
621 (int)(MI.getOperand(i + 3).getImm());
623 MI.getOperand(i + 3).ChangeToImmediate(Offset);
625 // Offset is symbolic. This is extremely rare.
626 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
627 (uint64_t)MI.getOperand(i+3).getOffset();
628 MI.getOperand(i+3).setOffset(Offset);
634 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
635 RegScavenger *RS) const {
636 MachineFrameInfo *MFI = MF.getFrameInfo();
638 // Calculate and set max stack object alignment early, so we can decide
639 // whether we will need stack realignment (and thus FP).
640 unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
641 calculateMaxStackAlignment(MFI));
643 MFI->setMaxAlignment(MaxAlign);
645 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
646 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
648 if (TailCallReturnAddrDelta < 0) {
649 // create RETURNADDR area
658 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
659 (-1U*SlotSize)+TailCallReturnAddrDelta,
664 assert((TailCallReturnAddrDelta <= 0) &&
665 "The Delta should always be zero or negative");
666 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
668 // Create a frame entry for the EBP register that must be saved.
669 int FrameIdx = MFI->CreateFixedObject(SlotSize,
671 TFI.getOffsetOfLocalArea() +
672 TailCallReturnAddrDelta,
674 assert(FrameIdx == MFI->getObjectIndexBegin() &&
675 "Slot for EBP register must be last in order to be found!");
680 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
681 /// stack pointer by a constant value.
683 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
684 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
685 const TargetInstrInfo &TII) {
686 bool isSub = NumBytes < 0;
687 uint64_t Offset = isSub ? -NumBytes : NumBytes;
690 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
691 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
693 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
694 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
695 uint64_t Chunk = (1LL << 31) - 1;
696 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
697 DebugLoc::getUnknownLoc());
700 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
702 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
705 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
710 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
712 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
713 unsigned StackPtr, uint64_t *NumBytes = NULL) {
714 if (MBBI == MBB.begin()) return;
716 MachineBasicBlock::iterator PI = prior(MBBI);
717 unsigned Opc = PI->getOpcode();
718 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
719 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
720 PI->getOperand(0).getReg() == StackPtr) {
722 *NumBytes += PI->getOperand(2).getImm();
724 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
725 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
726 PI->getOperand(0).getReg() == StackPtr) {
728 *NumBytes -= PI->getOperand(2).getImm();
733 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
735 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
736 MachineBasicBlock::iterator &MBBI,
737 unsigned StackPtr, uint64_t *NumBytes = NULL) {
738 // FIXME: THIS ISN'T RUN!!!
741 if (MBBI == MBB.end()) return;
743 MachineBasicBlock::iterator NI = next(MBBI);
744 if (NI == MBB.end()) return;
746 unsigned Opc = NI->getOpcode();
747 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
748 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
749 NI->getOperand(0).getReg() == StackPtr) {
751 *NumBytes -= NI->getOperand(2).getImm();
754 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
755 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
756 NI->getOperand(0).getReg() == StackPtr) {
758 *NumBytes += NI->getOperand(2).getImm();
764 /// mergeSPUpdates - Checks the instruction before/after the passed
765 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
766 /// stack adjustment is returned as a positive value for ADD and a negative for
768 static int mergeSPUpdates(MachineBasicBlock &MBB,
769 MachineBasicBlock::iterator &MBBI,
771 bool doMergeWithPrevious) {
772 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
773 (!doMergeWithPrevious && MBBI == MBB.end()))
776 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
777 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
778 unsigned Opc = PI->getOpcode();
781 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
782 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
783 PI->getOperand(0).getReg() == StackPtr){
784 Offset += PI->getOperand(2).getImm();
786 if (!doMergeWithPrevious) MBBI = NI;
787 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
788 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
789 PI->getOperand(0).getReg() == StackPtr) {
790 Offset -= PI->getOperand(2).getImm();
792 if (!doMergeWithPrevious) MBBI = NI;
798 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
800 unsigned FramePtr) const {
801 MachineFrameInfo *MFI = MF.getFrameInfo();
802 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
805 // Add callee saved registers to move list.
806 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
807 if (CSI.empty()) return;
809 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
810 const TargetData *TD = MF.getTarget().getTargetData();
811 bool HasFP = hasFP(MF);
813 // Calculate amount of bytes used for return address storing.
815 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
816 TargetFrameInfo::StackGrowsUp ?
817 TD->getPointerSize() : -TD->getPointerSize());
819 // FIXME: This is dirty hack. The code itself is pretty mess right now.
820 // It should be rewritten from scratch and generalized sometimes.
822 // Determine maximum offset (minumum due to stack growth).
823 int64_t MaxOffset = 0;
824 for (std::vector<CalleeSavedInfo>::const_iterator
825 I = CSI.begin(), E = CSI.end(); I != E; ++I)
826 MaxOffset = std::min(MaxOffset,
827 MFI->getObjectOffset(I->getFrameIdx()));
829 // Calculate offsets.
830 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
831 for (std::vector<CalleeSavedInfo>::const_iterator
832 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
833 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
834 unsigned Reg = I->getReg();
835 Offset = MaxOffset - Offset + saveAreaOffset;
837 // Don't output a new machine move if we're re-saving the frame
838 // pointer. This happens when the PrologEpilogInserter has inserted an extra
839 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
840 // generates one when frame pointers are used. If we generate a "machine
841 // move" for this extra "PUSH", the linker will lose track of the fact that
842 // the frame pointer should have the value of the first "PUSH" when it's
845 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
846 // another bug. I.e., one where we generate a prolog like this:
854 // The immediate re-push of EBP is unnecessary. At the least, it's an
855 // optimization bug. EBP can be used as a scratch register in certain
856 // cases, but probably not when we have a frame pointer.
857 if (HasFP && FramePtr == Reg)
860 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
861 MachineLocation CSSrc(Reg);
862 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
866 /// emitPrologue - Push callee-saved registers onto the stack, which
867 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
868 /// space for local variables. Also emit labels used by the exception handler to
869 /// generate the exception handling frames.
870 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
871 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
872 MachineBasicBlock::iterator MBBI = MBB.begin();
873 MachineFrameInfo *MFI = MF.getFrameInfo();
874 const Function *Fn = MF.getFunction();
875 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
876 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
877 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
878 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
879 !Fn->doesNotThrow() || UnwindTablesMandatory;
880 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
881 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
882 bool HasFP = hasFP(MF);
885 // Add RETADDR move area to callee saved frame size.
886 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
887 if (TailCallReturnAddrDelta < 0)
888 X86FI->setCalleeSavedFrameSize(
889 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
891 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
892 // function, and use up to 128 bytes of stack space, don't have a frame
893 // pointer, calls, or dynamic alloca then we do not need to adjust the
894 // stack pointer (we fit in the Red Zone).
895 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
896 !needsStackRealignment(MF) &&
897 !MFI->hasVarSizedObjects() && // No dynamic alloca.
898 !MFI->hasCalls() && // No calls.
899 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
900 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
901 if (HasFP) MinSize += SlotSize;
902 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
903 MFI->setStackSize(StackSize);
904 } else if (Subtarget->isTargetWin64()) {
905 // We need to always allocate 32 bytes as register spill area.
906 // FIXME: We might reuse these 32 bytes for leaf functions.
908 MFI->setStackSize(StackSize);
911 // Insert stack pointer adjustment for later moving of return addr. Only
912 // applies to tail call optimized functions where the callee argument stack
913 // size is bigger than the callers.
914 if (TailCallReturnAddrDelta < 0) {
916 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
919 .addImm(-TailCallReturnAddrDelta);
920 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
923 // Mapping for machine moves:
925 // DST: VirtualFP AND
926 // SRC: VirtualFP => DW_CFA_def_cfa_offset
927 // ELSE => DW_CFA_def_cfa
929 // SRC: VirtualFP AND
930 // DST: Register => DW_CFA_def_cfa_register
933 // OFFSET < 0 => DW_CFA_offset_extended_sf
934 // REG < 64 => DW_CFA_offset + Reg
935 // ELSE => DW_CFA_offset_extended
937 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
938 const TargetData *TD = MF.getTarget().getTargetData();
939 uint64_t NumBytes = 0;
941 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
942 TargetFrameInfo::StackGrowsUp ?
943 TD->getPointerSize() : -TD->getPointerSize());
946 // Calculate required stack adjustment.
947 uint64_t FrameSize = StackSize - SlotSize;
948 if (needsStackRealignment(MF))
949 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
951 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
953 // Get the offset of the stack slot for the EBP register, which is
954 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
955 // Update the frame offset adjustment.
956 MFI->setOffsetAdjustment(-NumBytes);
958 // Save EBP/RBP into the appropriate stack slot.
959 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
960 .addReg(FramePtr, RegState::Kill);
962 if (needsFrameMoves) {
963 // Mark the place where EBP/RBP was saved.
964 unsigned FrameLabelId = MMI->NextLabelID();
965 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
967 // Define the current CFA rule to use the provided offset.
969 MachineLocation SPDst(MachineLocation::VirtualFP);
970 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
971 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
973 // FIXME: Verify & implement for FP
974 MachineLocation SPDst(StackPtr);
975 MachineLocation SPSrc(StackPtr, stackGrowth);
976 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
979 // Change the rule for the FramePtr to be an "offset" rule.
980 MachineLocation FPDst(MachineLocation::VirtualFP,
982 MachineLocation FPSrc(FramePtr);
983 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
986 // Update EBP with the new base value...
987 BuildMI(MBB, MBBI, DL,
988 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
991 if (needsFrameMoves) {
992 // Mark effective beginning of when frame pointer becomes valid.
993 unsigned FrameLabelId = MMI->NextLabelID();
994 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
996 // Define the current CFA to use the EBP/RBP register.
997 MachineLocation FPDst(FramePtr);
998 MachineLocation FPSrc(MachineLocation::VirtualFP);
999 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
1002 // Mark the FramePtr as live-in in every block except the entry.
1003 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
1005 I->addLiveIn(FramePtr);
1008 if (needsStackRealignment(MF)) {
1010 BuildMI(MBB, MBBI, DL,
1011 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1012 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1014 // The EFLAGS implicit def is dead.
1015 MI->getOperand(3).setIsDead();
1018 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1021 // Skip the callee-saved push instructions.
1022 bool PushedRegs = false;
1023 int StackOffset = 2 * stackGrowth;
1025 while (MBBI != MBB.end() &&
1026 (MBBI->getOpcode() == X86::PUSH32r ||
1027 MBBI->getOpcode() == X86::PUSH64r)) {
1031 if (!HasFP && needsFrameMoves) {
1032 // Mark callee-saved push instruction.
1033 unsigned LabelId = MMI->NextLabelID();
1034 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1036 // Define the current CFA rule to use the provided offset.
1037 unsigned Ptr = StackSize ?
1038 MachineLocation::VirtualFP : StackPtr;
1039 MachineLocation SPDst(Ptr);
1040 MachineLocation SPSrc(Ptr, StackOffset);
1041 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1042 StackOffset += stackGrowth;
1046 if (MBBI != MBB.end())
1047 DL = MBBI->getDebugLoc();
1049 // Adjust stack pointer: ESP -= numbytes.
1050 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1051 // Check, whether EAX is livein for this function.
1052 bool isEAXAlive = false;
1053 for (MachineRegisterInfo::livein_iterator
1054 II = MF.getRegInfo().livein_begin(),
1055 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1056 unsigned Reg = II->first;
1057 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1058 Reg == X86::AH || Reg == X86::AL);
1061 // Function prologue calls _alloca to probe the stack when allocating more
1062 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1063 // to ensure that the guard pages used by the OS virtual memory manager are
1064 // allocated in correct sequence.
1066 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1068 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1069 .addExternalSymbol("_alloca");
1072 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1073 .addReg(X86::EAX, RegState::Kill);
1075 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1076 // allocated bytes for EAX.
1077 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1078 .addImm(NumBytes - 4);
1079 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1080 .addExternalSymbol("_alloca");
1083 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1085 StackPtr, false, NumBytes - 4);
1086 MBB.insert(MBBI, MI);
1088 } else if (NumBytes) {
1089 // If there is an SUB32ri of ESP immediately before this instruction, merge
1090 // the two. This can be the case when tail call elimination is enabled and
1091 // the callee has more arguments then the caller.
1092 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1094 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1095 // instruction, merge the two instructions.
1096 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1099 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1102 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1103 // Mark end of stack pointer adjustment.
1104 unsigned LabelId = MMI->NextLabelID();
1105 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1107 if (!HasFP && NumBytes) {
1108 // Define the current CFA rule to use the provided offset.
1110 MachineLocation SPDst(MachineLocation::VirtualFP);
1111 MachineLocation SPSrc(MachineLocation::VirtualFP,
1112 -StackSize + stackGrowth);
1113 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1115 // FIXME: Verify & implement for FP
1116 MachineLocation SPDst(StackPtr);
1117 MachineLocation SPSrc(StackPtr, stackGrowth);
1118 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1122 // Emit DWARF info specifying the offsets of the callee-saved registers.
1124 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1128 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1129 MachineBasicBlock &MBB) const {
1130 const MachineFrameInfo *MFI = MF.getFrameInfo();
1131 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1132 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1133 unsigned RetOpcode = MBBI->getOpcode();
1134 DebugLoc DL = MBBI->getDebugLoc();
1136 switch (RetOpcode) {
1138 llvm_unreachable("Can only insert epilog into returning blocks");
1141 case X86::TCRETURNdi:
1142 case X86::TCRETURNri:
1143 case X86::TCRETURNri64:
1144 case X86::TCRETURNdi64:
1145 case X86::EH_RETURN:
1146 case X86::EH_RETURN64:
1150 break; // These are ok
1153 // Get the number of bytes to allocate from the FrameInfo.
1154 uint64_t StackSize = MFI->getStackSize();
1155 uint64_t MaxAlign = MFI->getMaxAlignment();
1156 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1157 uint64_t NumBytes = 0;
1160 // Calculate required stack adjustment.
1161 uint64_t FrameSize = StackSize - SlotSize;
1162 if (needsStackRealignment(MF))
1163 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1165 NumBytes = FrameSize - CSSize;
1168 BuildMI(MBB, MBBI, DL,
1169 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1171 NumBytes = StackSize - CSSize;
1174 // Skip the callee-saved pop instructions.
1175 MachineBasicBlock::iterator LastCSPop = MBBI;
1176 while (MBBI != MBB.begin()) {
1177 MachineBasicBlock::iterator PI = prior(MBBI);
1178 unsigned Opc = PI->getOpcode();
1180 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1181 !PI->getDesc().isTerminator())
1187 DL = MBBI->getDebugLoc();
1189 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1190 // instruction, merge the two instructions.
1191 if (NumBytes || MFI->hasVarSizedObjects())
1192 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1194 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1195 // slot before popping them off! Same applies for the case, when stack was
1197 if (needsStackRealignment(MF)) {
1198 // We cannot use LEA here, because stack pointer was realigned. We need to
1199 // deallocate local frame back.
1201 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1202 MBBI = prior(LastCSPop);
1205 BuildMI(MBB, MBBI, DL,
1206 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1207 StackPtr).addReg(FramePtr);
1208 } else if (MFI->hasVarSizedObjects()) {
1210 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1212 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1213 FramePtr, false, -CSSize);
1214 MBB.insert(MBBI, MI);
1216 BuildMI(MBB, MBBI, DL,
1217 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1220 } else if (NumBytes) {
1221 // Adjust stack pointer back: ESP += numbytes.
1222 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1225 // We're returning from function via eh_return.
1226 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1227 MBBI = prior(MBB.end());
1228 MachineOperand &DestAddr = MBBI->getOperand(0);
1229 assert(DestAddr.isReg() && "Offset should be in register!");
1230 BuildMI(MBB, MBBI, DL,
1231 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1232 StackPtr).addReg(DestAddr.getReg());
1233 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1234 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1235 // Tail call return: adjust the stack pointer and jump to callee.
1236 MBBI = prior(MBB.end());
1237 MachineOperand &JumpTarget = MBBI->getOperand(0);
1238 MachineOperand &StackAdjust = MBBI->getOperand(1);
1239 assert(StackAdjust.isImm() && "Expecting immediate value.");
1241 // Adjust stack pointer.
1242 int StackAdj = StackAdjust.getImm();
1243 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1245 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1247 // Incoporate the retaddr area.
1248 Offset = StackAdj-MaxTCDelta;
1249 assert(Offset >= 0 && "Offset should never be negative");
1252 // Check for possible merge with preceeding ADD instruction.
1253 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1254 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1257 // Jump to label or value in register.
1258 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1259 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1260 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1261 else if (RetOpcode== X86::TCRETURNri64)
1262 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1264 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1266 // Delete the pseudo instruction TCRETURN.
1268 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1269 (X86FI->getTCReturnAddrDelta() < 0)) {
1270 // Add the return addr area delta back since we are not tail calling.
1271 int delta = -1*X86FI->getTCReturnAddrDelta();
1272 MBBI = prior(MBB.end());
1274 // Check for possible merge with preceeding ADD instruction.
1275 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1276 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1280 unsigned X86RegisterInfo::getRARegister() const {
1281 return Is64Bit ? X86::RIP // Should have dwarf #16.
1282 : X86::EIP; // Should have dwarf #8.
1285 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1286 return hasFP(MF) ? FramePtr : StackPtr;
1290 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1291 // Calculate amount of bytes used for return address storing
1292 int stackGrowth = (Is64Bit ? -8 : -4);
1294 // Initial state of the frame pointer is esp+4.
1295 MachineLocation Dst(MachineLocation::VirtualFP);
1296 MachineLocation Src(StackPtr, stackGrowth);
1297 Moves.push_back(MachineMove(0, Dst, Src));
1299 // Add return address to move list
1300 MachineLocation CSDst(StackPtr, stackGrowth);
1301 MachineLocation CSSrc(getRARegister());
1302 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1305 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1306 llvm_unreachable("What is the exception register");
1310 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1311 llvm_unreachable("What is the exception handler register");
1316 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1317 switch (VT.getSimpleVT().SimpleTy) {
1318 default: return Reg;
1323 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1325 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1327 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1329 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1335 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1337 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1339 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1341 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1343 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1345 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1347 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1349 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1351 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1353 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1355 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1357 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1359 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1361 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1363 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1365 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1371 default: return Reg;
1372 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1374 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1376 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1378 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1380 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1382 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1384 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1386 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1388 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1390 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1392 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1394 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1396 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1398 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1400 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1402 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1407 default: return Reg;
1408 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1410 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1412 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1414 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1416 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1418 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1420 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1422 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1424 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1426 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1428 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1430 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1432 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1434 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1436 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1438 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1443 default: return Reg;
1444 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1446 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1448 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1450 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1452 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1454 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1456 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1458 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1460 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1462 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1464 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1466 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1468 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1470 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1472 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1474 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1483 #include "X86GenRegisterInfo.inc"
1486 struct MSAC : public MachineFunctionPass {
1488 MSAC() : MachineFunctionPass(&ID) {}
1490 virtual bool runOnMachineFunction(MachineFunction &MF) {
1491 MachineFrameInfo *FFI = MF.getFrameInfo();
1492 MachineRegisterInfo &RI = MF.getRegInfo();
1494 // Calculate max stack alignment of all already allocated stack objects.
1495 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1497 // Be over-conservative: scan over all vreg defs and find, whether vector
1498 // registers are used. If yes - there is probability, that vector register
1499 // will be spilled and thus stack needs to be aligned properly.
1500 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1501 RegNum < RI.getLastVirtReg(); ++RegNum)
1502 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1504 if (FFI->getMaxAlignment() == MaxAlign)
1507 FFI->setMaxAlignment(MaxAlign);
1511 virtual const char *getPassName() const {
1512 return "X86 Maximal Stack Alignment Calculator";
1515 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1516 AU.setPreservesCFG();
1517 MachineFunctionPass::getAnalysisUsage(AU);
1525 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }