1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71 /// specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 /// getX86RegNum - This function maps LLVM register identifiers to their X86
94 /// specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass ||
169 A == &X86::GR64_NOSPRegClass ||
170 A == &X86::GR64_NOREX_NOSPRegClass)
171 return &X86::GR64_ABCDRegClass;
172 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173 A == &X86::GR32_NOREXRegClass ||
174 A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177 A == &X86::GR16_NOREXRegClass)
178 return &X86::GR16_ABCDRegClass;
179 } else if (B == &X86::GR8_NOREXRegClass) {
180 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_NOREXRegClass;
183 else if (A == &X86::GR64_ABCDRegClass)
184 return &X86::GR64_ABCDRegClass;
185 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186 A == &X86::GR32_NOSPRegClass)
187 return &X86::GR32_NOREXRegClass;
188 else if (A == &X86::GR32_ABCDRegClass)
189 return &X86::GR32_ABCDRegClass;
190 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191 return &X86::GR16_NOREXRegClass;
192 else if (A == &X86::GR16_ABCDRegClass)
193 return &X86::GR16_ABCDRegClass;
198 if (B == &X86::GR8_ABCD_HRegClass) {
199 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
200 A == &X86::GR64_NOREXRegClass ||
201 A == &X86::GR64_NOSPRegClass ||
202 A == &X86::GR64_NOREX_NOSPRegClass)
203 return &X86::GR64_ABCDRegClass;
204 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
205 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
206 return &X86::GR32_ABCDRegClass;
207 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
208 A == &X86::GR16_NOREXRegClass)
209 return &X86::GR16_ABCDRegClass;
214 if (B == &X86::GR16RegClass) {
215 if (A->getSize() == 4 || A->getSize() == 8)
217 } else if (B == &X86::GR16_ABCDRegClass) {
218 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
219 A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass ||
221 A == &X86::GR64_NOREX_NOSPRegClass)
222 return &X86::GR64_ABCDRegClass;
223 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
224 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
225 return &X86::GR32_ABCDRegClass;
226 } else if (B == &X86::GR16_NOREXRegClass) {
227 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
228 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
229 return &X86::GR64_NOREXRegClass;
230 else if (A == &X86::GR64_ABCDRegClass)
231 return &X86::GR64_ABCDRegClass;
232 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
233 A == &X86::GR32_NOSPRegClass)
234 return &X86::GR32_NOREXRegClass;
235 else if (A == &X86::GR32_ABCDRegClass)
236 return &X86::GR64_ABCDRegClass;
241 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
242 if (A->getSize() == 8)
244 } else if (B == &X86::GR32_ABCDRegClass) {
245 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
246 A == &X86::GR64_NOREXRegClass ||
247 A == &X86::GR64_NOSPRegClass ||
248 A == &X86::GR64_NOREX_NOSPRegClass)
249 return &X86::GR64_ABCDRegClass;
250 } else if (B == &X86::GR32_NOREXRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
252 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
253 return &X86::GR64_NOREXRegClass;
254 else if (A == &X86::GR64_ABCDRegClass)
255 return &X86::GR64_ABCDRegClass;
262 const TargetRegisterClass *
263 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
265 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
266 case 0: // Normal GPRs.
267 if (TM.getSubtarget<X86Subtarget>().is64Bit())
268 return &X86::GR64RegClass;
269 return &X86::GR32RegClass;
270 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
271 if (TM.getSubtarget<X86Subtarget>().is64Bit())
272 return &X86::GR64_NOSPRegClass;
273 return &X86::GR32_NOSPRegClass;
277 const TargetRegisterClass *
278 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
279 if (RC == &X86::CCRRegClass) {
281 return &X86::GR64RegClass;
283 return &X86::GR32RegClass;
289 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
290 bool callsEHReturn = false;
293 const MachineFrameInfo *MFI = MF->getFrameInfo();
294 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
295 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
298 static const unsigned CalleeSavedRegs32Bit[] = {
299 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
302 static const unsigned CalleeSavedRegs32EHRet[] = {
303 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
306 static const unsigned CalleeSavedRegs64Bit[] = {
307 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
310 static const unsigned CalleeSavedRegs64EHRet[] = {
311 X86::RAX, X86::RDX, X86::RBX, X86::R12,
312 X86::R13, X86::R14, X86::R15, X86::RBP, 0
315 static const unsigned CalleeSavedRegsWin64[] = {
316 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
317 X86::R12, X86::R13, X86::R14, X86::R15,
318 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
319 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
320 X86::XMM14, X86::XMM15, 0
325 return CalleeSavedRegsWin64;
327 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
329 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
333 const TargetRegisterClass* const*
334 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
335 bool callsEHReturn = false;
338 const MachineFrameInfo *MFI = MF->getFrameInfo();
339 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
340 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
343 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
344 &X86::GR32RegClass, &X86::GR32RegClass,
345 &X86::GR32RegClass, &X86::GR32RegClass, 0
347 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
348 &X86::GR32RegClass, &X86::GR32RegClass,
349 &X86::GR32RegClass, &X86::GR32RegClass,
350 &X86::GR32RegClass, &X86::GR32RegClass, 0
352 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
353 &X86::GR64RegClass, &X86::GR64RegClass,
354 &X86::GR64RegClass, &X86::GR64RegClass,
355 &X86::GR64RegClass, &X86::GR64RegClass, 0
357 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
358 &X86::GR64RegClass, &X86::GR64RegClass,
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass, 0
363 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
364 &X86::GR64RegClass, &X86::GR64RegClass,
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass,
368 &X86::VR128RegClass, &X86::VR128RegClass,
369 &X86::VR128RegClass, &X86::VR128RegClass,
370 &X86::VR128RegClass, &X86::VR128RegClass,
371 &X86::VR128RegClass, &X86::VR128RegClass,
372 &X86::VR128RegClass, &X86::VR128RegClass, 0
377 return CalleeSavedRegClassesWin64;
379 return (callsEHReturn ?
380 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
382 return (callsEHReturn ?
383 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
387 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
388 BitVector Reserved(getNumRegs());
389 // Set the stack-pointer register and its aliases as reserved.
390 Reserved.set(X86::RSP);
391 Reserved.set(X86::ESP);
392 Reserved.set(X86::SP);
393 Reserved.set(X86::SPL);
395 // Set the frame-pointer register and its aliases as reserved if needed.
397 Reserved.set(X86::RBP);
398 Reserved.set(X86::EBP);
399 Reserved.set(X86::BP);
400 Reserved.set(X86::BPL);
403 // Mark the x87 stack registers as reserved, since they don't behave normally
404 // with respect to liveness. We don't fully model the effects of x87 stack
405 // pushes and pops after stackification.
406 Reserved.set(X86::ST0);
407 Reserved.set(X86::ST1);
408 Reserved.set(X86::ST2);
409 Reserved.set(X86::ST3);
410 Reserved.set(X86::ST4);
411 Reserved.set(X86::ST5);
412 Reserved.set(X86::ST6);
413 Reserved.set(X86::ST7);
417 //===----------------------------------------------------------------------===//
418 // Stack Frame Processing methods
419 //===----------------------------------------------------------------------===//
421 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
422 unsigned MaxAlign = 0;
424 for (int i = FFI->getObjectIndexBegin(),
425 e = FFI->getObjectIndexEnd(); i != e; ++i) {
426 if (FFI->isDeadObjectIndex(i))
429 unsigned Align = FFI->getObjectAlignment(i);
430 MaxAlign = std::max(MaxAlign, Align);
436 /// hasFP - Return true if the specified function should have a dedicated frame
437 /// pointer register. This is true if the function has variable sized allocas
438 /// or if frame pointer elimination is disabled.
439 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
440 const MachineFrameInfo *MFI = MF.getFrameInfo();
441 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
443 return (NoFramePointerElim ||
444 needsStackRealignment(MF) ||
445 MFI->hasVarSizedObjects() ||
446 MFI->isFrameAddressTaken() ||
447 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
448 (MMI && MMI->callsUnwindInit()));
451 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
452 const MachineFrameInfo *MFI = MF.getFrameInfo();
453 bool requiresRealignment =
454 RealignStack && (MFI->getMaxAlignment() > StackAlign);
456 // FIXME: Currently we don't support stack realignment for functions with
457 // variable-sized allocas
458 if (requiresRealignment && MFI->hasVarSizedObjects())
460 "Stack realignment in presense of dynamic allocas is not supported");
462 return requiresRealignment;
465 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
466 return !MF.getFrameInfo()->hasVarSizedObjects();
469 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
470 int &FrameIdx) const {
471 if (Reg == FramePtr && hasFP(MF)) {
472 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
479 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
480 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
481 MachineFrameInfo *MFI = MF.getFrameInfo();
482 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
483 uint64_t StackSize = MFI->getStackSize();
485 if (needsStackRealignment(MF)) {
487 // Skip the saved EBP.
490 unsigned Align = MFI->getObjectAlignment(FI);
491 assert( (-(Offset + StackSize)) % Align == 0);
493 return Offset + StackSize;
495 // FIXME: Support tail calls
498 return Offset + StackSize;
500 // Skip the saved EBP.
503 // Skip the RETADDR move area
504 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
505 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
506 if (TailCallReturnAddrDelta < 0)
507 Offset -= TailCallReturnAddrDelta;
513 void X86RegisterInfo::
514 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator I) const {
516 if (!hasReservedCallFrame(MF)) {
517 // If the stack pointer can be changed after prologue, turn the
518 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
519 // adjcallstackdown instruction into 'add ESP, <amt>'
520 // TODO: consider using push / pop instead of sub + store / add
521 MachineInstr *Old = I;
522 uint64_t Amount = Old->getOperand(0).getImm();
524 // We need to keep the stack aligned properly. To do this, we round the
525 // amount of space needed for the outgoing arguments up to the next
526 // alignment boundary.
527 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
529 MachineInstr *New = 0;
530 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
531 New = BuildMI(MF, Old->getDebugLoc(),
532 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
537 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
539 // Factor out the amount the callee already popped.
540 uint64_t CalleeAmt = Old->getOperand(1).getImm();
544 unsigned Opc = (Amount < 128) ?
545 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
546 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
547 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
554 // The EFLAGS implicit def is dead.
555 New->getOperand(3).setIsDead();
557 // Replace the pseudo instruction with a new instruction.
561 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
562 // If we are performing frame pointer elimination and if the callee pops
563 // something off the stack pointer, add it back. We do this until we have
564 // more advanced stack pointer tracking ability.
565 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
566 unsigned Opc = (CalleeAmt < 128) ?
567 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
568 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
569 MachineInstr *Old = I;
571 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
576 // The EFLAGS implicit def is dead.
577 New->getOperand(3).setIsDead();
586 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
587 int SPAdj, int *Value,
588 RegScavenger *RS) const{
589 assert(SPAdj == 0 && "Unexpected");
592 MachineInstr &MI = *II;
593 MachineFunction &MF = *MI.getParent()->getParent();
595 while (!MI.getOperand(i).isFI()) {
597 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
600 int FrameIndex = MI.getOperand(i).getIndex();
603 if (needsStackRealignment(MF))
604 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
606 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
608 // This must be part of a four operand memory reference. Replace the
609 // FrameIndex with base register with EBP. Add an offset to the offset.
610 MI.getOperand(i).ChangeToRegister(BasePtr, false);
612 // Now add the frame object offset to the offset from EBP.
613 if (MI.getOperand(i+3).isImm()) {
614 // Offset is a 32-bit integer.
615 int Offset = getFrameIndexOffset(MF, FrameIndex) +
616 (int)(MI.getOperand(i + 3).getImm());
618 MI.getOperand(i + 3).ChangeToImmediate(Offset);
620 // Offset is symbolic. This is extremely rare.
621 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
622 (uint64_t)MI.getOperand(i+3).getOffset();
623 MI.getOperand(i+3).setOffset(Offset);
629 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
630 RegScavenger *RS) const {
631 MachineFrameInfo *MFI = MF.getFrameInfo();
633 // Calculate and set max stack object alignment early, so we can decide
634 // whether we will need stack realignment (and thus FP).
635 unsigned MaxAlign = std::max(MFI->getMaxAlignment(),
636 calculateMaxStackAlignment(MFI));
638 MFI->setMaxAlignment(MaxAlign);
640 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
641 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
643 if (TailCallReturnAddrDelta < 0) {
644 // create RETURNADDR area
653 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
654 (-1U*SlotSize)+TailCallReturnAddrDelta,
659 assert((TailCallReturnAddrDelta <= 0) &&
660 "The Delta should always be zero or negative");
661 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
663 // Create a frame entry for the EBP register that must be saved.
664 int FrameIdx = MFI->CreateFixedObject(SlotSize,
666 TFI.getOffsetOfLocalArea() +
667 TailCallReturnAddrDelta,
669 assert(FrameIdx == MFI->getObjectIndexBegin() &&
670 "Slot for EBP register must be last in order to be found!");
675 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
676 /// stack pointer by a constant value.
678 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
679 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
680 const TargetInstrInfo &TII) {
681 bool isSub = NumBytes < 0;
682 uint64_t Offset = isSub ? -NumBytes : NumBytes;
685 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
686 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
688 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
689 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
690 uint64_t Chunk = (1LL << 31) - 1;
691 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
692 DebugLoc::getUnknownLoc());
695 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
697 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
700 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
705 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
707 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
708 unsigned StackPtr, uint64_t *NumBytes = NULL) {
709 if (MBBI == MBB.begin()) return;
711 MachineBasicBlock::iterator PI = prior(MBBI);
712 unsigned Opc = PI->getOpcode();
713 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
714 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
715 PI->getOperand(0).getReg() == StackPtr) {
717 *NumBytes += PI->getOperand(2).getImm();
719 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
720 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
721 PI->getOperand(0).getReg() == StackPtr) {
723 *NumBytes -= PI->getOperand(2).getImm();
728 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
730 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
731 MachineBasicBlock::iterator &MBBI,
732 unsigned StackPtr, uint64_t *NumBytes = NULL) {
733 // FIXME: THIS ISN'T RUN!!!
736 if (MBBI == MBB.end()) return;
738 MachineBasicBlock::iterator NI = next(MBBI);
739 if (NI == MBB.end()) return;
741 unsigned Opc = NI->getOpcode();
742 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
743 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
744 NI->getOperand(0).getReg() == StackPtr) {
746 *NumBytes -= NI->getOperand(2).getImm();
749 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
750 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
751 NI->getOperand(0).getReg() == StackPtr) {
753 *NumBytes += NI->getOperand(2).getImm();
759 /// mergeSPUpdates - Checks the instruction before/after the passed
760 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
761 /// stack adjustment is returned as a positive value for ADD and a negative for
763 static int mergeSPUpdates(MachineBasicBlock &MBB,
764 MachineBasicBlock::iterator &MBBI,
766 bool doMergeWithPrevious) {
767 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
768 (!doMergeWithPrevious && MBBI == MBB.end()))
771 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
772 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
773 unsigned Opc = PI->getOpcode();
776 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
777 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
778 PI->getOperand(0).getReg() == StackPtr){
779 Offset += PI->getOperand(2).getImm();
781 if (!doMergeWithPrevious) MBBI = NI;
782 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
783 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
784 PI->getOperand(0).getReg() == StackPtr) {
785 Offset -= PI->getOperand(2).getImm();
787 if (!doMergeWithPrevious) MBBI = NI;
793 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
795 unsigned FramePtr) const {
796 MachineFrameInfo *MFI = MF.getFrameInfo();
797 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
800 // Add callee saved registers to move list.
801 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
802 if (CSI.empty()) return;
804 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
805 const TargetData *TD = MF.getTarget().getTargetData();
806 bool HasFP = hasFP(MF);
808 // Calculate amount of bytes used for return address storing.
810 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
811 TargetFrameInfo::StackGrowsUp ?
812 TD->getPointerSize() : -TD->getPointerSize());
814 // FIXME: This is dirty hack. The code itself is pretty mess right now.
815 // It should be rewritten from scratch and generalized sometimes.
817 // Determine maximum offset (minumum due to stack growth).
818 int64_t MaxOffset = 0;
819 for (std::vector<CalleeSavedInfo>::const_iterator
820 I = CSI.begin(), E = CSI.end(); I != E; ++I)
821 MaxOffset = std::min(MaxOffset,
822 MFI->getObjectOffset(I->getFrameIdx()));
824 // Calculate offsets.
825 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
826 for (std::vector<CalleeSavedInfo>::const_iterator
827 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
828 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
829 unsigned Reg = I->getReg();
830 Offset = MaxOffset - Offset + saveAreaOffset;
832 // Don't output a new machine move if we're re-saving the frame
833 // pointer. This happens when the PrologEpilogInserter has inserted an extra
834 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
835 // generates one when frame pointers are used. If we generate a "machine
836 // move" for this extra "PUSH", the linker will lose track of the fact that
837 // the frame pointer should have the value of the first "PUSH" when it's
840 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
841 // another bug. I.e., one where we generate a prolog like this:
849 // The immediate re-push of EBP is unnecessary. At the least, it's an
850 // optimization bug. EBP can be used as a scratch register in certain
851 // cases, but probably not when we have a frame pointer.
852 if (HasFP && FramePtr == Reg)
855 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
856 MachineLocation CSSrc(Reg);
857 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
861 /// emitPrologue - Push callee-saved registers onto the stack, which
862 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
863 /// space for local variables. Also emit labels used by the exception handler to
864 /// generate the exception handling frames.
865 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
866 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
867 MachineBasicBlock::iterator MBBI = MBB.begin();
868 MachineFrameInfo *MFI = MF.getFrameInfo();
869 const Function *Fn = MF.getFunction();
870 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
871 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
872 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
873 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
874 !Fn->doesNotThrow() || UnwindTablesMandatory;
875 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
876 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
877 bool HasFP = hasFP(MF);
880 // Add RETADDR move area to callee saved frame size.
881 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
882 if (TailCallReturnAddrDelta < 0)
883 X86FI->setCalleeSavedFrameSize(
884 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
886 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
887 // function, and use up to 128 bytes of stack space, don't have a frame
888 // pointer, calls, or dynamic alloca then we do not need to adjust the
889 // stack pointer (we fit in the Red Zone).
890 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
891 !needsStackRealignment(MF) &&
892 !MFI->hasVarSizedObjects() && // No dynamic alloca.
893 !MFI->hasCalls() && // No calls.
894 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
895 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
896 if (HasFP) MinSize += SlotSize;
897 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
898 MFI->setStackSize(StackSize);
899 } else if (Subtarget->isTargetWin64()) {
900 // We need to always allocate 32 bytes as register spill area.
901 // FIXME: We might reuse these 32 bytes for leaf functions.
903 MFI->setStackSize(StackSize);
906 // Insert stack pointer adjustment for later moving of return addr. Only
907 // applies to tail call optimized functions where the callee argument stack
908 // size is bigger than the callers.
909 if (TailCallReturnAddrDelta < 0) {
911 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
914 .addImm(-TailCallReturnAddrDelta);
915 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
918 // Mapping for machine moves:
920 // DST: VirtualFP AND
921 // SRC: VirtualFP => DW_CFA_def_cfa_offset
922 // ELSE => DW_CFA_def_cfa
924 // SRC: VirtualFP AND
925 // DST: Register => DW_CFA_def_cfa_register
928 // OFFSET < 0 => DW_CFA_offset_extended_sf
929 // REG < 64 => DW_CFA_offset + Reg
930 // ELSE => DW_CFA_offset_extended
932 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
933 const TargetData *TD = MF.getTarget().getTargetData();
934 uint64_t NumBytes = 0;
936 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
937 TargetFrameInfo::StackGrowsUp ?
938 TD->getPointerSize() : -TD->getPointerSize());
941 // Calculate required stack adjustment.
942 uint64_t FrameSize = StackSize - SlotSize;
943 if (needsStackRealignment(MF))
944 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
946 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
948 // Get the offset of the stack slot for the EBP register, which is
949 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
950 // Update the frame offset adjustment.
951 MFI->setOffsetAdjustment(-NumBytes);
953 // Save EBP/RBP into the appropriate stack slot.
954 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
955 .addReg(FramePtr, RegState::Kill);
957 if (needsFrameMoves) {
958 // Mark the place where EBP/RBP was saved.
959 unsigned FrameLabelId = MMI->NextLabelID();
960 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
962 // Define the current CFA rule to use the provided offset.
964 MachineLocation SPDst(MachineLocation::VirtualFP);
965 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
966 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
968 // FIXME: Verify & implement for FP
969 MachineLocation SPDst(StackPtr);
970 MachineLocation SPSrc(StackPtr, stackGrowth);
971 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
974 // Change the rule for the FramePtr to be an "offset" rule.
975 MachineLocation FPDst(MachineLocation::VirtualFP,
977 MachineLocation FPSrc(FramePtr);
978 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
981 // Update EBP with the new base value...
982 BuildMI(MBB, MBBI, DL,
983 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
986 if (needsFrameMoves) {
987 // Mark effective beginning of when frame pointer becomes valid.
988 unsigned FrameLabelId = MMI->NextLabelID();
989 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
991 // Define the current CFA to use the EBP/RBP register.
992 MachineLocation FPDst(FramePtr);
993 MachineLocation FPSrc(MachineLocation::VirtualFP);
994 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
997 // Mark the FramePtr as live-in in every block except the entry.
998 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
1000 I->addLiveIn(FramePtr);
1003 if (needsStackRealignment(MF)) {
1005 BuildMI(MBB, MBBI, DL,
1006 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1007 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1009 // The EFLAGS implicit def is dead.
1010 MI->getOperand(3).setIsDead();
1013 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1016 // Skip the callee-saved push instructions.
1017 bool PushedRegs = false;
1018 int StackOffset = 2 * stackGrowth;
1020 while (MBBI != MBB.end() &&
1021 (MBBI->getOpcode() == X86::PUSH32r ||
1022 MBBI->getOpcode() == X86::PUSH64r)) {
1026 if (!HasFP && needsFrameMoves) {
1027 // Mark callee-saved push instruction.
1028 unsigned LabelId = MMI->NextLabelID();
1029 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1031 // Define the current CFA rule to use the provided offset.
1032 unsigned Ptr = StackSize ?
1033 MachineLocation::VirtualFP : StackPtr;
1034 MachineLocation SPDst(Ptr);
1035 MachineLocation SPSrc(Ptr, StackOffset);
1036 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1037 StackOffset += stackGrowth;
1041 if (MBBI != MBB.end())
1042 DL = MBBI->getDebugLoc();
1044 // Adjust stack pointer: ESP -= numbytes.
1045 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1046 // Check, whether EAX is livein for this function.
1047 bool isEAXAlive = false;
1048 for (MachineRegisterInfo::livein_iterator
1049 II = MF.getRegInfo().livein_begin(),
1050 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1051 unsigned Reg = II->first;
1052 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1053 Reg == X86::AH || Reg == X86::AL);
1056 // Function prologue calls _alloca to probe the stack when allocating more
1057 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1058 // to ensure that the guard pages used by the OS virtual memory manager are
1059 // allocated in correct sequence.
1061 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1063 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1064 .addExternalSymbol("_alloca");
1067 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1068 .addReg(X86::EAX, RegState::Kill);
1070 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1071 // allocated bytes for EAX.
1072 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1073 .addImm(NumBytes - 4);
1074 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1075 .addExternalSymbol("_alloca");
1078 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1080 StackPtr, false, NumBytes - 4);
1081 MBB.insert(MBBI, MI);
1083 } else if (NumBytes) {
1084 // If there is an SUB32ri of ESP immediately before this instruction, merge
1085 // the two. This can be the case when tail call elimination is enabled and
1086 // the callee has more arguments then the caller.
1087 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1089 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1090 // instruction, merge the two instructions.
1091 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1094 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1097 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1098 // Mark end of stack pointer adjustment.
1099 unsigned LabelId = MMI->NextLabelID();
1100 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1102 if (!HasFP && NumBytes) {
1103 // Define the current CFA rule to use the provided offset.
1105 MachineLocation SPDst(MachineLocation::VirtualFP);
1106 MachineLocation SPSrc(MachineLocation::VirtualFP,
1107 -StackSize + stackGrowth);
1108 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1110 // FIXME: Verify & implement for FP
1111 MachineLocation SPDst(StackPtr);
1112 MachineLocation SPSrc(StackPtr, stackGrowth);
1113 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1117 // Emit DWARF info specifying the offsets of the callee-saved registers.
1119 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1123 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1124 MachineBasicBlock &MBB) const {
1125 const MachineFrameInfo *MFI = MF.getFrameInfo();
1126 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1127 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1128 unsigned RetOpcode = MBBI->getOpcode();
1129 DebugLoc DL = MBBI->getDebugLoc();
1131 switch (RetOpcode) {
1133 llvm_unreachable("Can only insert epilog into returning blocks");
1136 case X86::TCRETURNdi:
1137 case X86::TCRETURNri:
1138 case X86::TCRETURNri64:
1139 case X86::TCRETURNdi64:
1140 case X86::EH_RETURN:
1141 case X86::EH_RETURN64:
1145 break; // These are ok
1148 // Get the number of bytes to allocate from the FrameInfo.
1149 uint64_t StackSize = MFI->getStackSize();
1150 uint64_t MaxAlign = MFI->getMaxAlignment();
1151 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1152 uint64_t NumBytes = 0;
1155 // Calculate required stack adjustment.
1156 uint64_t FrameSize = StackSize - SlotSize;
1157 if (needsStackRealignment(MF))
1158 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1160 NumBytes = FrameSize - CSSize;
1163 BuildMI(MBB, MBBI, DL,
1164 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1166 NumBytes = StackSize - CSSize;
1169 // Skip the callee-saved pop instructions.
1170 MachineBasicBlock::iterator LastCSPop = MBBI;
1171 while (MBBI != MBB.begin()) {
1172 MachineBasicBlock::iterator PI = prior(MBBI);
1173 unsigned Opc = PI->getOpcode();
1175 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1176 !PI->getDesc().isTerminator())
1182 DL = MBBI->getDebugLoc();
1184 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1185 // instruction, merge the two instructions.
1186 if (NumBytes || MFI->hasVarSizedObjects())
1187 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1189 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1190 // slot before popping them off! Same applies for the case, when stack was
1192 if (needsStackRealignment(MF)) {
1193 // We cannot use LEA here, because stack pointer was realigned. We need to
1194 // deallocate local frame back.
1196 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1197 MBBI = prior(LastCSPop);
1200 BuildMI(MBB, MBBI, DL,
1201 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1202 StackPtr).addReg(FramePtr);
1203 } else if (MFI->hasVarSizedObjects()) {
1205 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1207 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1208 FramePtr, false, -CSSize);
1209 MBB.insert(MBBI, MI);
1211 BuildMI(MBB, MBBI, DL,
1212 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1215 } else if (NumBytes) {
1216 // Adjust stack pointer back: ESP += numbytes.
1217 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1220 // We're returning from function via eh_return.
1221 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1222 MBBI = prior(MBB.end());
1223 MachineOperand &DestAddr = MBBI->getOperand(0);
1224 assert(DestAddr.isReg() && "Offset should be in register!");
1225 BuildMI(MBB, MBBI, DL,
1226 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1227 StackPtr).addReg(DestAddr.getReg());
1228 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1229 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1230 // Tail call return: adjust the stack pointer and jump to callee.
1231 MBBI = prior(MBB.end());
1232 MachineOperand &JumpTarget = MBBI->getOperand(0);
1233 MachineOperand &StackAdjust = MBBI->getOperand(1);
1234 assert(StackAdjust.isImm() && "Expecting immediate value.");
1236 // Adjust stack pointer.
1237 int StackAdj = StackAdjust.getImm();
1238 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1240 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1242 // Incoporate the retaddr area.
1243 Offset = StackAdj-MaxTCDelta;
1244 assert(Offset >= 0 && "Offset should never be negative");
1247 // Check for possible merge with preceeding ADD instruction.
1248 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1249 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1252 // Jump to label or value in register.
1253 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1254 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1255 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1256 else if (RetOpcode== X86::TCRETURNri64)
1257 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1259 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1261 // Delete the pseudo instruction TCRETURN.
1263 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1264 (X86FI->getTCReturnAddrDelta() < 0)) {
1265 // Add the return addr area delta back since we are not tail calling.
1266 int delta = -1*X86FI->getTCReturnAddrDelta();
1267 MBBI = prior(MBB.end());
1269 // Check for possible merge with preceeding ADD instruction.
1270 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1271 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1275 unsigned X86RegisterInfo::getRARegister() const {
1276 return Is64Bit ? X86::RIP // Should have dwarf #16.
1277 : X86::EIP; // Should have dwarf #8.
1280 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1281 return hasFP(MF) ? FramePtr : StackPtr;
1285 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1286 // Calculate amount of bytes used for return address storing
1287 int stackGrowth = (Is64Bit ? -8 : -4);
1289 // Initial state of the frame pointer is esp+4.
1290 MachineLocation Dst(MachineLocation::VirtualFP);
1291 MachineLocation Src(StackPtr, stackGrowth);
1292 Moves.push_back(MachineMove(0, Dst, Src));
1294 // Add return address to move list
1295 MachineLocation CSDst(StackPtr, stackGrowth);
1296 MachineLocation CSSrc(getRARegister());
1297 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1300 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1301 llvm_unreachable("What is the exception register");
1305 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1306 llvm_unreachable("What is the exception handler register");
1311 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1312 switch (VT.getSimpleVT().SimpleTy) {
1313 default: return Reg;
1318 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1320 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1322 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1324 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1330 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1332 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1334 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1336 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1338 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1340 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1342 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1344 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1346 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1348 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1350 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1352 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1354 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1356 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1358 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1360 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1366 default: return Reg;
1367 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1369 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1371 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1373 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1375 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1377 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1379 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1381 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1383 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1385 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1387 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1389 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1391 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1393 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1395 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1397 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1402 default: return Reg;
1403 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1405 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1407 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1409 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1411 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1413 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1415 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1417 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1419 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1421 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1423 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1425 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1427 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1429 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1431 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1433 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1438 default: return Reg;
1439 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1441 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1443 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1445 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1447 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1449 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1451 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1453 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1455 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1457 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1459 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1461 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1463 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1465 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1467 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1469 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1478 #include "X86GenRegisterInfo.inc"
1481 struct MSAC : public MachineFunctionPass {
1483 MSAC() : MachineFunctionPass(&ID) {}
1485 virtual bool runOnMachineFunction(MachineFunction &MF) {
1486 MachineFrameInfo *FFI = MF.getFrameInfo();
1487 MachineRegisterInfo &RI = MF.getRegInfo();
1489 // Calculate max stack alignment of all already allocated stack objects.
1490 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1492 // Be over-conservative: scan over all vreg defs and find, whether vector
1493 // registers are used. If yes - there is probability, that vector register
1494 // will be spilled and thus stack needs to be aligned properly.
1495 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1496 RegNum < RI.getLastVirtReg(); ++RegNum)
1497 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1499 if (FFI->getMaxAlignment() == MaxAlign)
1502 FFI->setMaxAlignment(MaxAlign);
1506 virtual const char *getPassName() const {
1507 return "X86 Maximal Stack Alignment Calculator";
1510 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1511 AU.setPreservesCFG();
1512 MachineFunctionPass::getAnalysisUsage(AU);
1520 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }