1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "Support/CommandLine.h"
27 #include "Support/STLExtras.h"
32 NoFPElim("disable-fp-elim",
33 cl::desc("Disable frame pointer elimination optimization"));
35 NoFusing("disable-spill-fusing",
36 cl::desc("Disable fusing of spill code into instructions"));
38 PrintFailedFusing("print-failed-fuse-candidates",
39 cl::desc("Print instructions that the allocator wants to"
40 " fuse, but the X86 backend currently can't"),
44 X86RegisterInfo::X86RegisterInfo()
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
47 static unsigned getIdx(const TargetRegisterClass *RC) {
48 switch (RC->getSize()) {
49 default: assert(0 && "Invalid data size!");
57 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MI,
59 unsigned SrcReg, int FrameIdx,
60 const TargetRegisterClass *RC) const {
61 static const unsigned Opcode[] =
62 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FSTPr80 };
63 MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
64 FrameIdx).addReg(SrcReg);
69 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned DestReg, int FrameIdx,
72 const TargetRegisterClass *RC) const{
73 static const unsigned Opcode[] =
74 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FLDr80 };
75 unsigned OC = Opcode[getIdx(RC)];
76 MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
80 int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned DestReg, unsigned SrcReg,
83 const TargetRegisterClass *RC) const {
84 static const unsigned Opcode[] =
85 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
86 MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
90 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
92 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
93 .addReg(MI->getOperand(1).getReg());
96 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
98 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
99 .addZImm(MI->getOperand(1).getImmedValue());
102 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
104 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
108 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
110 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
111 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
115 bool X86RegisterInfo::foldMemoryOperand(MachineBasicBlock::iterator &MI,
116 unsigned i, int FrameIndex) const {
117 if (NoFusing) return false;
119 /// FIXME: This should obviously be autogenerated by tablegen when patterns
121 MachineBasicBlock& MBB = *MI->getParent();
122 MachineInstr* NI = 0;
124 switch(MI->getOpcode()) {
125 case X86::MOVrr8: NI = MakeMRInst(X86::MOVmr8 , FrameIndex, MI); break;
126 case X86::MOVrr16: NI = MakeMRInst(X86::MOVmr16, FrameIndex, MI); break;
127 case X86::MOVrr32: NI = MakeMRInst(X86::MOVmr32, FrameIndex, MI); break;
128 case X86::MOVri8: NI = MakeMIInst(X86::MOVmi8 , FrameIndex, MI); break;
129 case X86::MOVri16: NI = MakeMIInst(X86::MOVmi16, FrameIndex, MI); break;
130 case X86::MOVri32: NI = MakeMIInst(X86::MOVmi32, FrameIndex, MI); break;
131 case X86::ADDrr8: NI = MakeMRInst(X86::ADDmr8 , FrameIndex, MI); break;
132 case X86::ADDrr16: NI = MakeMRInst(X86::ADDmr16, FrameIndex, MI); break;
133 case X86::ADDrr32: NI = MakeMRInst(X86::ADDmr32, FrameIndex, MI); break;
134 case X86::ADCrr32: NI = MakeMRInst(X86::ADCmr32, FrameIndex, MI); break;
135 case X86::ADDri8: NI = MakeMIInst(X86::ADDmi8 , FrameIndex, MI); break;
136 case X86::ADDri16: NI = MakeMIInst(X86::ADDmi16, FrameIndex, MI); break;
137 case X86::ADDri32: NI = MakeMIInst(X86::ADDmi32, FrameIndex, MI); break;
138 case X86::SUBrr8: NI = MakeMRInst(X86::SUBmr8 , FrameIndex, MI); break;
139 case X86::SUBrr16: NI = MakeMRInst(X86::SUBmr16, FrameIndex, MI); break;
140 case X86::SUBrr32: NI = MakeMRInst(X86::SUBmr32, FrameIndex, MI); break;
141 case X86::SBBrr32: NI = MakeMRInst(X86::SBBmr32, FrameIndex, MI); break;
142 case X86::SUBri8: NI = MakeMIInst(X86::SUBmi8 , FrameIndex, MI); break;
143 case X86::SUBri16: NI = MakeMIInst(X86::SUBmi16, FrameIndex, MI); break;
144 case X86::SUBri32: NI = MakeMIInst(X86::SUBmi32, FrameIndex, MI); break;
145 case X86::ANDrr8: NI = MakeMRInst(X86::ANDmr8 , FrameIndex, MI); break;
146 case X86::ANDrr16: NI = MakeMRInst(X86::ANDmr16, FrameIndex, MI); break;
147 case X86::ANDrr32: NI = MakeMRInst(X86::ANDmr32, FrameIndex, MI); break;
148 case X86::ANDri8: NI = MakeMIInst(X86::ANDmi8 , FrameIndex, MI); break;
149 case X86::ANDri16: NI = MakeMIInst(X86::ANDmi16, FrameIndex, MI); break;
150 case X86::ANDri32: NI = MakeMIInst(X86::ANDmi32, FrameIndex, MI); break;
151 default: break; // Cannot fold
154 switch(MI->getOpcode()) {
155 case X86::MOVrr8: NI = MakeRMInst(X86::MOVrm8 , FrameIndex, MI); break;
156 case X86::MOVrr16: NI = MakeRMInst(X86::MOVrm16, FrameIndex, MI); break;
157 case X86::MOVrr32: NI = MakeRMInst(X86::MOVrm32, FrameIndex, MI); break;
158 case X86::ADDrr8: NI = MakeRMInst(X86::ADDrm8 , FrameIndex, MI); break;
159 case X86::ADDrr16: NI = MakeRMInst(X86::ADDrm16, FrameIndex, MI); break;
160 case X86::ADDrr32: NI = MakeRMInst(X86::ADDrm32, FrameIndex, MI); break;
161 case X86::ADCrr32: NI = MakeRMInst(X86::ADCrm32, FrameIndex, MI); break;
162 case X86::SUBrr8: NI = MakeRMInst(X86::SUBrm8 , FrameIndex, MI); break;
163 case X86::SUBrr16: NI = MakeRMInst(X86::SUBrm16, FrameIndex, MI); break;
164 case X86::SUBrr32: NI = MakeRMInst(X86::SUBrm32, FrameIndex, MI); break;
165 case X86::SBBrr32: NI = MakeRMInst(X86::SBBrm32, FrameIndex, MI); break;
166 case X86::ANDrr8: NI = MakeRMInst(X86::ANDrm8 , FrameIndex, MI); break;
167 case X86::ANDrr16: NI = MakeRMInst(X86::ANDrm16, FrameIndex, MI); break;
168 case X86::ANDrr32: NI = MakeRMInst(X86::ANDrm32, FrameIndex, MI); break;
169 case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break;
170 case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break;
171 case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI);break;
172 case X86::IMULrri32: NI = MakeRMIInst(X86::IMULrmi32, FrameIndex, MI);break;
177 MI = MBB.insert(MBB.erase(MI), NI);
180 if (PrintFailedFusing)
181 std::cerr << "We failed to fuse: " << *MI;
186 //===----------------------------------------------------------------------===//
187 // Stack Frame Processing methods
188 //===----------------------------------------------------------------------===//
190 // hasFP - Return true if the specified function should have a dedicated frame
191 // pointer register. This is true if the function has variable sized allocas or
192 // if frame pointer elimination is disabled.
194 static bool hasFP(MachineFunction &MF) {
195 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
198 void X86RegisterInfo::
199 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
200 MachineBasicBlock::iterator I) const {
202 // If we have a frame pointer, turn the adjcallstackup instruction into a
203 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
205 MachineInstr *Old = I;
206 unsigned Amount = Old->getOperand(0).getImmedValue();
208 // We need to keep the stack aligned properly. To do this, we round the
209 // amount of space needed for the outgoing arguments up to the next
210 // alignment boundary.
211 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
212 Amount = (Amount+Align-1)/Align*Align;
215 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
216 New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
218 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
219 New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
222 // Replace the pseudo instruction with a new instruction...
230 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
231 MachineBasicBlock::iterator II) const {
233 MachineInstr &MI = *II;
234 while (!MI.getOperand(i).isFrameIndex()) {
236 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
239 int FrameIndex = MI.getOperand(i).getFrameIndex();
241 // This must be part of a four operand memory reference. Replace the
242 // FrameIndex with base register with EBP. Add add an offset to the offset.
243 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
245 // Now add the frame object offset to the offset from EBP.
246 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
247 MI.getOperand(i+3).getImmedValue()+4;
250 Offset += MF.getFrameInfo()->getStackSize();
252 Offset += 4; // Skip the saved EBP
254 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
258 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
260 // Create a frame entry for the EBP register that must be saved.
261 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
262 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
263 "Slot for EBP register must be last in order to be found!");
267 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
268 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
269 MachineBasicBlock::iterator MBBI = MBB.begin();
270 MachineFrameInfo *MFI = MF.getFrameInfo();
273 // Get the number of bytes to allocate from the FrameInfo
274 unsigned NumBytes = MFI->getStackSize();
276 // Get the offset of the stack slot for the EBP register... which is
277 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
278 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
280 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
281 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
282 MBB.insert(MBBI, MI);
285 // Save EBP into the appropriate stack slot...
286 MI = addRegOffset(BuildMI(X86::MOVmr32, 5), // mov [ESP-<offset>], EBP
287 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
288 MBB.insert(MBBI, MI);
290 // Update EBP with the new base value...
291 if (NumBytes == 4) // mov EBP, ESP
292 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
293 else // lea EBP, [ESP+StackSize]
294 MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP,NumBytes-4);
296 MBB.insert(MBBI, MI);
299 if (MFI->hasCalls()) {
300 // When we have no frame pointer, we reserve argument space for call sites
301 // in the function immediately on entry to the current function. This
302 // eliminates the need for add/sub ESP brackets around call sites.
304 NumBytes += MFI->getMaxCallFrameSize();
306 // Round the size to a multiple of the alignment (don't forget the 4 byte
308 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
309 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
312 // Update frame info to pretend that this is part of the stack...
313 MFI->setStackSize(NumBytes);
316 // adjust stack pointer: ESP -= numbytes
317 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
318 MBB.insert(MBBI, MI);
323 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
324 MachineBasicBlock &MBB) const {
325 const MachineFrameInfo *MFI = MF.getFrameInfo();
326 MachineBasicBlock::iterator MBBI = prior(MBB.end());
328 assert(MBBI->getOpcode() == X86::RET &&
329 "Can only insert epilog into returning blocks");
332 // Get the offset of the stack slot for the EBP register... which is
333 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
334 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
337 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
338 MBB.insert(MBBI, MI);
341 MI = BuildMI(X86::POPr32, 0, X86::EBP);
342 MBB.insert(MBBI, MI);
344 // Get the number of bytes allocated from the FrameInfo...
345 unsigned NumBytes = MFI->getStackSize();
347 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
348 MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
349 MBB.insert(MBBI, MI);
354 #include "X86GenRegisterInfo.inc"
356 const TargetRegisterClass*
357 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
358 switch (Ty->getPrimitiveID()) {
360 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
361 default: assert(0 && "Invalid type to getClass!");
363 case Type::SByteTyID:
364 case Type::UByteTyID: return &R8Instance;
365 case Type::ShortTyID:
366 case Type::UShortTyID: return &R16Instance;
369 case Type::PointerTyID: return &R32Instance;
371 case Type::FloatTyID:
372 case Type::DoubleTyID: return &RFPInstance;