1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86InstrBuilder.h"
18 #include "llvm/Constants.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "Support/CommandLine.h"
27 #include "Support/STLExtras.h"
32 NoFPElim("disable-fp-elim",
33 cl::desc("Disable frame pointer elimination optimization"));
36 X86RegisterInfo::X86RegisterInfo()
37 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {}
39 static unsigned getIdx(const TargetRegisterClass *RC) {
40 switch (RC->getSize()) {
41 default: assert(0 && "Invalid data size!");
49 int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
50 MachineBasicBlock::iterator MI,
51 unsigned SrcReg, int FrameIdx,
52 const TargetRegisterClass *RC) const {
53 static const unsigned Opcode[] =
54 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
55 MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
56 FrameIdx).addReg(SrcReg);
61 int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
62 MachineBasicBlock::iterator MI,
63 unsigned DestReg, int FrameIdx,
64 const TargetRegisterClass *RC) const{
65 static const unsigned Opcode[] =
66 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
67 unsigned OC = Opcode[getIdx(RC)];
68 MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
72 int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
73 MachineBasicBlock::iterator MI,
74 unsigned DestReg, unsigned SrcReg,
75 const TargetRegisterClass *RC) const {
76 static const unsigned Opcode[] =
77 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
78 MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
82 bool X86RegisterInfo::canFoldMemoryOperand(MachineInstr* MI,
85 switch(MI->getOpcode()) {
86 case X86::ADDrr8: case X86::ADDrr16: case X86::ADDrr32:
87 case X86::ADDri8: case X86::ADDri16: case X86::ADDri32:
88 case X86::ANDrr8: case X86::ANDrr16: case X86::ANDrr32:
89 case X86::ANDri8: case X86::ANDri16: case X86::ANDri32:
90 case X86::MOVrr8: case X86::MOVrr16: case X86::MOVrr32:
92 case X86::IMULrr16: case X86::IMULrr32:
93 case X86::IMULrri16: case X86::IMULrri32:
100 static MachineInstr *MakeMRInst(unsigned Opcode, unsigned FrameIndex,
102 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
103 .addReg(MI->getOperand(1).getReg());
106 static MachineInstr *MakeMIInst(unsigned Opcode, unsigned FrameIndex,
108 return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
109 .addZImm(MI->getOperand(1).getImmedValue());
112 static MachineInstr *MakeRMInst(unsigned Opcode, unsigned FrameIndex,
114 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
118 static MachineInstr *MakeRMIInst(unsigned Opcode, unsigned FrameIndex,
120 return addFrameReference(BuildMI(Opcode, 5, MI->getOperand(0).getReg()),
121 FrameIndex).addZImm(MI->getOperand(2).getImmedValue());
126 int X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
128 int FrameIndex) const
130 /// FIXME: This should obviously be autogenerated by tablegen when patterns
132 MachineBasicBlock& MBB = *MI->getParent();
133 MachineInstr* NI = 0;
135 switch(MI->getOpcode()) {
136 case X86::MOVrr8: NI = MakeMRInst(X86::MOVmr8 , FrameIndex, MI); break;
137 case X86::MOVrr16: NI = MakeMRInst(X86::MOVmr16, FrameIndex, MI); break;
138 case X86::MOVrr32: NI = MakeMRInst(X86::MOVmr32, FrameIndex, MI); break;
139 case X86::ADDrr8: NI = MakeMRInst(X86::ADDmr8 , FrameIndex, MI); break;
140 case X86::ADDrr16: NI = MakeMRInst(X86::ADDmr16, FrameIndex, MI); break;
141 case X86::ADDrr32: NI = MakeMRInst(X86::ADDmr32, FrameIndex, MI); break;
142 case X86::ADDri8: NI = MakeMIInst(X86::ADDmi8 , FrameIndex, MI); break;
143 case X86::ADDri16: NI = MakeMIInst(X86::ADDmi16, FrameIndex, MI); break;
144 case X86::ADDri32: NI = MakeMIInst(X86::ADDmi32, FrameIndex, MI); break;
145 case X86::ANDrr8: NI = MakeMRInst(X86::ANDmr8 , FrameIndex, MI); break;
146 case X86::ANDrr16: NI = MakeMRInst(X86::ANDmr16, FrameIndex, MI); break;
147 case X86::ANDrr32: NI = MakeMRInst(X86::ANDmr32, FrameIndex, MI); break;
148 case X86::ANDri8: NI = MakeMIInst(X86::ANDmi8 , FrameIndex, MI); break;
149 case X86::ANDri16: NI = MakeMIInst(X86::ANDmi16, FrameIndex, MI); break;
150 case X86::ANDri32: NI = MakeMIInst(X86::ANDmi32, FrameIndex, MI); break;
152 default: assert(0 && "Operand cannot be folded");
155 switch(MI->getOpcode()) {
156 case X86::MOVrr8: NI = MakeRMInst(X86::MOVrm8 , FrameIndex, MI); break;
157 case X86::MOVrr16: NI = MakeRMInst(X86::MOVrm16, FrameIndex, MI); break;
158 case X86::MOVrr32: NI = MakeRMInst(X86::MOVrm32, FrameIndex, MI); break;
159 case X86::ADDrr8: NI = MakeRMInst(X86::ADDrm8 , FrameIndex, MI); break;
160 case X86::ADDrr16: NI = MakeRMInst(X86::ADDrm16, FrameIndex, MI); break;
161 case X86::ADDrr32: NI = MakeRMInst(X86::ADDrm32, FrameIndex, MI); break;
162 case X86::ANDrr8: NI = MakeRMInst(X86::ANDrm8 , FrameIndex, MI); break;
163 case X86::ANDrr16: NI = MakeRMInst(X86::ANDrm16, FrameIndex, MI); break;
164 case X86::ANDrr32: NI = MakeRMInst(X86::ANDrm32, FrameIndex, MI); break;
165 case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break;
166 case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break;
167 case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI); break;
168 case X86::IMULrri32: NI = MakeRMIInst(X86::IMULrmi32, FrameIndex, MI); break;
170 default: assert(0 && "Operand cannot be folded");
173 assert(0 && "Operand cannot be folded");
176 MBB.insert(MBB.erase(MI), NI);
180 //===----------------------------------------------------------------------===//
181 // Stack Frame Processing methods
182 //===----------------------------------------------------------------------===//
184 // hasFP - Return true if the specified function should have a dedicated frame
185 // pointer register. This is true if the function has variable sized allocas or
186 // if frame pointer elimination is disabled.
188 static bool hasFP(MachineFunction &MF) {
189 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
192 void X86RegisterInfo::
193 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
194 MachineBasicBlock::iterator I) const {
196 // If we have a frame pointer, turn the adjcallstackup instruction into a
197 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
199 MachineInstr *Old = I;
200 unsigned Amount = Old->getOperand(0).getImmedValue();
202 // We need to keep the stack aligned properly. To do this, we round the
203 // amount of space needed for the outgoing arguments up to the next
204 // alignment boundary.
205 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
206 Amount = (Amount+Align-1)/Align*Align;
209 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
210 New=BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
212 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
213 New=BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(Amount);
216 // Replace the pseudo instruction with a new instruction...
224 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
225 MachineBasicBlock::iterator II) const {
227 MachineInstr &MI = *II;
228 while (!MI.getOperand(i).isFrameIndex()) {
230 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
233 int FrameIndex = MI.getOperand(i).getFrameIndex();
235 // This must be part of a four operand memory reference. Replace the
236 // FrameIndex with base register with EBP. Add add an offset to the offset.
237 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
239 // Now add the frame object offset to the offset from EBP.
240 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
241 MI.getOperand(i+3).getImmedValue()+4;
244 Offset += MF.getFrameInfo()->getStackSize();
246 Offset += 4; // Skip the saved EBP
248 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
252 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
254 // Create a frame entry for the EBP register that must be saved.
255 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
256 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
257 "Slot for EBP register must be last in order to be found!");
261 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
262 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
263 MachineBasicBlock::iterator MBBI = MBB.begin();
264 MachineFrameInfo *MFI = MF.getFrameInfo();
267 // Get the number of bytes to allocate from the FrameInfo
268 unsigned NumBytes = MFI->getStackSize();
270 // Get the offset of the stack slot for the EBP register... which is
271 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
272 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
274 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
275 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
276 MBB.insert(MBBI, MI);
279 // Save EBP into the appropriate stack slot...
280 MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
281 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
282 MBB.insert(MBBI, MI);
284 // Update EBP with the new base value...
285 if (NumBytes == 4) // mov EBP, ESP
286 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
287 else // lea EBP, [ESP+StackSize]
288 MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP,NumBytes-4);
290 MBB.insert(MBBI, MI);
293 if (MFI->hasCalls()) {
294 // When we have no frame pointer, we reserve argument space for call sites
295 // in the function immediately on entry to the current function. This
296 // eliminates the need for add/sub ESP brackets around call sites.
298 NumBytes += MFI->getMaxCallFrameSize();
300 // Round the size to a multiple of the alignment (don't forget the 4 byte
302 unsigned Align = MF.getTarget().getFrameInfo().getStackAlignment();
303 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
306 // Update frame info to pretend that this is part of the stack...
307 MFI->setStackSize(NumBytes);
310 // adjust stack pointer: ESP -= numbytes
311 MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
312 MBB.insert(MBBI, MI);
317 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
318 MachineBasicBlock &MBB) const {
319 const MachineFrameInfo *MFI = MF.getFrameInfo();
320 MachineBasicBlock::iterator MBBI = prior(MBB.end());
322 assert(MBBI->getOpcode() == X86::RET &&
323 "Can only insert epilog into returning blocks");
326 // Get the offset of the stack slot for the EBP register... which is
327 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
328 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
331 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
332 MBB.insert(MBBI, MI);
335 MI = BuildMI(X86::POPr32, 0, X86::EBP);
336 MBB.insert(MBBI, MI);
338 // Get the number of bytes allocated from the FrameInfo...
339 unsigned NumBytes = MFI->getStackSize();
341 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
342 MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
343 MBB.insert(MBBI, MI);
348 #include "X86GenRegisterInfo.inc"
350 const TargetRegisterClass*
351 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
352 switch (Ty->getPrimitiveID()) {
354 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
355 default: assert(0 && "Invalid type to getClass!");
357 case Type::SByteTyID:
358 case Type::UByteTyID: return &R8Instance;
359 case Type::ShortTyID:
360 case Type::UShortTyID: return &R16Instance;
363 case Type::PointerTyID: return &R32Instance;
365 case Type::FloatTyID:
366 case Type::DoubleTyID: return &RFPInstance;