1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/CommandLine.h"
45 ForceStackAlign("force-align-stack",
46 cl::desc("Force align the stack to the minimum alignment"
47 " needed for the function."),
48 cl::init(false), cl::Hidden);
50 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51 const TargetInstrInfo &tii)
52 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
53 X86::ADJCALLSTACKDOWN64 :
54 X86::ADJCALLSTACKDOWN32,
55 tm.getSubtarget<X86Subtarget>().is64Bit() ?
56 X86::ADJCALLSTACKUP64 :
57 X86::ADJCALLSTACKUP32),
59 // Cache some information.
60 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
61 Is64Bit = Subtarget->is64Bit();
62 IsWin64 = Subtarget->isTargetWin64();
63 StackAlign = TM.getFrameLowering()->getStackAlignment();
76 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
77 /// specific numbering, used in debug info and exception tables.
78 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
79 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
80 unsigned Flavour = DWARFFlavour::X86_64;
82 if (!Subtarget->is64Bit()) {
83 if (Subtarget->isTargetDarwin()) {
85 Flavour = DWARFFlavour::X86_32_DarwinEH;
87 Flavour = DWARFFlavour::X86_32_Generic;
88 } else if (Subtarget->isTargetCygMing()) {
89 // Unsupported by now, just quick fallback
90 Flavour = DWARFFlavour::X86_32_Generic;
92 Flavour = DWARFFlavour::X86_32_Generic;
96 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
100 X86RegisterInfo::getSEHRegNum(unsigned i) const {
101 int reg = getX86RegNum(i);
103 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
105 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
106 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
107 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
108 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
109 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
110 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
111 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
112 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
113 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
114 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
120 /// getX86RegNum - This function maps LLVM register identifiers to their X86
121 /// specific numbering, which is used in various places encoding instructions.
122 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
124 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
125 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
126 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
127 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
128 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
130 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
132 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
134 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
137 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
139 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
141 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
143 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
145 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
147 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
149 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
151 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
154 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
155 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
156 return RegNo-X86::ST0;
158 case X86::XMM0: case X86::XMM8:
159 case X86::YMM0: case X86::YMM8: case X86::MM0:
161 case X86::XMM1: case X86::XMM9:
162 case X86::YMM1: case X86::YMM9: case X86::MM1:
164 case X86::XMM2: case X86::XMM10:
165 case X86::YMM2: case X86::YMM10: case X86::MM2:
167 case X86::XMM3: case X86::XMM11:
168 case X86::YMM3: case X86::YMM11: case X86::MM3:
170 case X86::XMM4: case X86::XMM12:
171 case X86::YMM4: case X86::YMM12: case X86::MM4:
173 case X86::XMM5: case X86::XMM13:
174 case X86::YMM5: case X86::YMM13: case X86::MM5:
176 case X86::XMM6: case X86::XMM14:
177 case X86::YMM6: case X86::YMM14: case X86::MM6:
179 case X86::XMM7: case X86::XMM15:
180 case X86::YMM7: case X86::YMM15: case X86::MM7:
183 case X86::ES: return 0;
184 case X86::CS: return 1;
185 case X86::SS: return 2;
186 case X86::DS: return 3;
187 case X86::FS: return 4;
188 case X86::GS: return 5;
190 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
191 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
192 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
193 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
194 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
195 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
196 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
197 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
199 // Pseudo index registers are equivalent to a "none"
200 // scaled index (See Intel Manual 2A, table 2-3)
206 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
207 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
212 const TargetRegisterClass *
213 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
214 const TargetRegisterClass *B,
215 unsigned SubIdx) const {
219 if (B == &X86::GR8RegClass) {
220 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
222 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
223 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
224 A == &X86::GR64_NOREXRegClass ||
225 A == &X86::GR64_NOSPRegClass ||
226 A == &X86::GR64_NOREX_NOSPRegClass)
227 return &X86::GR64_ABCDRegClass;
228 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
229 A == &X86::GR32_NOREXRegClass ||
230 A == &X86::GR32_NOSPRegClass)
231 return &X86::GR32_ABCDRegClass;
232 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
233 A == &X86::GR16_NOREXRegClass)
234 return &X86::GR16_ABCDRegClass;
235 } else if (B == &X86::GR8_NOREXRegClass) {
236 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
237 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
238 return &X86::GR64_NOREXRegClass;
239 else if (A == &X86::GR64_ABCDRegClass)
240 return &X86::GR64_ABCDRegClass;
241 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
242 A == &X86::GR32_NOSPRegClass)
243 return &X86::GR32_NOREXRegClass;
244 else if (A == &X86::GR32_ABCDRegClass)
245 return &X86::GR32_ABCDRegClass;
246 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
247 return &X86::GR16_NOREXRegClass;
248 else if (A == &X86::GR16_ABCDRegClass)
249 return &X86::GR16_ABCDRegClass;
252 case X86::sub_8bit_hi:
253 if (B == &X86::GR8_ABCD_HRegClass ||
254 B->hasSubClass(&X86::GR8_ABCD_HRegClass))
255 switch (A->getSize()) {
256 case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
257 case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
258 case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
263 if (B == &X86::GR16RegClass) {
264 if (A->getSize() == 4 || A->getSize() == 8)
266 } else if (B == &X86::GR16_ABCDRegClass) {
267 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
268 A == &X86::GR64_NOREXRegClass ||
269 A == &X86::GR64_NOSPRegClass ||
270 A == &X86::GR64_NOREX_NOSPRegClass)
271 return &X86::GR64_ABCDRegClass;
272 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
273 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
274 return &X86::GR32_ABCDRegClass;
275 } else if (B == &X86::GR16_NOREXRegClass) {
276 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
277 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
278 return &X86::GR64_NOREXRegClass;
279 else if (A == &X86::GR64_ABCDRegClass)
280 return &X86::GR64_ABCDRegClass;
281 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
282 A == &X86::GR32_NOSPRegClass)
283 return &X86::GR32_NOREXRegClass;
284 else if (A == &X86::GR32_ABCDRegClass)
285 return &X86::GR64_ABCDRegClass;
289 if (B == &X86::GR32RegClass) {
290 if (A->getSize() == 8)
292 } else if (B == &X86::GR32_NOSPRegClass) {
293 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
294 return &X86::GR64_NOSPRegClass;
295 if (A->getSize() == 8)
296 return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
297 } else if (B == &X86::GR32_ABCDRegClass) {
298 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
299 A == &X86::GR64_NOREXRegClass ||
300 A == &X86::GR64_NOSPRegClass ||
301 A == &X86::GR64_NOREX_NOSPRegClass)
302 return &X86::GR64_ABCDRegClass;
303 } else if (B == &X86::GR32_NOREXRegClass) {
304 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
305 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
306 return &X86::GR64_NOREXRegClass;
307 else if (A == &X86::GR64_ABCDRegClass)
308 return &X86::GR64_ABCDRegClass;
312 if (B == &X86::FR32RegClass)
316 if (B == &X86::FR64RegClass)
320 if (B == &X86::VR128RegClass)
327 const TargetRegisterClass*
328 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
329 const TargetRegisterClass *Super = RC;
330 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
332 switch (Super->getID()) {
333 case X86::GR8RegClassID:
334 case X86::GR16RegClassID:
335 case X86::GR32RegClassID:
336 case X86::GR64RegClassID:
337 case X86::FR32RegClassID:
338 case X86::FR64RegClassID:
339 case X86::RFP32RegClassID:
340 case X86::RFP64RegClassID:
341 case X86::RFP80RegClassID:
342 case X86::VR128RegClassID:
343 case X86::VR256RegClassID:
344 // Don't return a super-class that would shrink the spill size.
345 // That can happen with the vector and float classes.
346 if (Super->getSize() == RC->getSize())
354 const TargetRegisterClass *
355 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
357 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
358 case 0: // Normal GPRs.
359 if (TM.getSubtarget<X86Subtarget>().is64Bit())
360 return &X86::GR64RegClass;
361 return &X86::GR32RegClass;
362 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
363 if (TM.getSubtarget<X86Subtarget>().is64Bit())
364 return &X86::GR64_NOSPRegClass;
365 return &X86::GR32_NOSPRegClass;
366 case 2: // Available for tailcall (not callee-saved GPRs).
367 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
368 return &X86::GR64_TCW64RegClass;
369 if (TM.getSubtarget<X86Subtarget>().is64Bit())
370 return &X86::GR64_TCRegClass;
371 return &X86::GR32_TCRegClass;
375 const TargetRegisterClass *
376 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
377 if (RC == &X86::CCRRegClass) {
379 return &X86::GR64RegClass;
381 return &X86::GR32RegClass;
387 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
388 MachineFunction &MF) const {
389 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
391 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
392 switch (RC->getID()) {
395 case X86::GR32RegClassID:
397 case X86::GR64RegClassID:
399 case X86::VR128RegClassID:
400 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
401 case X86::VR64RegClassID:
407 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
408 bool callsEHReturn = false;
409 bool ghcCall = false;
412 callsEHReturn = MF->getMMI().callsEHReturn();
413 const Function *F = MF->getFunction();
414 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
417 static const unsigned GhcCalleeSavedRegs[] = {
421 static const unsigned CalleeSavedRegs32Bit[] = {
422 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
425 static const unsigned CalleeSavedRegs32EHRet[] = {
426 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
429 static const unsigned CalleeSavedRegs64Bit[] = {
430 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
433 static const unsigned CalleeSavedRegs64EHRet[] = {
434 X86::RAX, X86::RDX, X86::RBX, X86::R12,
435 X86::R13, X86::R14, X86::R15, X86::RBP, 0
438 static const unsigned CalleeSavedRegsWin64[] = {
439 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
440 X86::R12, X86::R13, X86::R14, X86::R15,
441 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
442 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
443 X86::XMM14, X86::XMM15, 0
447 return GhcCalleeSavedRegs;
448 } else if (Is64Bit) {
450 return CalleeSavedRegsWin64;
452 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
454 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
458 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
459 BitVector Reserved(getNumRegs());
460 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
462 // Set the stack-pointer register and its aliases as reserved.
463 Reserved.set(X86::RSP);
464 Reserved.set(X86::ESP);
465 Reserved.set(X86::SP);
466 Reserved.set(X86::SPL);
468 // Set the instruction pointer register and its aliases as reserved.
469 Reserved.set(X86::RIP);
470 Reserved.set(X86::EIP);
471 Reserved.set(X86::IP);
473 // Set the frame-pointer register and its aliases as reserved if needed.
474 if (TFI->hasFP(MF)) {
475 Reserved.set(X86::RBP);
476 Reserved.set(X86::EBP);
477 Reserved.set(X86::BP);
478 Reserved.set(X86::BPL);
481 // Mark the x87 stack registers as reserved, since they don't behave normally
482 // with respect to liveness. We don't fully model the effects of x87 stack
483 // pushes and pops after stackification.
484 Reserved.set(X86::ST0);
485 Reserved.set(X86::ST1);
486 Reserved.set(X86::ST2);
487 Reserved.set(X86::ST3);
488 Reserved.set(X86::ST4);
489 Reserved.set(X86::ST5);
490 Reserved.set(X86::ST6);
491 Reserved.set(X86::ST7);
493 // Mark the segment registers as reserved.
494 Reserved.set(X86::CS);
495 Reserved.set(X86::SS);
496 Reserved.set(X86::DS);
497 Reserved.set(X86::ES);
498 Reserved.set(X86::FS);
499 Reserved.set(X86::GS);
504 //===----------------------------------------------------------------------===//
505 // Stack Frame Processing methods
506 //===----------------------------------------------------------------------===//
508 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
509 const MachineFrameInfo *MFI = MF.getFrameInfo();
510 return (RealignStack &&
511 !MFI->hasVarSizedObjects());
514 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
515 const MachineFrameInfo *MFI = MF.getFrameInfo();
516 const Function *F = MF.getFunction();
517 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
518 F->hasFnAttr(Attribute::StackAlignment));
520 // FIXME: Currently we don't support stack realignment for functions with
521 // variable-sized allocas.
522 // FIXME: It's more complicated than this...
523 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
525 "Stack realignment in presence of dynamic allocas is not supported");
527 // If we've requested that we force align the stack do so now.
529 return canRealignStack(MF);
531 return requiresRealignment && canRealignStack(MF);
534 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
535 unsigned Reg, int &FrameIdx) const {
536 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
538 if (Reg == FramePtr && TFI->hasFP(MF)) {
539 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
545 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
548 return X86::SUB64ri8;
549 return X86::SUB64ri32;
552 return X86::SUB32ri8;
557 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
560 return X86::ADD64ri8;
561 return X86::ADD64ri32;
564 return X86::ADD32ri8;
569 void X86RegisterInfo::
570 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
571 MachineBasicBlock::iterator I) const {
572 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
573 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
574 int Opcode = I->getOpcode();
575 bool isDestroy = Opcode == getCallFrameDestroyOpcode();
576 DebugLoc DL = I->getDebugLoc();
577 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
578 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
581 if (!reseveCallFrame) {
582 // If the stack pointer can be changed after prologue, turn the
583 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
584 // adjcallstackdown instruction into 'add ESP, <amt>'
585 // TODO: consider using push / pop instead of sub + store / add
589 // We need to keep the stack aligned properly. To do this, we round the
590 // amount of space needed for the outgoing arguments up to the next
591 // alignment boundary.
592 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
594 MachineInstr *New = 0;
595 if (Opcode == getCallFrameSetupOpcode()) {
596 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
601 assert(Opcode == getCallFrameDestroyOpcode());
603 // Factor out the amount the callee already popped.
607 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
608 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
609 .addReg(StackPtr).addImm(Amount);
614 // The EFLAGS implicit def is dead.
615 New->getOperand(3).setIsDead();
617 // Replace the pseudo instruction with a new instruction.
624 if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) {
625 // If we are performing frame pointer elimination and if the callee pops
626 // something off the stack pointer, add it back. We do this until we have
627 // more advanced stack pointer tracking ability.
628 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
629 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
630 .addReg(StackPtr).addImm(CalleeAmt);
632 // The EFLAGS implicit def is dead.
633 New->getOperand(3).setIsDead();
639 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
640 int SPAdj, RegScavenger *RS) const{
641 assert(SPAdj == 0 && "Unexpected");
644 MachineInstr &MI = *II;
645 MachineFunction &MF = *MI.getParent()->getParent();
646 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
648 while (!MI.getOperand(i).isFI()) {
650 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
653 int FrameIndex = MI.getOperand(i).getIndex();
656 unsigned Opc = MI.getOpcode();
657 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
658 if (needsStackRealignment(MF))
659 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
663 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
665 // This must be part of a four operand memory reference. Replace the
666 // FrameIndex with base register with EBP. Add an offset to the offset.
667 MI.getOperand(i).ChangeToRegister(BasePtr, false);
669 // Now add the frame object offset to the offset from EBP.
672 // Tail call jmp happens after FP is popped.
673 const MachineFrameInfo *MFI = MF.getFrameInfo();
674 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
676 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
678 if (MI.getOperand(i+3).isImm()) {
679 // Offset is a 32-bit integer.
680 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
681 MI.getOperand(i + 3).ChangeToImmediate(Offset);
683 // Offset is symbolic. This is extremely rare.
684 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
685 MI.getOperand(i+3).setOffset(Offset);
689 unsigned X86RegisterInfo::getRARegister() const {
690 return Is64Bit ? X86::RIP // Should have dwarf #16.
691 : X86::EIP; // Should have dwarf #8.
694 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
695 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
696 return TFI->hasFP(MF) ? FramePtr : StackPtr;
699 unsigned X86RegisterInfo::getEHExceptionRegister() const {
700 llvm_unreachable("What is the exception register");
704 unsigned X86RegisterInfo::getEHHandlerRegister() const {
705 llvm_unreachable("What is the exception handler register");
710 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
711 switch (VT.getSimpleVT().SimpleTy) {
717 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
719 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
721 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
723 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
729 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
731 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
733 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
735 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
737 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
739 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
741 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
743 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
745 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
747 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
749 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
751 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
753 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
755 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
757 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
759 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
766 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
768 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
770 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
772 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
774 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
776 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
778 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
780 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
782 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
784 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
786 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
788 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
790 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
792 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
794 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
796 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
802 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
804 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
806 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
808 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
810 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
812 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
814 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
816 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
818 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
820 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
822 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
824 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
826 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
828 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
830 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
832 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
838 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
840 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
842 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
844 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
846 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
848 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
850 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
852 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
854 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
856 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
858 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
860 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
862 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
864 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
866 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
868 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
877 #include "X86GenRegisterInfo.inc"
880 struct MSAH : public MachineFunctionPass {
882 MSAH() : MachineFunctionPass(ID) {}
884 virtual bool runOnMachineFunction(MachineFunction &MF) {
885 const X86TargetMachine *TM =
886 static_cast<const X86TargetMachine *>(&MF.getTarget());
887 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
888 MachineRegisterInfo &RI = MF.getRegInfo();
889 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
890 unsigned StackAlignment = X86RI->getStackAlignment();
892 // Be over-conservative: scan over all vreg defs and find whether vector
893 // registers are used. If yes, there is a possibility that vector register
894 // will be spilled and thus require dynamic stack realignment.
895 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
896 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
897 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
898 FuncInfo->setReserveFP(true);
906 virtual const char *getPassName() const {
907 return "X86 Maximal Stack Alignment Check";
910 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
911 AU.setPreservesCFG();
912 MachineFunctionPass::getAnalysisUsage(AU);
920 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }