1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
47 // Cache some information.
48 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
49 Is64Bit = Subtarget->is64Bit();
50 IsWin64 = Subtarget->isTargetWin64();
51 StackAlign = TM.getFrameInfo()->getStackAlignment();
63 // getDwarfRegNum - This function maps LLVM register identifiers to the
64 // Dwarf specific numbering, used in debug info and exception tables.
66 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 unsigned Flavour = DWARFFlavour::X86_64;
69 if (!Subtarget->is64Bit()) {
70 if (Subtarget->isTargetDarwin()) {
72 Flavour = DWARFFlavour::X86_32_DarwinEH;
74 Flavour = DWARFFlavour::X86_32_Generic;
75 } else if (Subtarget->isTargetCygMing()) {
76 // Unsupported by now, just quick fallback
77 Flavour = DWARFFlavour::X86_32_Generic;
79 Flavour = DWARFFlavour::X86_32_Generic;
83 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
86 // getX86RegNum - This function maps LLVM register identifiers to their X86
87 // specific numbering, which is used in various places encoding instructions.
89 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
91 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
92 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
93 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
94 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
95 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
97 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
99 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
101 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
104 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
106 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
108 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
110 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
112 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
114 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
116 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
118 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
121 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
122 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
123 return RegNo-X86::ST0;
125 case X86::XMM0: case X86::XMM8: case X86::MM0:
127 case X86::XMM1: case X86::XMM9: case X86::MM1:
129 case X86::XMM2: case X86::XMM10: case X86::MM2:
131 case X86::XMM3: case X86::XMM11: case X86::MM3:
133 case X86::XMM4: case X86::XMM12: case X86::MM4:
135 case X86::XMM5: case X86::XMM13: case X86::MM5:
137 case X86::XMM6: case X86::XMM14: case X86::MM6:
139 case X86::XMM7: case X86::XMM15: case X86::MM7:
143 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
144 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
149 const TargetRegisterClass *
150 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
151 if (RC == &X86::CCRRegClass) {
153 return &X86::GR64RegClass;
155 return &X86::GR32RegClass;
161 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
162 bool callsEHReturn = false;
165 const MachineFrameInfo *MFI = MF->getFrameInfo();
166 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
167 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
170 static const unsigned CalleeSavedRegs32Bit[] = {
171 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
174 static const unsigned CalleeSavedRegs32EHRet[] = {
175 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
178 static const unsigned CalleeSavedRegs64Bit[] = {
179 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
182 static const unsigned CalleeSavedRegs64EHRet[] = {
183 X86::RAX, X86::RDX, X86::RBX, X86::R12,
184 X86::R13, X86::R14, X86::R15, X86::RBP, 0
187 static const unsigned CalleeSavedRegsWin64[] = {
188 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
189 X86::R12, X86::R13, X86::R14, X86::R15,
190 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
191 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
192 X86::XMM14, X86::XMM15, 0
197 return CalleeSavedRegsWin64;
199 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
201 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
205 const TargetRegisterClass* const*
206 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
207 bool callsEHReturn = false;
210 const MachineFrameInfo *MFI = MF->getFrameInfo();
211 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
212 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
215 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
216 &X86::GR32RegClass, &X86::GR32RegClass,
217 &X86::GR32RegClass, &X86::GR32RegClass, 0
219 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
220 &X86::GR32RegClass, &X86::GR32RegClass,
221 &X86::GR32RegClass, &X86::GR32RegClass,
222 &X86::GR32RegClass, &X86::GR32RegClass, 0
224 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
225 &X86::GR64RegClass, &X86::GR64RegClass,
226 &X86::GR64RegClass, &X86::GR64RegClass,
227 &X86::GR64RegClass, &X86::GR64RegClass, 0
229 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
230 &X86::GR64RegClass, &X86::GR64RegClass,
231 &X86::GR64RegClass, &X86::GR64RegClass,
232 &X86::GR64RegClass, &X86::GR64RegClass,
233 &X86::GR64RegClass, &X86::GR64RegClass, 0
235 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
236 &X86::GR64RegClass, &X86::GR64RegClass,
237 &X86::GR64RegClass, &X86::GR64RegClass,
238 &X86::GR64RegClass, &X86::GR64RegClass,
239 &X86::GR64RegClass, &X86::GR64RegClass,
240 &X86::VR128RegClass, &X86::VR128RegClass,
241 &X86::VR128RegClass, &X86::VR128RegClass,
242 &X86::VR128RegClass, &X86::VR128RegClass,
243 &X86::VR128RegClass, &X86::VR128RegClass,
244 &X86::VR128RegClass, &X86::VR128RegClass, 0
249 return CalleeSavedRegClassesWin64;
251 return (callsEHReturn ?
252 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
254 return (callsEHReturn ?
255 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
259 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
260 BitVector Reserved(getNumRegs());
261 Reserved.set(X86::RSP);
262 Reserved.set(X86::ESP);
263 Reserved.set(X86::SP);
264 Reserved.set(X86::SPL);
266 Reserved.set(X86::RBP);
267 Reserved.set(X86::EBP);
268 Reserved.set(X86::BP);
269 Reserved.set(X86::BPL);
274 //===----------------------------------------------------------------------===//
275 // Stack Frame Processing methods
276 //===----------------------------------------------------------------------===//
278 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
279 unsigned MaxAlign = 0;
280 for (int i = FFI->getObjectIndexBegin(),
281 e = FFI->getObjectIndexEnd(); i != e; ++i) {
282 if (FFI->isDeadObjectIndex(i))
284 unsigned Align = FFI->getObjectAlignment(i);
285 MaxAlign = std::max(MaxAlign, Align);
291 // hasFP - Return true if the specified function should have a dedicated frame
292 // pointer register. This is true if the function has variable sized allocas or
293 // if frame pointer elimination is disabled.
295 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
296 const MachineFrameInfo *MFI = MF.getFrameInfo();
297 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
299 return (NoFramePointerElim ||
300 needsStackRealignment(MF) ||
301 MFI->hasVarSizedObjects() ||
302 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
303 (MMI && MMI->callsUnwindInit()));
306 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
307 const MachineFrameInfo *MFI = MF.getFrameInfo();;
309 // FIXME: Currently we don't support stack realignment for functions with
310 // variable-sized allocas
311 return (RealignStack &&
312 (MFI->getMaxAlignment() > StackAlign &&
313 !MFI->hasVarSizedObjects()));
316 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
317 return !MF.getFrameInfo()->hasVarSizedObjects();
321 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
322 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
323 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
325 if (needsStackRealignment(MF)) {
327 // Skip the saved EBP
330 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
331 assert( (-(Offset + StackSize)) % Align == 0);
332 return Offset + StackSize;
335 // FIXME: Support tail calls
338 return Offset + StackSize;
340 // Skip the saved EBP
343 // Skip the RETADDR move area
344 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
345 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
346 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
352 void X86RegisterInfo::
353 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
354 MachineBasicBlock::iterator I) const {
355 if (!hasReservedCallFrame(MF)) {
356 // If the stack pointer can be changed after prologue, turn the
357 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
358 // adjcallstackdown instruction into 'add ESP, <amt>'
359 // TODO: consider using push / pop instead of sub + store / add
360 MachineInstr *Old = I;
361 uint64_t Amount = Old->getOperand(0).getImm();
363 // We need to keep the stack aligned properly. To do this, we round the
364 // amount of space needed for the outgoing arguments up to the next
365 // alignment boundary.
366 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
368 MachineInstr *New = 0;
369 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
370 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
371 StackPtr).addReg(StackPtr).addImm(Amount);
373 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
374 // factor out the amount the callee already popped.
375 uint64_t CalleeAmt = Old->getOperand(1).getImm();
378 unsigned Opc = (Amount < 128) ?
379 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
380 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
381 New = BuildMI(MF, TII.get(Opc), StackPtr)
382 .addReg(StackPtr).addImm(Amount);
386 // Replace the pseudo instruction with a new instruction...
387 if (New) MBB.insert(I, New);
389 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
390 // If we are performing frame pointer elimination and if the callee pops
391 // something off the stack pointer, add it back. We do this until we have
392 // more advanced stack pointer tracking ability.
393 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
394 unsigned Opc = (CalleeAmt < 128) ?
395 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
396 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
398 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
406 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
407 int SPAdj, RegScavenger *RS) const{
408 assert(SPAdj == 0 && "Unexpected");
411 MachineInstr &MI = *II;
412 MachineFunction &MF = *MI.getParent()->getParent();
413 while (!MI.getOperand(i).isFrameIndex()) {
415 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
418 int FrameIndex = MI.getOperand(i).getIndex();
421 if (needsStackRealignment(MF))
422 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
424 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
426 // This must be part of a four operand memory reference. Replace the
427 // FrameIndex with base register with EBP. Add an offset to the offset.
428 MI.getOperand(i).ChangeToRegister(BasePtr, false);
430 // Now add the frame object offset to the offset from EBP.
431 int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
432 MI.getOperand(i+3).getImm();
434 MI.getOperand(i+3).ChangeToImmediate(Offset);
438 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
439 RegScavenger *RS) const {
440 MachineFrameInfo *FFI = MF.getFrameInfo();
442 // Calculate and set max stack object alignment early, so we can decide
443 // whether we will need stack realignment (and thus FP).
444 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
445 calculateMaxStackAlignment(FFI));
447 FFI->setMaxAlignment(MaxAlign);
451 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
452 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
453 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
454 if (TailCallReturnAddrDelta < 0) {
455 // create RETURNADDR area
465 CreateFixedObject(-TailCallReturnAddrDelta,
466 (-1*SlotSize)+TailCallReturnAddrDelta);
469 assert((TailCallReturnAddrDelta <= 0) &&
470 "The Delta should always be zero or negative");
471 // Create a frame entry for the EBP register that must be saved.
472 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
474 TailCallReturnAddrDelta);
475 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
476 "Slot for EBP register must be last in order to be found!");
480 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
481 /// stack pointer by a constant value.
483 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
484 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
485 const TargetInstrInfo &TII) {
486 bool isSub = NumBytes < 0;
487 uint64_t Offset = isSub ? -NumBytes : NumBytes;
490 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
491 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
493 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
494 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
495 uint64_t Chunk = (1LL << 31) - 1;
498 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
499 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
504 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
506 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
507 unsigned StackPtr, uint64_t *NumBytes = NULL) {
508 if (MBBI == MBB.begin()) return;
510 MachineBasicBlock::iterator PI = prior(MBBI);
511 unsigned Opc = PI->getOpcode();
512 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
513 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
514 PI->getOperand(0).getReg() == StackPtr) {
516 *NumBytes += PI->getOperand(2).getImm();
518 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
519 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
520 PI->getOperand(0).getReg() == StackPtr) {
522 *NumBytes -= PI->getOperand(2).getImm();
527 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
529 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
530 MachineBasicBlock::iterator &MBBI,
531 unsigned StackPtr, uint64_t *NumBytes = NULL) {
534 if (MBBI == MBB.end()) return;
536 MachineBasicBlock::iterator NI = next(MBBI);
537 if (NI == MBB.end()) return;
539 unsigned Opc = NI->getOpcode();
540 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
541 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
542 NI->getOperand(0).getReg() == StackPtr) {
544 *NumBytes -= NI->getOperand(2).getImm();
547 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
548 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
549 NI->getOperand(0).getReg() == StackPtr) {
551 *NumBytes += NI->getOperand(2).getImm();
557 /// mergeSPUpdates - Checks the instruction before/after the passed
558 /// instruction. If it is an ADD/SUB instruction it is deleted
559 /// argument and the stack adjustment is returned as a positive value for ADD
560 /// and a negative for SUB.
561 static int mergeSPUpdates(MachineBasicBlock &MBB,
562 MachineBasicBlock::iterator &MBBI,
564 bool doMergeWithPrevious) {
566 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
567 (!doMergeWithPrevious && MBBI == MBB.end()))
572 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
573 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
574 unsigned Opc = PI->getOpcode();
575 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
576 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
577 PI->getOperand(0).getReg() == StackPtr){
578 Offset += PI->getOperand(2).getImm();
580 if (!doMergeWithPrevious) MBBI = NI;
581 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
582 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
583 PI->getOperand(0).getReg() == StackPtr) {
584 Offset -= PI->getOperand(2).getImm();
586 if (!doMergeWithPrevious) MBBI = NI;
592 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
593 unsigned FrameLabelId,
594 unsigned ReadyLabelId) const {
595 MachineFrameInfo *MFI = MF.getFrameInfo();
596 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
600 uint64_t StackSize = MFI->getStackSize();
601 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
602 const TargetData *TD = MF.getTarget().getTargetData();
604 // Calculate amount of bytes used for return address storing
606 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
607 TargetFrameInfo::StackGrowsUp ?
608 TD->getPointerSize() : -TD->getPointerSize());
611 // Show update of SP.
614 MachineLocation SPDst(MachineLocation::VirtualFP);
615 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
616 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
618 MachineLocation SPDst(MachineLocation::VirtualFP);
619 MachineLocation SPSrc(MachineLocation::VirtualFP,
620 -StackSize+stackGrowth);
621 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
624 //FIXME: Verify & implement for FP
625 MachineLocation SPDst(StackPtr);
626 MachineLocation SPSrc(StackPtr, stackGrowth);
627 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
630 // Add callee saved registers to move list.
631 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
633 // FIXME: This is dirty hack. The code itself is pretty mess right now.
634 // It should be rewritten from scratch and generalized sometimes.
636 // Determine maximum offset (minumum due to stack growth)
637 int64_t MaxOffset = 0;
638 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
639 MaxOffset = std::min(MaxOffset,
640 MFI->getObjectOffset(CSI[I].getFrameIdx()));
643 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
644 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
645 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
646 unsigned Reg = CSI[I].getReg();
647 Offset = (MaxOffset-Offset+saveAreaOffset);
648 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
649 MachineLocation CSSrc(Reg);
650 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
655 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
656 MachineLocation FPSrc(FramePtr);
657 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
660 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
661 MachineLocation FPSrc(MachineLocation::VirtualFP);
662 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
666 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
667 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
668 MachineFrameInfo *MFI = MF.getFrameInfo();
669 const Function* Fn = MF.getFunction();
670 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
671 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
672 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
673 MachineBasicBlock::iterator MBBI = MBB.begin();
674 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
675 !Fn->doesNotThrow() ||
676 UnwindTablesMandatory;
677 // Prepare for frame info.
678 unsigned FrameLabelId = 0;
680 // Get the number of bytes to allocate from the FrameInfo.
681 uint64_t StackSize = MFI->getStackSize();
682 // Get desired stack alignment
683 uint64_t MaxAlign = MFI->getMaxAlignment();
685 // Add RETADDR move area to callee saved frame size.
686 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
687 if (TailCallReturnAddrDelta < 0)
688 X86FI->setCalleeSavedFrameSize(
689 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
691 // Insert stack pointer adjustment for later moving of return addr. Only
692 // applies to tail call optimized functions where the callee argument stack
693 // size is bigger than the callers.
694 if (TailCallReturnAddrDelta < 0) {
695 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
696 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
699 uint64_t NumBytes = 0;
701 // Calculate required stack adjustment
702 uint64_t FrameSize = StackSize - SlotSize;
703 if (needsStackRealignment(MF))
704 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
706 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
708 // Get the offset of the stack slot for the EBP register... which is
709 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
710 // Update the frame offset adjustment.
711 MFI->setOffsetAdjustment(-NumBytes);
713 // Save EBP into the appropriate stack slot...
714 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
717 if (needsFrameMoves) {
718 // Mark effective beginning of when frame pointer becomes valid.
719 FrameLabelId = MMI->NextLabelID();
720 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
723 // Update EBP with the new base value...
724 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
728 if (needsStackRealignment(MF))
730 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
731 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
733 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
735 unsigned ReadyLabelId = 0;
736 if (needsFrameMoves) {
737 // Mark effective beginning of when frame pointer is ready.
738 ReadyLabelId = MMI->NextLabelID();
739 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
742 // Skip the callee-saved push instructions.
743 while (MBBI != MBB.end() &&
744 (MBBI->getOpcode() == X86::PUSH32r ||
745 MBBI->getOpcode() == X86::PUSH64r))
748 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
749 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
750 // Check, whether EAX is livein for this function
751 bool isEAXAlive = false;
752 for (MachineRegisterInfo::livein_iterator
753 II = MF.getRegInfo().livein_begin(),
754 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
755 unsigned Reg = II->first;
756 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
757 Reg == X86::AH || Reg == X86::AL);
760 // Function prologue calls _alloca to probe the stack when allocating
761 // more than 4k bytes in one go. Touching the stack at 4K increments is
762 // necessary to ensure that the guard pages used by the OS virtual memory
763 // manager are allocated in correct sequence.
765 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
766 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
767 .addExternalSymbol("_alloca");
770 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
771 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
772 // allocated bytes for EAX.
773 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
774 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
775 .addExternalSymbol("_alloca");
777 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
778 StackPtr, false, NumBytes-4);
779 MBB.insert(MBBI, MI);
782 // If there is an SUB32ri of ESP immediately before this instruction,
783 // merge the two. This can be the case when tail call elimination is
784 // enabled and the callee has more arguments then the caller.
785 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
786 // If there is an ADD32ri or SUB32ri of ESP immediately after this
787 // instruction, merge the two instructions.
788 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
791 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
796 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
799 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
800 MachineBasicBlock &MBB) const {
801 const MachineFrameInfo *MFI = MF.getFrameInfo();
802 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
803 MachineBasicBlock::iterator MBBI = prior(MBB.end());
804 unsigned RetOpcode = MBBI->getOpcode();
809 case X86::TCRETURNdi:
810 case X86::TCRETURNri:
811 case X86::TCRETURNri64:
812 case X86::TCRETURNdi64:
814 case X86::EH_RETURN64:
817 case X86::TAILJMPm: break; // These are ok
819 assert(0 && "Can only insert epilog into returning blocks");
822 // Get the number of bytes to allocate from the FrameInfo
823 uint64_t StackSize = MFI->getStackSize();
824 uint64_t MaxAlign = MFI->getMaxAlignment();
825 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
826 uint64_t NumBytes = 0;
829 // Calculate required stack adjustment
830 uint64_t FrameSize = StackSize - SlotSize;
831 if (needsStackRealignment(MF))
832 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
834 NumBytes = FrameSize - CSSize;
837 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
839 NumBytes = StackSize - CSSize;
841 // Skip the callee-saved pop instructions.
842 MachineBasicBlock::iterator LastCSPop = MBBI;
843 while (MBBI != MBB.begin()) {
844 MachineBasicBlock::iterator PI = prior(MBBI);
845 unsigned Opc = PI->getOpcode();
846 if (Opc != X86::POP32r && Opc != X86::POP64r &&
847 !PI->getDesc().isTerminator())
852 // If there is an ADD32ri or SUB32ri of ESP immediately before this
853 // instruction, merge the two instructions.
854 if (NumBytes || MFI->hasVarSizedObjects())
855 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
857 // If dynamic alloca is used, then reset esp to point to the last callee-saved
858 // slot before popping them off! Same applies for the case, when stack was
860 if (needsStackRealignment(MF)) {
861 // We cannot use LEA here, because stack pointer was realigned. We need to
862 // deallocate local frame back
864 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
865 MBBI = prior(LastCSPop);
869 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
870 StackPtr).addReg(FramePtr);
871 } else if (MFI->hasVarSizedObjects()) {
873 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
874 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
875 FramePtr, false, -CSSize);
876 MBB.insert(MBBI, MI);
878 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
879 StackPtr).addReg(FramePtr);
882 // adjust stack pointer back: ESP += numbytes
884 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
887 // We're returning from function via eh_return.
888 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
889 MBBI = prior(MBB.end());
890 MachineOperand &DestAddr = MBBI->getOperand(0);
891 assert(DestAddr.isRegister() && "Offset should be in register!");
893 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
894 StackPtr).addReg(DestAddr.getReg());
895 // Tail call return: adjust the stack pointer and jump to callee
896 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
897 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
898 MBBI = prior(MBB.end());
899 MachineOperand &JumpTarget = MBBI->getOperand(0);
900 MachineOperand &StackAdjust = MBBI->getOperand(1);
901 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
903 // Adjust stack pointer.
904 int StackAdj = StackAdjust.getImm();
905 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
907 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
908 // Incoporate the retaddr area.
909 Offset = StackAdj-MaxTCDelta;
910 assert(Offset >= 0 && "Offset should never be negative");
912 // Check for possible merge with preceeding ADD instruction.
913 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
914 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
916 // Jump to label or value in register.
917 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
918 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
919 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
920 else if (RetOpcode== X86::TCRETURNri64) {
921 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
923 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
924 // Delete the pseudo instruction TCRETURN.
926 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
927 (X86FI->getTCReturnAddrDelta() < 0)) {
928 // Add the return addr area delta back since we are not tail calling.
929 int delta = -1*X86FI->getTCReturnAddrDelta();
930 MBBI = prior(MBB.end());
931 // Check for possible merge with preceeding ADD instruction.
932 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
933 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
937 unsigned X86RegisterInfo::getRARegister() const {
939 return X86::RIP; // Should have dwarf #16
941 return X86::EIP; // Should have dwarf #8
944 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
945 return hasFP(MF) ? FramePtr : StackPtr;
948 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
950 // Calculate amount of bytes used for return address storing
951 int stackGrowth = (Is64Bit ? -8 : -4);
953 // Initial state of the frame pointer is esp+4.
954 MachineLocation Dst(MachineLocation::VirtualFP);
955 MachineLocation Src(StackPtr, stackGrowth);
956 Moves.push_back(MachineMove(0, Dst, Src));
958 // Add return address to move list
959 MachineLocation CSDst(StackPtr, stackGrowth);
960 MachineLocation CSSrc(getRARegister());
961 Moves.push_back(MachineMove(0, CSDst, CSSrc));
964 unsigned X86RegisterInfo::getEHExceptionRegister() const {
965 assert(0 && "What is the exception register");
969 unsigned X86RegisterInfo::getEHHandlerRegister() const {
970 assert(0 && "What is the exception handler register");
975 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
976 switch (VT.getSimpleVT()) {
982 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
984 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
986 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
988 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
994 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
996 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
998 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1000 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1002 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1004 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1006 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1008 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1010 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1012 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1014 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1016 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1018 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1020 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1022 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1024 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1030 default: return Reg;
1031 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1033 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1035 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1037 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1039 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1041 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1043 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1045 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1047 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1049 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1051 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1053 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1055 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1057 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1059 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1061 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1066 default: return Reg;
1067 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1069 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1071 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1073 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1075 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1077 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1079 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1081 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1083 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1085 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1087 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1089 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1091 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1093 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1095 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1097 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1102 default: return Reg;
1103 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1105 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1107 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1109 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1111 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1113 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1115 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1117 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1119 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1121 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1123 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1125 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1127 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1129 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1131 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1133 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1142 #include "X86GenRegisterInfo.inc"
1145 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1147 MSAC() : MachineFunctionPass(&ID) {}
1149 virtual bool runOnMachineFunction(MachineFunction &MF) {
1150 MachineFrameInfo *FFI = MF.getFrameInfo();
1151 MachineRegisterInfo &RI = MF.getRegInfo();
1153 // Calculate max stack alignment of all already allocated stack objects.
1154 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1156 // Be over-conservative: scan over all vreg defs and find, whether vector
1157 // registers are used. If yes - there is probability, that vector register
1158 // will be spilled and thus stack needs to be aligned properly.
1159 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1160 RegNum < RI.getLastVirtReg(); ++RegNum)
1161 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1163 FFI->setMaxAlignment(MaxAlign);
1168 virtual const char *getPassName() const {
1169 return "X86 Maximal Stack Alignment Calculator";
1177 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }