1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/Target/TargetAsmInfo.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
41 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
42 const TargetInstrInfo &tii)
43 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
45 // Cache some information.
46 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
47 Is64Bit = Subtarget->is64Bit();
48 IsWin64 = Subtarget->isTargetWin64();
49 StackAlign = TM.getFrameInfo()->getStackAlignment();
61 // getDwarfRegNum - This function maps LLVM register identifiers to the
62 // Dwarf specific numbering, used in debug info and exception tables.
64 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
65 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
66 unsigned Flavour = DWARFFlavour::X86_64;
67 if (!Subtarget->is64Bit()) {
68 if (Subtarget->isTargetDarwin()) {
70 Flavour = DWARFFlavour::X86_32_DarwinEH;
72 Flavour = DWARFFlavour::X86_32_Generic;
73 } else if (Subtarget->isTargetCygMing()) {
74 // Unsupported by now, just quick fallback
75 Flavour = DWARFFlavour::X86_32_Generic;
77 Flavour = DWARFFlavour::X86_32_Generic;
81 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
84 // getX86RegNum - This function maps LLVM register identifiers to their X86
85 // specific numbering, which is used in various places encoding instructions.
87 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
89 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
90 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
91 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
92 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
93 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
95 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
97 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
99 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
102 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
104 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
106 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
108 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
110 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
112 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
114 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
116 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
119 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
120 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
121 return RegNo-X86::ST0;
123 case X86::XMM0: case X86::XMM8: case X86::MM0:
125 case X86::XMM1: case X86::XMM9: case X86::MM1:
127 case X86::XMM2: case X86::XMM10: case X86::MM2:
129 case X86::XMM3: case X86::XMM11: case X86::MM3:
131 case X86::XMM4: case X86::XMM12: case X86::MM4:
133 case X86::XMM5: case X86::XMM13: case X86::MM5:
135 case X86::XMM6: case X86::XMM14: case X86::MM6:
137 case X86::XMM7: case X86::XMM15: case X86::MM7:
141 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
142 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
147 const TargetRegisterClass *
148 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
149 if (RC == &X86::CCRRegClass) {
151 return &X86::GR64RegClass;
153 return &X86::GR32RegClass;
159 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
160 static const unsigned CalleeSavedRegs32Bit[] = {
161 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
164 static const unsigned CalleeSavedRegs32EHRet[] = {
165 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
168 static const unsigned CalleeSavedRegs64Bit[] = {
169 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
172 static const unsigned CalleeSavedRegsWin64[] = {
173 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
174 X86::R12, X86::R13, X86::R14, X86::R15, 0
179 return CalleeSavedRegsWin64;
181 return CalleeSavedRegs64Bit;
184 MachineFrameInfo *MFI = MF->getFrameInfo();
185 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
186 if (MMI && MMI->callsEHReturn())
187 return CalleeSavedRegs32EHRet;
189 return CalleeSavedRegs32Bit;
193 const TargetRegisterClass* const*
194 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
195 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
196 &X86::GR32RegClass, &X86::GR32RegClass,
197 &X86::GR32RegClass, &X86::GR32RegClass, 0
199 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
200 &X86::GR32RegClass, &X86::GR32RegClass,
201 &X86::GR32RegClass, &X86::GR32RegClass,
202 &X86::GR32RegClass, &X86::GR32RegClass, 0
204 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
205 &X86::GR64RegClass, &X86::GR64RegClass,
206 &X86::GR64RegClass, &X86::GR64RegClass,
207 &X86::GR64RegClass, &X86::GR64RegClass, 0
209 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
210 &X86::GR64RegClass, &X86::GR64RegClass,
211 &X86::GR64RegClass, &X86::GR64RegClass,
212 &X86::GR64RegClass, &X86::GR64RegClass,
213 &X86::GR64RegClass, &X86::GR64RegClass, 0
218 return CalleeSavedRegClassesWin64;
220 return CalleeSavedRegClasses64Bit;
223 MachineFrameInfo *MFI = MF->getFrameInfo();
224 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
225 if (MMI && MMI->callsEHReturn())
226 return CalleeSavedRegClasses32EHRet;
228 return CalleeSavedRegClasses32Bit;
233 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
234 BitVector Reserved(getNumRegs());
235 Reserved.set(X86::RSP);
236 Reserved.set(X86::ESP);
237 Reserved.set(X86::SP);
238 Reserved.set(X86::SPL);
240 Reserved.set(X86::RBP);
241 Reserved.set(X86::EBP);
242 Reserved.set(X86::BP);
243 Reserved.set(X86::BPL);
248 //===----------------------------------------------------------------------===//
249 // Stack Frame Processing methods
250 //===----------------------------------------------------------------------===//
252 // hasFP - Return true if the specified function should have a dedicated frame
253 // pointer register. This is true if the function has variable sized allocas or
254 // if frame pointer elimination is disabled.
256 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
257 MachineFrameInfo *MFI = MF.getFrameInfo();
258 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
260 return (NoFramePointerElim ||
261 MFI->hasVarSizedObjects() ||
262 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
263 (MMI && MMI->callsUnwindInit()));
266 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
267 return !MF.getFrameInfo()->hasVarSizedObjects();
270 void X86RegisterInfo::
271 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
272 MachineBasicBlock::iterator I) const {
273 if (!hasReservedCallFrame(MF)) {
274 // If the stack pointer can be changed after prologue, turn the
275 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
276 // adjcallstackdown instruction into 'add ESP, <amt>'
277 // TODO: consider using push / pop instead of sub + store / add
278 MachineInstr *Old = I;
279 uint64_t Amount = Old->getOperand(0).getImm();
281 // We need to keep the stack aligned properly. To do this, we round the
282 // amount of space needed for the outgoing arguments up to the next
283 // alignment boundary.
284 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
286 MachineInstr *New = 0;
287 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
288 New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr)
289 .addReg(StackPtr).addImm(Amount);
291 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
292 // factor out the amount the callee already popped.
293 uint64_t CalleeAmt = Old->getOperand(1).getImm();
296 unsigned Opc = (Amount < 128) ?
297 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
298 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
299 New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount);
303 // Replace the pseudo instruction with a new instruction...
304 if (New) MBB.insert(I, New);
306 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
307 // If we are performing frame pointer elimination and if the callee pops
308 // something off the stack pointer, add it back. We do this until we have
309 // more advanced stack pointer tracking ability.
310 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
311 unsigned Opc = (CalleeAmt < 128) ?
312 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
313 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
315 BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
323 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
324 int SPAdj, RegScavenger *RS) const{
325 assert(SPAdj == 0 && "Unexpected");
328 MachineInstr &MI = *II;
329 MachineFunction &MF = *MI.getParent()->getParent();
330 while (!MI.getOperand(i).isFrameIndex()) {
332 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
335 int FrameIndex = MI.getOperand(i).getIndex();
336 // This must be part of a four operand memory reference. Replace the
337 // FrameIndex with base register with EBP. Add an offset to the offset.
338 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false);
340 // Now add the frame object offset to the offset from EBP.
341 int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
342 MI.getOperand(i+3).getImm()+SlotSize;
345 Offset += MF.getFrameInfo()->getStackSize();
347 Offset += SlotSize; // Skip the saved EBP
348 // Skip the RETADDR move area
349 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
350 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
351 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
354 MI.getOperand(i+3).ChangeToImmediate(Offset);
358 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
359 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
360 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
361 if (TailCallReturnAddrDelta < 0) {
362 // create RETURNADDR area
372 CreateFixedObject(-TailCallReturnAddrDelta,
373 (-1*SlotSize)+TailCallReturnAddrDelta);
376 assert((TailCallReturnAddrDelta <= 0) &&
377 "The Delta should always be zero or negative");
378 // Create a frame entry for the EBP register that must be saved.
379 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
381 TailCallReturnAddrDelta);
382 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
383 "Slot for EBP register must be last in order to be found!");
387 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
388 /// stack pointer by a constant value.
390 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
391 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
392 const TargetInstrInfo &TII) {
393 bool isSub = NumBytes < 0;
394 uint64_t Offset = isSub ? -NumBytes : NumBytes;
397 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
398 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
400 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
401 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
402 uint64_t Chunk = (1LL << 31) - 1;
405 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
406 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
411 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
413 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
414 unsigned StackPtr, uint64_t *NumBytes = NULL) {
415 if (MBBI == MBB.begin()) return;
417 MachineBasicBlock::iterator PI = prior(MBBI);
418 unsigned Opc = PI->getOpcode();
419 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
420 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
421 PI->getOperand(0).getReg() == StackPtr) {
423 *NumBytes += PI->getOperand(2).getImm();
425 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
426 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
427 PI->getOperand(0).getReg() == StackPtr) {
429 *NumBytes -= PI->getOperand(2).getImm();
434 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
436 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
437 MachineBasicBlock::iterator &MBBI,
438 unsigned StackPtr, uint64_t *NumBytes = NULL) {
441 if (MBBI == MBB.end()) return;
443 MachineBasicBlock::iterator NI = next(MBBI);
444 if (NI == MBB.end()) return;
446 unsigned Opc = NI->getOpcode();
447 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
448 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
449 NI->getOperand(0).getReg() == StackPtr) {
451 *NumBytes -= NI->getOperand(2).getImm();
454 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
455 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
456 NI->getOperand(0).getReg() == StackPtr) {
458 *NumBytes += NI->getOperand(2).getImm();
464 /// mergeSPUpdates - Checks the instruction before/after the passed
465 /// instruction. If it is an ADD/SUB instruction it is deleted
466 /// argument and the stack adjustment is returned as a positive value for ADD
467 /// and a negative for SUB.
468 static int mergeSPUpdates(MachineBasicBlock &MBB,
469 MachineBasicBlock::iterator &MBBI,
471 bool doMergeWithPrevious) {
473 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
474 (!doMergeWithPrevious && MBBI == MBB.end()))
479 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
480 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
481 unsigned Opc = PI->getOpcode();
482 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
483 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
484 PI->getOperand(0).getReg() == StackPtr){
485 Offset += PI->getOperand(2).getImm();
487 if (!doMergeWithPrevious) MBBI = NI;
488 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
489 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
490 PI->getOperand(0).getReg() == StackPtr) {
491 Offset -= PI->getOperand(2).getImm();
493 if (!doMergeWithPrevious) MBBI = NI;
499 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
500 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
501 MachineFrameInfo *MFI = MF.getFrameInfo();
502 const Function* Fn = MF.getFunction();
503 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
504 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
505 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
506 MachineBasicBlock::iterator MBBI = MBB.begin();
507 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
508 !Fn->doesNotThrow() ||
509 UnwindTablesMandatory;
511 // Prepare for frame info.
512 unsigned FrameLabelId = 0;
514 // Get the number of bytes to allocate from the FrameInfo.
515 uint64_t StackSize = MFI->getStackSize();
516 // Add RETADDR move area to callee saved frame size.
517 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
518 if (TailCallReturnAddrDelta < 0)
519 X86FI->setCalleeSavedFrameSize(
520 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
521 uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
523 // Insert stack pointer adjustment for later moving of return addr. Only
524 // applies to tail call optimized functions where the callee argument stack
525 // size is bigger than the callers.
526 if (TailCallReturnAddrDelta < 0) {
527 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
528 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
532 // Get the offset of the stack slot for the EBP register... which is
533 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
534 // Update the frame offset adjustment.
535 MFI->setOffsetAdjustment(SlotSize-NumBytes);
537 // Save EBP into the appropriate stack slot...
538 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
540 NumBytes -= SlotSize;
542 if (needsFrameMoves) {
543 // Mark effective beginning of when frame pointer becomes valid.
544 FrameLabelId = MMI->NextLabelID();
545 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
548 // Update EBP with the new base value...
549 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
553 unsigned ReadyLabelId = 0;
554 if (needsFrameMoves) {
555 // Mark effective beginning of when frame pointer is ready.
556 ReadyLabelId = MMI->NextLabelID();
557 BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
560 // Skip the callee-saved push instructions.
561 while (MBBI != MBB.end() &&
562 (MBBI->getOpcode() == X86::PUSH32r ||
563 MBBI->getOpcode() == X86::PUSH64r))
566 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
567 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
568 // Check, whether EAX is livein for this function
569 bool isEAXAlive = false;
570 for (MachineRegisterInfo::livein_iterator
571 II = MF.getRegInfo().livein_begin(),
572 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
573 unsigned Reg = II->first;
574 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
575 Reg == X86::AH || Reg == X86::AL);
578 // Function prologue calls _alloca to probe the stack when allocating
579 // more than 4k bytes in one go. Touching the stack at 4K increments is
580 // necessary to ensure that the guard pages used by the OS virtual memory
581 // manager are allocated in correct sequence.
583 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
584 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
585 .addExternalSymbol("_alloca");
588 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
589 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
590 // allocated bytes for EAX.
591 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
592 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
593 .addExternalSymbol("_alloca");
595 MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX),
596 StackPtr, NumBytes-4);
597 MBB.insert(MBBI, MI);
600 // If there is an SUB32ri of ESP immediately before this instruction,
601 // merge the two. This can be the case when tail call elimination is
602 // enabled and the callee has more arguments then the caller.
603 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
604 // If there is an ADD32ri or SUB32ri of ESP immediately after this
605 // instruction, merge the two instructions.
606 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
609 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
613 if (needsFrameMoves) {
614 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
615 const TargetData *TD = MF.getTarget().getTargetData();
617 // Calculate amount of bytes used for return address storing
619 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
620 TargetFrameInfo::StackGrowsUp ?
621 TD->getPointerSize() : -TD->getPointerSize());
624 // Show update of SP.
627 MachineLocation SPDst(MachineLocation::VirtualFP);
628 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
629 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
631 MachineLocation SPDst(MachineLocation::VirtualFP);
632 MachineLocation SPSrc(MachineLocation::VirtualFP,
633 -StackSize+stackGrowth);
634 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
637 //FIXME: Verify & implement for FP
638 MachineLocation SPDst(StackPtr);
639 MachineLocation SPSrc(StackPtr, stackGrowth);
640 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
643 // Add callee saved registers to move list.
644 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
646 // FIXME: This is dirty hack. The code itself is pretty mess right now.
647 // It should be rewritten from scratch and generalized sometimes.
649 // Determine maximum offset (minumum due to stack growth)
650 int64_t MaxOffset = 0;
651 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
652 MaxOffset = std::min(MaxOffset,
653 MFI->getObjectOffset(CSI[I].getFrameIdx()));
656 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
657 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
658 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
659 unsigned Reg = CSI[I].getReg();
660 Offset = (MaxOffset-Offset+saveAreaOffset);
661 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
662 MachineLocation CSSrc(Reg);
663 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
668 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
669 MachineLocation FPSrc(FramePtr);
670 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
673 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
674 MachineLocation FPSrc(MachineLocation::VirtualFP);
675 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
678 // If it's main() on Cygwin\Mingw32 we should align stack as well
679 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
680 Subtarget->isTargetCygMing()) {
681 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
682 .addReg(X86::ESP).addImm(-StackAlign);
685 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
686 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
690 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
691 MachineBasicBlock &MBB) const {
692 const MachineFrameInfo *MFI = MF.getFrameInfo();
693 const Function* Fn = MF.getFunction();
694 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
695 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
696 MachineBasicBlock::iterator MBBI = prior(MBB.end());
697 unsigned RetOpcode = MBBI->getOpcode();
702 case X86::TCRETURNdi:
703 case X86::TCRETURNri:
704 case X86::TCRETURNri64:
705 case X86::TCRETURNdi64:
709 case X86::TAILJMPm: break; // These are ok
711 assert(0 && "Can only insert epilog into returning blocks");
714 // Get the number of bytes to allocate from the FrameInfo
715 uint64_t StackSize = MFI->getStackSize();
716 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
717 uint64_t NumBytes = StackSize - CSSize;
721 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
722 NumBytes -= SlotSize;
725 // Skip the callee-saved pop instructions.
726 while (MBBI != MBB.begin()) {
727 MachineBasicBlock::iterator PI = prior(MBBI);
728 unsigned Opc = PI->getOpcode();
729 if (Opc != X86::POP32r && Opc != X86::POP64r &&
730 !PI->getDesc().isTerminator())
735 // If there is an ADD32ri or SUB32ri of ESP immediately before this
736 // instruction, merge the two instructions.
737 if (NumBytes || MFI->hasVarSizedObjects())
738 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
740 // If dynamic alloca is used, then reset esp to point to the last callee-saved
741 // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we
742 // aligned stack in the prologue, - revert stack changes back. Note: we're
743 // assuming, that frame pointer was forced for main()
744 if (MFI->hasVarSizedObjects() ||
745 (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
746 Subtarget->isTargetCygMing())) {
747 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
749 MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr),
751 MBB.insert(MBBI, MI);
753 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
759 // adjust stack pointer back: ESP += numbytes
761 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
763 // We're returning from function via eh_return.
764 if (RetOpcode == X86::EH_RETURN) {
765 MBBI = prior(MBB.end());
766 MachineOperand &DestAddr = MBBI->getOperand(0);
767 assert(DestAddr.isRegister() && "Offset should be in register!");
768 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr).
769 addReg(DestAddr.getReg());
770 // Tail call return: adjust the stack pointer and jump to callee
771 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
772 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
773 MBBI = prior(MBB.end());
774 MachineOperand &JumpTarget = MBBI->getOperand(0);
775 MachineOperand &StackAdjust = MBBI->getOperand(1);
776 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
778 // Adjust stack pointer.
779 int StackAdj = StackAdjust.getImm();
780 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
782 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
783 // Incoporate the retaddr area.
784 Offset = StackAdj-MaxTCDelta;
785 assert(Offset >= 0 && "Offset should never be negative");
787 // Check for possible merge with preceeding ADD instruction.
788 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
789 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
791 // Jump to label or value in register.
792 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
793 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
794 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
795 else if (RetOpcode== X86::TCRETURNri64) {
796 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
798 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
799 // Delete the pseudo instruction TCRETURN.
801 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
802 (X86FI->getTCReturnAddrDelta() < 0)) {
803 // Add the return addr area delta back since we are not tail calling.
804 int delta = -1*X86FI->getTCReturnAddrDelta();
805 MBBI = prior(MBB.end());
806 // Check for possible merge with preceeding ADD instruction.
807 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
808 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
812 unsigned X86RegisterInfo::getRARegister() const {
814 return X86::RIP; // Should have dwarf #16
816 return X86::EIP; // Should have dwarf #8
819 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
820 return hasFP(MF) ? FramePtr : StackPtr;
824 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
825 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
827 return Offset + MF.getFrameInfo()->getStackSize();
829 Offset += SlotSize; // Skip the saved EBP
830 // Skip the RETADDR move area
831 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
832 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
833 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
837 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
839 // Calculate amount of bytes used for return address storing
840 int stackGrowth = (Is64Bit ? -8 : -4);
842 // Initial state of the frame pointer is esp+4.
843 MachineLocation Dst(MachineLocation::VirtualFP);
844 MachineLocation Src(StackPtr, stackGrowth);
845 Moves.push_back(MachineMove(0, Dst, Src));
847 // Add return address to move list
848 MachineLocation CSDst(StackPtr, stackGrowth);
849 MachineLocation CSSrc(getRARegister());
850 Moves.push_back(MachineMove(0, CSDst, CSSrc));
853 unsigned X86RegisterInfo::getEHExceptionRegister() const {
854 assert(0 && "What is the exception register");
858 unsigned X86RegisterInfo::getEHHandlerRegister() const {
859 assert(0 && "What is the exception handler register");
864 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
871 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
873 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
875 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
877 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
883 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
885 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
887 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
889 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
891 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
893 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
895 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
897 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
899 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
901 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
903 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
905 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
907 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
909 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
911 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
913 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
920 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
922 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
924 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
926 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
928 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
930 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
932 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
934 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
936 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
938 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
940 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
942 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
944 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
946 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
948 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
950 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
956 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
958 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
960 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
962 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
964 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
966 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
968 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
970 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
972 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
974 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
976 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
978 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
980 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
982 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
984 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
986 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
992 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
994 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
996 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
998 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1000 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1002 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1004 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1006 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1008 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1010 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1012 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1014 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1016 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1018 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1020 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1022 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1031 #include "X86GenRegisterInfo.inc"