1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
70 /// specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 /// getX86RegNum - This function maps LLVM register identifiers to their X86
93 /// specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
189 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
190 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
195 const TargetRegisterClass *
196 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
197 const TargetRegisterClass *B,
198 unsigned SubIdx) const {
202 if (B == &X86::GR8RegClass) {
203 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
205 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
206 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
207 A == &X86::GR64_NOREXRegClass ||
208 A == &X86::GR64_NOSPRegClass ||
209 A == &X86::GR64_NOREX_NOSPRegClass)
210 return &X86::GR64_ABCDRegClass;
211 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
212 A == &X86::GR32_NOREXRegClass ||
213 A == &X86::GR32_NOSPRegClass)
214 return &X86::GR32_ABCDRegClass;
215 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
216 A == &X86::GR16_NOREXRegClass)
217 return &X86::GR16_ABCDRegClass;
218 } else if (B == &X86::GR8_NOREXRegClass) {
219 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
221 return &X86::GR64_NOREXRegClass;
222 else if (A == &X86::GR64_ABCDRegClass)
223 return &X86::GR64_ABCDRegClass;
224 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
225 A == &X86::GR32_NOSPRegClass)
226 return &X86::GR32_NOREXRegClass;
227 else if (A == &X86::GR32_ABCDRegClass)
228 return &X86::GR32_ABCDRegClass;
229 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
230 return &X86::GR16_NOREXRegClass;
231 else if (A == &X86::GR16_ABCDRegClass)
232 return &X86::GR16_ABCDRegClass;
235 case X86::sub_8bit_hi:
236 if (B == &X86::GR8_ABCD_HRegClass) {
237 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
238 A == &X86::GR64_NOREXRegClass ||
239 A == &X86::GR64_NOSPRegClass ||
240 A == &X86::GR64_NOREX_NOSPRegClass)
241 return &X86::GR64_ABCDRegClass;
242 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
243 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
244 return &X86::GR32_ABCDRegClass;
245 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
246 A == &X86::GR16_NOREXRegClass)
247 return &X86::GR16_ABCDRegClass;
251 if (B == &X86::GR16RegClass) {
252 if (A->getSize() == 4 || A->getSize() == 8)
254 } else if (B == &X86::GR16_ABCDRegClass) {
255 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
256 A == &X86::GR64_NOREXRegClass ||
257 A == &X86::GR64_NOSPRegClass ||
258 A == &X86::GR64_NOREX_NOSPRegClass)
259 return &X86::GR64_ABCDRegClass;
260 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
261 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
262 return &X86::GR32_ABCDRegClass;
263 } else if (B == &X86::GR16_NOREXRegClass) {
264 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
265 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
266 return &X86::GR64_NOREXRegClass;
267 else if (A == &X86::GR64_ABCDRegClass)
268 return &X86::GR64_ABCDRegClass;
269 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
270 A == &X86::GR32_NOSPRegClass)
271 return &X86::GR32_NOREXRegClass;
272 else if (A == &X86::GR32_ABCDRegClass)
273 return &X86::GR64_ABCDRegClass;
277 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
278 if (A->getSize() == 8)
280 } else if (B == &X86::GR32_ABCDRegClass) {
281 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
282 A == &X86::GR64_NOREXRegClass ||
283 A == &X86::GR64_NOSPRegClass ||
284 A == &X86::GR64_NOREX_NOSPRegClass)
285 return &X86::GR64_ABCDRegClass;
286 } else if (B == &X86::GR32_NOREXRegClass) {
287 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
288 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
289 return &X86::GR64_NOREXRegClass;
290 else if (A == &X86::GR64_ABCDRegClass)
291 return &X86::GR64_ABCDRegClass;
295 if (B == &X86::FR32RegClass)
299 if (B == &X86::FR64RegClass)
303 if (B == &X86::VR128RegClass)
310 const TargetRegisterClass *
311 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
313 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
314 case 0: // Normal GPRs.
315 if (TM.getSubtarget<X86Subtarget>().is64Bit())
316 return &X86::GR64RegClass;
317 return &X86::GR32RegClass;
318 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
319 if (TM.getSubtarget<X86Subtarget>().is64Bit())
320 return &X86::GR64_NOSPRegClass;
321 return &X86::GR32_NOSPRegClass;
325 const TargetRegisterClass *
326 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
327 if (RC == &X86::CCRRegClass) {
329 return &X86::GR64RegClass;
331 return &X86::GR32RegClass;
337 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
338 bool callsEHReturn = false;
339 bool ghcCall = false;
342 callsEHReturn = MF->getMMI().callsEHReturn();
343 const Function *F = MF->getFunction();
344 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
347 static const unsigned GhcCalleeSavedRegs[] = {
351 static const unsigned CalleeSavedRegs32Bit[] = {
352 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
355 static const unsigned CalleeSavedRegs32EHRet[] = {
356 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
359 static const unsigned CalleeSavedRegs64Bit[] = {
360 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
363 static const unsigned CalleeSavedRegs64EHRet[] = {
364 X86::RAX, X86::RDX, X86::RBX, X86::R12,
365 X86::R13, X86::R14, X86::R15, X86::RBP, 0
368 static const unsigned CalleeSavedRegsWin64[] = {
369 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
370 X86::R12, X86::R13, X86::R14, X86::R15,
371 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
372 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
373 X86::XMM14, X86::XMM15, 0
377 return GhcCalleeSavedRegs;
378 } else if (Is64Bit) {
380 return CalleeSavedRegsWin64;
382 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
384 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
388 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
389 BitVector Reserved(getNumRegs());
390 // Set the stack-pointer register and its aliases as reserved.
391 Reserved.set(X86::RSP);
392 Reserved.set(X86::ESP);
393 Reserved.set(X86::SP);
394 Reserved.set(X86::SPL);
396 // Set the instruction pointer register and its aliases as reserved.
397 Reserved.set(X86::RIP);
398 Reserved.set(X86::EIP);
399 Reserved.set(X86::IP);
401 // Set the frame-pointer register and its aliases as reserved if needed.
403 Reserved.set(X86::RBP);
404 Reserved.set(X86::EBP);
405 Reserved.set(X86::BP);
406 Reserved.set(X86::BPL);
409 // Mark the x87 stack registers as reserved, since they don't behave normally
410 // with respect to liveness. We don't fully model the effects of x87 stack
411 // pushes and pops after stackification.
412 Reserved.set(X86::ST0);
413 Reserved.set(X86::ST1);
414 Reserved.set(X86::ST2);
415 Reserved.set(X86::ST3);
416 Reserved.set(X86::ST4);
417 Reserved.set(X86::ST5);
418 Reserved.set(X86::ST6);
419 Reserved.set(X86::ST7);
423 //===----------------------------------------------------------------------===//
424 // Stack Frame Processing methods
425 //===----------------------------------------------------------------------===//
427 /// hasFP - Return true if the specified function should have a dedicated frame
428 /// pointer register. This is true if the function has variable sized allocas
429 /// or if frame pointer elimination is disabled.
430 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
431 const MachineFrameInfo *MFI = MF.getFrameInfo();
432 const MachineModuleInfo &MMI = MF.getMMI();
434 return (DisableFramePointerElim(MF) ||
435 needsStackRealignment(MF) ||
436 MFI->hasVarSizedObjects() ||
437 MFI->isFrameAddressTaken() ||
438 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
439 MMI.callsUnwindInit());
442 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
443 const MachineFrameInfo *MFI = MF.getFrameInfo();
444 return (RealignStack &&
445 !MFI->hasVarSizedObjects());
448 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
449 const MachineFrameInfo *MFI = MF.getFrameInfo();
450 const Function *F = MF.getFunction();
451 bool requiresRealignment =
452 RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
453 F->hasFnAttr(Attribute::StackAlignment));
455 // FIXME: Currently we don't support stack realignment for functions with
456 // variable-sized allocas.
457 // FIXME: Temporary disable the error - it seems to be too conservative.
458 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
460 "Stack realignment in presense of dynamic allocas is not supported");
462 return (requiresRealignment && !MFI->hasVarSizedObjects());
465 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
466 return !MF.getFrameInfo()->hasVarSizedObjects();
469 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
470 int &FrameIdx) const {
471 if (Reg == FramePtr && hasFP(MF)) {
472 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
479 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
480 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
481 const MachineFrameInfo *MFI = MF.getFrameInfo();
482 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
483 uint64_t StackSize = MFI->getStackSize();
485 if (needsStackRealignment(MF)) {
487 // Skip the saved EBP.
490 unsigned Align = MFI->getObjectAlignment(FI);
491 assert((-(Offset + StackSize)) % Align == 0);
493 return Offset + StackSize;
495 // FIXME: Support tail calls
498 return Offset + StackSize;
500 // Skip the saved EBP.
503 // Skip the RETADDR move area
504 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
505 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
506 if (TailCallReturnAddrDelta < 0)
507 Offset -= TailCallReturnAddrDelta;
513 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
516 return X86::SUB64ri8;
517 return X86::SUB64ri32;
520 return X86::SUB32ri8;
525 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
528 return X86::ADD64ri8;
529 return X86::ADD64ri32;
532 return X86::ADD32ri8;
537 void X86RegisterInfo::
538 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator I) const {
540 if (!hasReservedCallFrame(MF)) {
541 // If the stack pointer can be changed after prologue, turn the
542 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
543 // adjcallstackdown instruction into 'add ESP, <amt>'
544 // TODO: consider using push / pop instead of sub + store / add
545 MachineInstr *Old = I;
546 uint64_t Amount = Old->getOperand(0).getImm();
548 // We need to keep the stack aligned properly. To do this, we round the
549 // amount of space needed for the outgoing arguments up to the next
550 // alignment boundary.
551 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
553 MachineInstr *New = 0;
554 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
555 New = BuildMI(MF, Old->getDebugLoc(),
556 TII.get(getSUBriOpcode(Is64Bit, Amount)),
561 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
563 // Factor out the amount the callee already popped.
564 uint64_t CalleeAmt = Old->getOperand(1).getImm();
568 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
569 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
576 // The EFLAGS implicit def is dead.
577 New->getOperand(3).setIsDead();
579 // Replace the pseudo instruction with a new instruction.
583 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
584 // If we are performing frame pointer elimination and if the callee pops
585 // something off the stack pointer, add it back. We do this until we have
586 // more advanced stack pointer tracking ability.
587 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
588 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
589 MachineInstr *Old = I;
591 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
596 // The EFLAGS implicit def is dead.
597 New->getOperand(3).setIsDead();
606 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
607 int SPAdj, FrameIndexValue *Value,
608 RegScavenger *RS) const{
609 assert(SPAdj == 0 && "Unexpected");
612 MachineInstr &MI = *II;
613 MachineFunction &MF = *MI.getParent()->getParent();
615 while (!MI.getOperand(i).isFI()) {
617 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
620 int FrameIndex = MI.getOperand(i).getIndex();
623 unsigned Opc = MI.getOpcode();
624 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
625 if (needsStackRealignment(MF))
626 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
630 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
632 // This must be part of a four operand memory reference. Replace the
633 // FrameIndex with base register with EBP. Add an offset to the offset.
634 MI.getOperand(i).ChangeToRegister(BasePtr, false);
636 // Now add the frame object offset to the offset from EBP.
639 // Tail call jmp happens after FP is popped.
640 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
641 const MachineFrameInfo *MFI = MF.getFrameInfo();
642 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
644 FIOffset = getFrameIndexOffset(MF, FrameIndex);
646 if (MI.getOperand(i+3).isImm()) {
647 // Offset is a 32-bit integer.
648 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
649 MI.getOperand(i + 3).ChangeToImmediate(Offset);
651 // Offset is symbolic. This is extremely rare.
652 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
653 MI.getOperand(i+3).setOffset(Offset);
659 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
660 RegScavenger *RS) const {
661 MachineFrameInfo *MFI = MF.getFrameInfo();
663 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
664 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
666 if (TailCallReturnAddrDelta < 0) {
667 // create RETURNADDR area
676 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
677 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
681 assert((TailCallReturnAddrDelta <= 0) &&
682 "The Delta should always be zero or negative");
683 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
685 // Create a frame entry for the EBP register that must be saved.
686 int FrameIdx = MFI->CreateFixedObject(SlotSize,
688 TFI.getOffsetOfLocalArea() +
689 TailCallReturnAddrDelta,
691 assert(FrameIdx == MFI->getObjectIndexBegin() &&
692 "Slot for EBP register must be last in order to be found!");
697 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
698 /// stack pointer by a constant value.
700 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
701 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
702 const TargetInstrInfo &TII) {
703 bool isSub = NumBytes < 0;
704 uint64_t Offset = isSub ? -NumBytes : NumBytes;
705 unsigned Opc = isSub ?
706 getSUBriOpcode(Is64Bit, Offset) :
707 getADDriOpcode(Is64Bit, Offset);
708 uint64_t Chunk = (1LL << 31) - 1;
709 DebugLoc DL = MBB.findDebugLoc(MBBI);
712 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
714 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
717 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
722 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
724 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
725 unsigned StackPtr, uint64_t *NumBytes = NULL) {
726 if (MBBI == MBB.begin()) return;
728 MachineBasicBlock::iterator PI = prior(MBBI);
729 unsigned Opc = PI->getOpcode();
730 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
731 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
732 PI->getOperand(0).getReg() == StackPtr) {
734 *NumBytes += PI->getOperand(2).getImm();
736 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
737 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
738 PI->getOperand(0).getReg() == StackPtr) {
740 *NumBytes -= PI->getOperand(2).getImm();
745 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
747 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
748 MachineBasicBlock::iterator &MBBI,
749 unsigned StackPtr, uint64_t *NumBytes = NULL) {
750 // FIXME: THIS ISN'T RUN!!!
753 if (MBBI == MBB.end()) return;
755 MachineBasicBlock::iterator NI = llvm::next(MBBI);
756 if (NI == MBB.end()) return;
758 unsigned Opc = NI->getOpcode();
759 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
760 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
761 NI->getOperand(0).getReg() == StackPtr) {
763 *NumBytes -= NI->getOperand(2).getImm();
766 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
767 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
768 NI->getOperand(0).getReg() == StackPtr) {
770 *NumBytes += NI->getOperand(2).getImm();
776 /// mergeSPUpdates - Checks the instruction before/after the passed
777 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
778 /// stack adjustment is returned as a positive value for ADD and a negative for
780 static int mergeSPUpdates(MachineBasicBlock &MBB,
781 MachineBasicBlock::iterator &MBBI,
783 bool doMergeWithPrevious) {
784 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
785 (!doMergeWithPrevious && MBBI == MBB.end()))
788 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
789 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
790 unsigned Opc = PI->getOpcode();
793 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
794 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
795 PI->getOperand(0).getReg() == StackPtr){
796 Offset += PI->getOperand(2).getImm();
798 if (!doMergeWithPrevious) MBBI = NI;
799 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
800 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
801 PI->getOperand(0).getReg() == StackPtr) {
802 Offset -= PI->getOperand(2).getImm();
804 if (!doMergeWithPrevious) MBBI = NI;
810 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
812 unsigned FramePtr) const {
813 MachineFrameInfo *MFI = MF.getFrameInfo();
814 MachineModuleInfo &MMI = MF.getMMI();
816 // Add callee saved registers to move list.
817 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
818 if (CSI.empty()) return;
820 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
821 const TargetData *TD = MF.getTarget().getTargetData();
822 bool HasFP = hasFP(MF);
824 // Calculate amount of bytes used for return address storing.
826 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
827 TargetFrameInfo::StackGrowsUp ?
828 TD->getPointerSize() : -TD->getPointerSize());
830 // FIXME: This is dirty hack. The code itself is pretty mess right now.
831 // It should be rewritten from scratch and generalized sometimes.
833 // Determine maximum offset (minumum due to stack growth).
834 int64_t MaxOffset = 0;
835 for (std::vector<CalleeSavedInfo>::const_iterator
836 I = CSI.begin(), E = CSI.end(); I != E; ++I)
837 MaxOffset = std::min(MaxOffset,
838 MFI->getObjectOffset(I->getFrameIdx()));
840 // Calculate offsets.
841 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
842 for (std::vector<CalleeSavedInfo>::const_iterator
843 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
844 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
845 unsigned Reg = I->getReg();
846 Offset = MaxOffset - Offset + saveAreaOffset;
848 // Don't output a new machine move if we're re-saving the frame
849 // pointer. This happens when the PrologEpilogInserter has inserted an extra
850 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
851 // generates one when frame pointers are used. If we generate a "machine
852 // move" for this extra "PUSH", the linker will lose track of the fact that
853 // the frame pointer should have the value of the first "PUSH" when it's
856 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
857 // another bug. I.e., one where we generate a prolog like this:
865 // The immediate re-push of EBP is unnecessary. At the least, it's an
866 // optimization bug. EBP can be used as a scratch register in certain
867 // cases, but probably not when we have a frame pointer.
868 if (HasFP && FramePtr == Reg)
871 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
872 MachineLocation CSSrc(Reg);
873 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
877 /// emitPrologue - Push callee-saved registers onto the stack, which
878 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
879 /// space for local variables. Also emit labels used by the exception handler to
880 /// generate the exception handling frames.
881 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
882 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
883 MachineBasicBlock::iterator MBBI = MBB.begin();
884 MachineFrameInfo *MFI = MF.getFrameInfo();
885 const Function *Fn = MF.getFunction();
886 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
887 MachineModuleInfo &MMI = MF.getMMI();
888 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
889 bool needsFrameMoves = MMI.hasDebugInfo() ||
890 !Fn->doesNotThrow() || UnwindTablesMandatory;
891 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
892 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
893 bool HasFP = hasFP(MF);
896 // Add RETADDR move area to callee saved frame size.
897 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
898 if (TailCallReturnAddrDelta < 0)
899 X86FI->setCalleeSavedFrameSize(
900 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
902 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
903 // function, and use up to 128 bytes of stack space, don't have a frame
904 // pointer, calls, or dynamic alloca then we do not need to adjust the
905 // stack pointer (we fit in the Red Zone).
906 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
907 !needsStackRealignment(MF) &&
908 !MFI->hasVarSizedObjects() && // No dynamic alloca.
909 !MFI->adjustsStack() && // No calls.
910 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
911 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
912 if (HasFP) MinSize += SlotSize;
913 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
914 MFI->setStackSize(StackSize);
915 } else if (Subtarget->isTargetWin64()) {
916 // We need to always allocate 32 bytes as register spill area.
917 // FIXME: We might reuse these 32 bytes for leaf functions.
919 MFI->setStackSize(StackSize);
922 // Insert stack pointer adjustment for later moving of return addr. Only
923 // applies to tail call optimized functions where the callee argument stack
924 // size is bigger than the callers.
925 if (TailCallReturnAddrDelta < 0) {
927 BuildMI(MBB, MBBI, DL,
928 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
931 .addImm(-TailCallReturnAddrDelta);
932 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
935 // Mapping for machine moves:
937 // DST: VirtualFP AND
938 // SRC: VirtualFP => DW_CFA_def_cfa_offset
939 // ELSE => DW_CFA_def_cfa
941 // SRC: VirtualFP AND
942 // DST: Register => DW_CFA_def_cfa_register
945 // OFFSET < 0 => DW_CFA_offset_extended_sf
946 // REG < 64 => DW_CFA_offset + Reg
947 // ELSE => DW_CFA_offset_extended
949 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
950 const TargetData *TD = MF.getTarget().getTargetData();
951 uint64_t NumBytes = 0;
952 int stackGrowth = -TD->getPointerSize();
955 // Calculate required stack adjustment.
956 uint64_t FrameSize = StackSize - SlotSize;
957 if (needsStackRealignment(MF))
958 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
960 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
962 // Get the offset of the stack slot for the EBP register, which is
963 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
964 // Update the frame offset adjustment.
965 MFI->setOffsetAdjustment(-NumBytes);
967 // Save EBP/RBP into the appropriate stack slot.
968 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
969 .addReg(FramePtr, RegState::Kill);
971 if (needsFrameMoves) {
972 // Mark the place where EBP/RBP was saved.
973 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
974 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
976 // Define the current CFA rule to use the provided offset.
978 MachineLocation SPDst(MachineLocation::VirtualFP);
979 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
980 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
982 // FIXME: Verify & implement for FP
983 MachineLocation SPDst(StackPtr);
984 MachineLocation SPSrc(StackPtr, stackGrowth);
985 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
988 // Change the rule for the FramePtr to be an "offset" rule.
989 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
990 MachineLocation FPSrc(FramePtr);
991 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
994 // Update EBP with the new base value...
995 BuildMI(MBB, MBBI, DL,
996 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
999 if (needsFrameMoves) {
1000 // Mark effective beginning of when frame pointer becomes valid.
1001 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1002 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
1004 // Define the current CFA to use the EBP/RBP register.
1005 MachineLocation FPDst(FramePtr);
1006 MachineLocation FPSrc(MachineLocation::VirtualFP);
1007 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1010 // Mark the FramePtr as live-in in every block except the entry.
1011 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1013 I->addLiveIn(FramePtr);
1016 if (needsStackRealignment(MF)) {
1018 BuildMI(MBB, MBBI, DL,
1019 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1020 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1022 // The EFLAGS implicit def is dead.
1023 MI->getOperand(3).setIsDead();
1026 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1029 // Skip the callee-saved push instructions.
1030 bool PushedRegs = false;
1031 int StackOffset = 2 * stackGrowth;
1033 while (MBBI != MBB.end() &&
1034 (MBBI->getOpcode() == X86::PUSH32r ||
1035 MBBI->getOpcode() == X86::PUSH64r)) {
1039 if (!HasFP && needsFrameMoves) {
1040 // Mark callee-saved push instruction.
1041 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1042 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1044 // Define the current CFA rule to use the provided offset.
1045 unsigned Ptr = StackSize ?
1046 MachineLocation::VirtualFP : StackPtr;
1047 MachineLocation SPDst(Ptr);
1048 MachineLocation SPSrc(Ptr, StackOffset);
1049 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1050 StackOffset += stackGrowth;
1054 DL = MBB.findDebugLoc(MBBI);
1056 // Adjust stack pointer: ESP -= numbytes.
1057 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1058 // Check, whether EAX is livein for this function.
1059 bool isEAXAlive = false;
1060 for (MachineRegisterInfo::livein_iterator
1061 II = MF.getRegInfo().livein_begin(),
1062 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1063 unsigned Reg = II->first;
1064 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1065 Reg == X86::AH || Reg == X86::AL);
1068 // Function prologue calls _alloca to probe the stack when allocating more
1069 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1070 // to ensure that the guard pages used by the OS virtual memory manager are
1071 // allocated in correct sequence.
1073 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1075 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1076 .addExternalSymbol("_alloca")
1077 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1080 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1081 .addReg(X86::EAX, RegState::Kill);
1083 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1084 // allocated bytes for EAX.
1085 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1086 .addImm(NumBytes - 4);
1087 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1088 .addExternalSymbol("_alloca")
1089 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1092 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1094 StackPtr, false, NumBytes - 4);
1095 MBB.insert(MBBI, MI);
1097 } else if (NumBytes) {
1098 // If there is an SUB32ri of ESP immediately before this instruction, merge
1099 // the two. This can be the case when tail call elimination is enabled and
1100 // the callee has more arguments then the caller.
1101 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1103 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1104 // instruction, merge the two instructions.
1105 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1108 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1111 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1112 // Mark end of stack pointer adjustment.
1113 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1114 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1116 if (!HasFP && NumBytes) {
1117 // Define the current CFA rule to use the provided offset.
1119 MachineLocation SPDst(MachineLocation::VirtualFP);
1120 MachineLocation SPSrc(MachineLocation::VirtualFP,
1121 -StackSize + stackGrowth);
1122 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1124 // FIXME: Verify & implement for FP
1125 MachineLocation SPDst(StackPtr);
1126 MachineLocation SPSrc(StackPtr, stackGrowth);
1127 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1131 // Emit DWARF info specifying the offsets of the callee-saved registers.
1133 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1137 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1138 MachineBasicBlock &MBB) const {
1139 const MachineFrameInfo *MFI = MF.getFrameInfo();
1140 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1141 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1142 unsigned RetOpcode = MBBI->getOpcode();
1143 DebugLoc DL = MBBI->getDebugLoc();
1145 switch (RetOpcode) {
1147 llvm_unreachable("Can only insert epilog into returning blocks");
1150 case X86::TCRETURNdi:
1151 case X86::TCRETURNri:
1152 case X86::TCRETURNmi:
1153 case X86::TCRETURNdi64:
1154 case X86::TCRETURNri64:
1155 case X86::TCRETURNmi64:
1156 case X86::EH_RETURN:
1157 case X86::EH_RETURN64:
1158 break; // These are ok
1161 // Get the number of bytes to allocate from the FrameInfo.
1162 uint64_t StackSize = MFI->getStackSize();
1163 uint64_t MaxAlign = MFI->getMaxAlignment();
1164 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1165 uint64_t NumBytes = 0;
1168 // Calculate required stack adjustment.
1169 uint64_t FrameSize = StackSize - SlotSize;
1170 if (needsStackRealignment(MF))
1171 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1173 NumBytes = FrameSize - CSSize;
1176 BuildMI(MBB, MBBI, DL,
1177 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1179 NumBytes = StackSize - CSSize;
1182 // Skip the callee-saved pop instructions.
1183 MachineBasicBlock::iterator LastCSPop = MBBI;
1184 while (MBBI != MBB.begin()) {
1185 MachineBasicBlock::iterator PI = prior(MBBI);
1186 unsigned Opc = PI->getOpcode();
1188 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1189 !PI->getDesc().isTerminator())
1195 DL = MBBI->getDebugLoc();
1197 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1198 // instruction, merge the two instructions.
1199 if (NumBytes || MFI->hasVarSizedObjects())
1200 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1202 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1203 // slot before popping them off! Same applies for the case, when stack was
1205 if (needsStackRealignment(MF)) {
1206 // We cannot use LEA here, because stack pointer was realigned. We need to
1207 // deallocate local frame back.
1209 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1210 MBBI = prior(LastCSPop);
1213 BuildMI(MBB, MBBI, DL,
1214 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1215 StackPtr).addReg(FramePtr);
1216 } else if (MFI->hasVarSizedObjects()) {
1218 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1220 addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1221 FramePtr, false, -CSSize);
1222 MBB.insert(MBBI, MI);
1224 BuildMI(MBB, MBBI, DL,
1225 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1228 } else if (NumBytes) {
1229 // Adjust stack pointer back: ESP += numbytes.
1230 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1233 // We're returning from function via eh_return.
1234 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1235 MBBI = prior(MBB.end());
1236 MachineOperand &DestAddr = MBBI->getOperand(0);
1237 assert(DestAddr.isReg() && "Offset should be in register!");
1238 BuildMI(MBB, MBBI, DL,
1239 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1240 StackPtr).addReg(DestAddr.getReg());
1241 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1242 RetOpcode == X86::TCRETURNmi ||
1243 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1244 RetOpcode == X86::TCRETURNmi64) {
1245 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1246 // Tail call return: adjust the stack pointer and jump to callee.
1247 MBBI = prior(MBB.end());
1248 MachineOperand &JumpTarget = MBBI->getOperand(0);
1249 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1250 assert(StackAdjust.isImm() && "Expecting immediate value.");
1252 // Adjust stack pointer.
1253 int StackAdj = StackAdjust.getImm();
1254 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1256 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1258 // Incoporate the retaddr area.
1259 Offset = StackAdj-MaxTCDelta;
1260 assert(Offset >= 0 && "Offset should never be negative");
1263 // Check for possible merge with preceeding ADD instruction.
1264 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1265 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1268 // Jump to label or value in register.
1269 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1270 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1271 ? X86::TAILJMPd : X86::TAILJMPd64)).
1272 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1273 JumpTarget.getTargetFlags());
1274 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1275 MachineInstrBuilder MIB =
1276 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1277 ? X86::TAILJMPm : X86::TAILJMPm64));
1278 for (unsigned i = 0; i != 5; ++i)
1279 MIB.addOperand(MBBI->getOperand(i));
1280 } else if (RetOpcode == X86::TCRETURNri64) {
1281 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1282 addReg(JumpTarget.getReg(), RegState::Kill);
1284 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1285 addReg(JumpTarget.getReg(), RegState::Kill);
1288 MachineInstr *NewMI = prior(MBBI);
1289 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1290 NewMI->addOperand(MBBI->getOperand(i));
1292 // Delete the pseudo instruction TCRETURN.
1294 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1295 (X86FI->getTCReturnAddrDelta() < 0)) {
1296 // Add the return addr area delta back since we are not tail calling.
1297 int delta = -1*X86FI->getTCReturnAddrDelta();
1298 MBBI = prior(MBB.end());
1300 // Check for possible merge with preceeding ADD instruction.
1301 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1302 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1306 unsigned X86RegisterInfo::getRARegister() const {
1307 return Is64Bit ? X86::RIP // Should have dwarf #16.
1308 : X86::EIP; // Should have dwarf #8.
1311 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1312 return hasFP(MF) ? FramePtr : StackPtr;
1316 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1317 // Calculate amount of bytes used for return address storing
1318 int stackGrowth = (Is64Bit ? -8 : -4);
1320 // Initial state of the frame pointer is esp+stackGrowth.
1321 MachineLocation Dst(MachineLocation::VirtualFP);
1322 MachineLocation Src(StackPtr, stackGrowth);
1323 Moves.push_back(MachineMove(0, Dst, Src));
1325 // Add return address to move list
1326 MachineLocation CSDst(StackPtr, stackGrowth);
1327 MachineLocation CSSrc(getRARegister());
1328 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1331 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1332 llvm_unreachable("What is the exception register");
1336 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1337 llvm_unreachable("What is the exception handler register");
1342 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1343 switch (VT.getSimpleVT().SimpleTy) {
1344 default: return Reg;
1349 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1351 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1353 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1355 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1361 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1363 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1365 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1367 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1369 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1371 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1373 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1375 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1377 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1379 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1381 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1383 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1385 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1387 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1389 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1391 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1397 default: return Reg;
1398 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1400 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1402 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1404 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1406 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1408 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1410 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1412 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1414 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1416 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1418 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1420 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1422 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1424 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1426 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1428 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1433 default: return Reg;
1434 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1436 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1438 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1440 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1442 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1444 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1446 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1448 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1450 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1452 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1454 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1456 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1458 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1460 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1462 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1464 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1469 default: return Reg;
1470 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1472 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1474 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1476 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1478 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1480 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1482 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1484 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1486 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1488 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1490 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1492 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1494 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1496 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1498 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1500 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1509 #include "X86GenRegisterInfo.inc"
1512 struct MSAH : public MachineFunctionPass {
1514 MSAH() : MachineFunctionPass(&ID) {}
1516 virtual bool runOnMachineFunction(MachineFunction &MF) {
1517 const X86TargetMachine *TM =
1518 static_cast<const X86TargetMachine *>(&MF.getTarget());
1519 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1520 MachineRegisterInfo &RI = MF.getRegInfo();
1521 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1522 unsigned StackAlignment = X86RI->getStackAlignment();
1524 // Be over-conservative: scan over all vreg defs and find whether vector
1525 // registers are used. If yes, there is a possibility that vector register
1526 // will be spilled and thus require dynamic stack realignment.
1527 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1528 RegNum < RI.getLastVirtReg(); ++RegNum)
1529 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1530 FuncInfo->setReserveFP(true);
1538 virtual const char *getPassName() const {
1539 return "X86 Maximal Stack Alignment Check";
1542 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1543 AU.setPreservesCFG();
1544 MachineFunctionPass::getAnalysisUsage(AU);
1552 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }