1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
70 /// specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 /// getX86RegNum - This function maps LLVM register identifiers to their X86
93 /// specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8:
131 case X86::YMM0: case X86::YMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9:
134 case X86::YMM1: case X86::YMM9: case X86::MM1:
136 case X86::XMM2: case X86::XMM10:
137 case X86::YMM2: case X86::YMM10: case X86::MM2:
139 case X86::XMM3: case X86::XMM11:
140 case X86::YMM3: case X86::YMM11: case X86::MM3:
142 case X86::XMM4: case X86::XMM12:
143 case X86::YMM4: case X86::YMM12: case X86::MM4:
145 case X86::XMM5: case X86::XMM13:
146 case X86::YMM5: case X86::YMM13: case X86::MM5:
148 case X86::XMM6: case X86::XMM14:
149 case X86::YMM6: case X86::YMM14: case X86::MM6:
151 case X86::XMM7: case X86::XMM15:
152 case X86::YMM7: case X86::YMM15: case X86::MM7:
196 // Pseudo index registers are equivalent to a "none"
197 // scaled index (See Intel Manual 2A, table 2-3)
203 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
204 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
209 const TargetRegisterClass *
210 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
211 const TargetRegisterClass *B,
212 unsigned SubIdx) const {
216 if (B == &X86::GR8RegClass) {
217 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
219 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
220 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
221 A == &X86::GR64_NOREXRegClass ||
222 A == &X86::GR64_NOSPRegClass ||
223 A == &X86::GR64_NOREX_NOSPRegClass)
224 return &X86::GR64_ABCDRegClass;
225 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
226 A == &X86::GR32_NOREXRegClass ||
227 A == &X86::GR32_NOSPRegClass)
228 return &X86::GR32_ABCDRegClass;
229 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
230 A == &X86::GR16_NOREXRegClass)
231 return &X86::GR16_ABCDRegClass;
232 } else if (B == &X86::GR8_NOREXRegClass) {
233 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
234 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
235 return &X86::GR64_NOREXRegClass;
236 else if (A == &X86::GR64_ABCDRegClass)
237 return &X86::GR64_ABCDRegClass;
238 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
239 A == &X86::GR32_NOSPRegClass)
240 return &X86::GR32_NOREXRegClass;
241 else if (A == &X86::GR32_ABCDRegClass)
242 return &X86::GR32_ABCDRegClass;
243 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
244 return &X86::GR16_NOREXRegClass;
245 else if (A == &X86::GR16_ABCDRegClass)
246 return &X86::GR16_ABCDRegClass;
249 case X86::sub_8bit_hi:
250 if (B == &X86::GR8_ABCD_HRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
252 A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass ||
254 A == &X86::GR64_NOREX_NOSPRegClass)
255 return &X86::GR64_ABCDRegClass;
256 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
257 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
258 return &X86::GR32_ABCDRegClass;
259 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
260 A == &X86::GR16_NOREXRegClass)
261 return &X86::GR16_ABCDRegClass;
265 if (B == &X86::GR16RegClass) {
266 if (A->getSize() == 4 || A->getSize() == 8)
268 } else if (B == &X86::GR16_ABCDRegClass) {
269 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
270 A == &X86::GR64_NOREXRegClass ||
271 A == &X86::GR64_NOSPRegClass ||
272 A == &X86::GR64_NOREX_NOSPRegClass)
273 return &X86::GR64_ABCDRegClass;
274 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
275 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
276 return &X86::GR32_ABCDRegClass;
277 } else if (B == &X86::GR16_NOREXRegClass) {
278 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
279 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
280 return &X86::GR64_NOREXRegClass;
281 else if (A == &X86::GR64_ABCDRegClass)
282 return &X86::GR64_ABCDRegClass;
283 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
284 A == &X86::GR32_NOSPRegClass)
285 return &X86::GR32_NOREXRegClass;
286 else if (A == &X86::GR32_ABCDRegClass)
287 return &X86::GR64_ABCDRegClass;
291 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
292 if (A->getSize() == 8)
294 } else if (B == &X86::GR32_ABCDRegClass) {
295 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
296 A == &X86::GR64_NOREXRegClass ||
297 A == &X86::GR64_NOSPRegClass ||
298 A == &X86::GR64_NOREX_NOSPRegClass)
299 return &X86::GR64_ABCDRegClass;
300 } else if (B == &X86::GR32_NOREXRegClass) {
301 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
302 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
303 return &X86::GR64_NOREXRegClass;
304 else if (A == &X86::GR64_ABCDRegClass)
305 return &X86::GR64_ABCDRegClass;
309 if (B == &X86::FR32RegClass)
313 if (B == &X86::FR64RegClass)
317 if (B == &X86::VR128RegClass)
324 const TargetRegisterClass *
325 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
327 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
328 case 0: // Normal GPRs.
329 if (TM.getSubtarget<X86Subtarget>().is64Bit())
330 return &X86::GR64RegClass;
331 return &X86::GR32RegClass;
332 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
333 if (TM.getSubtarget<X86Subtarget>().is64Bit())
334 return &X86::GR64_NOSPRegClass;
335 return &X86::GR32_NOSPRegClass;
339 const TargetRegisterClass *
340 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
341 if (RC == &X86::CCRRegClass) {
343 return &X86::GR64RegClass;
345 return &X86::GR32RegClass;
351 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
352 bool callsEHReturn = false;
353 bool ghcCall = false;
356 callsEHReturn = MF->getMMI().callsEHReturn();
357 const Function *F = MF->getFunction();
358 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
361 static const unsigned GhcCalleeSavedRegs[] = {
365 static const unsigned CalleeSavedRegs32Bit[] = {
366 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
369 static const unsigned CalleeSavedRegs32EHRet[] = {
370 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
373 static const unsigned CalleeSavedRegs64Bit[] = {
374 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
377 static const unsigned CalleeSavedRegs64EHRet[] = {
378 X86::RAX, X86::RDX, X86::RBX, X86::R12,
379 X86::R13, X86::R14, X86::R15, X86::RBP, 0
382 static const unsigned CalleeSavedRegsWin64[] = {
383 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
384 X86::R12, X86::R13, X86::R14, X86::R15,
385 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
386 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
387 X86::XMM14, X86::XMM15, 0
391 return GhcCalleeSavedRegs;
392 } else if (Is64Bit) {
394 return CalleeSavedRegsWin64;
396 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
398 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
402 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
403 BitVector Reserved(getNumRegs());
404 // Set the stack-pointer register and its aliases as reserved.
405 Reserved.set(X86::RSP);
406 Reserved.set(X86::ESP);
407 Reserved.set(X86::SP);
408 Reserved.set(X86::SPL);
410 // Set the instruction pointer register and its aliases as reserved.
411 Reserved.set(X86::RIP);
412 Reserved.set(X86::EIP);
413 Reserved.set(X86::IP);
415 // Set the frame-pointer register and its aliases as reserved if needed.
417 Reserved.set(X86::RBP);
418 Reserved.set(X86::EBP);
419 Reserved.set(X86::BP);
420 Reserved.set(X86::BPL);
423 // Mark the x87 stack registers as reserved, since they don't behave normally
424 // with respect to liveness. We don't fully model the effects of x87 stack
425 // pushes and pops after stackification.
426 Reserved.set(X86::ST0);
427 Reserved.set(X86::ST1);
428 Reserved.set(X86::ST2);
429 Reserved.set(X86::ST3);
430 Reserved.set(X86::ST4);
431 Reserved.set(X86::ST5);
432 Reserved.set(X86::ST6);
433 Reserved.set(X86::ST7);
437 //===----------------------------------------------------------------------===//
438 // Stack Frame Processing methods
439 //===----------------------------------------------------------------------===//
441 /// hasFP - Return true if the specified function should have a dedicated frame
442 /// pointer register. This is true if the function has variable sized allocas
443 /// or if frame pointer elimination is disabled.
444 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
445 const MachineFrameInfo *MFI = MF.getFrameInfo();
446 const MachineModuleInfo &MMI = MF.getMMI();
448 return (DisableFramePointerElim(MF) ||
449 needsStackRealignment(MF) ||
450 MFI->hasVarSizedObjects() ||
451 MFI->isFrameAddressTaken() ||
452 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
453 MMI.callsUnwindInit());
456 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
457 const MachineFrameInfo *MFI = MF.getFrameInfo();
458 return (RealignStack &&
459 !MFI->hasVarSizedObjects());
462 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
463 const MachineFrameInfo *MFI = MF.getFrameInfo();
464 const Function *F = MF.getFunction();
465 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
466 F->hasFnAttr(Attribute::StackAlignment));
468 // FIXME: Currently we don't support stack realignment for functions with
469 // variable-sized allocas.
470 // FIXME: It's more complicated than this...
471 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
473 "Stack realignment in presense of dynamic allocas is not supported");
475 return requiresRealignment && canRealignStack(MF);
478 bool X86RegisterInfo::hasReservedCallFrame(const MachineFunction &MF) const {
479 return !MF.getFrameInfo()->hasVarSizedObjects();
482 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
483 unsigned Reg, int &FrameIdx) const {
484 if (Reg == FramePtr && hasFP(MF)) {
485 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
492 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
493 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
494 const MachineFrameInfo *MFI = MF.getFrameInfo();
495 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
496 uint64_t StackSize = MFI->getStackSize();
498 if (needsStackRealignment(MF)) {
500 // Skip the saved EBP.
503 unsigned Align = MFI->getObjectAlignment(FI);
504 assert((-(Offset + StackSize)) % Align == 0);
506 return Offset + StackSize;
508 // FIXME: Support tail calls
511 return Offset + StackSize;
513 // Skip the saved EBP.
516 // Skip the RETADDR move area
517 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
518 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
519 if (TailCallReturnAddrDelta < 0)
520 Offset -= TailCallReturnAddrDelta;
526 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
529 return X86::SUB64ri8;
530 return X86::SUB64ri32;
533 return X86::SUB32ri8;
538 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
541 return X86::ADD64ri8;
542 return X86::ADD64ri32;
545 return X86::ADD32ri8;
550 void X86RegisterInfo::
551 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
552 MachineBasicBlock::iterator I) const {
553 if (!hasReservedCallFrame(MF)) {
554 // If the stack pointer can be changed after prologue, turn the
555 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
556 // adjcallstackdown instruction into 'add ESP, <amt>'
557 // TODO: consider using push / pop instead of sub + store / add
558 MachineInstr *Old = I;
559 uint64_t Amount = Old->getOperand(0).getImm();
561 // We need to keep the stack aligned properly. To do this, we round the
562 // amount of space needed for the outgoing arguments up to the next
563 // alignment boundary.
564 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
566 MachineInstr *New = 0;
567 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
568 New = BuildMI(MF, Old->getDebugLoc(),
569 TII.get(getSUBriOpcode(Is64Bit, Amount)),
574 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
576 // Factor out the amount the callee already popped.
577 uint64_t CalleeAmt = Old->getOperand(1).getImm();
581 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
582 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
589 // The EFLAGS implicit def is dead.
590 New->getOperand(3).setIsDead();
592 // Replace the pseudo instruction with a new instruction.
596 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
597 // If we are performing frame pointer elimination and if the callee pops
598 // something off the stack pointer, add it back. We do this until we have
599 // more advanced stack pointer tracking ability.
600 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
601 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
602 MachineInstr *Old = I;
604 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
609 // The EFLAGS implicit def is dead.
610 New->getOperand(3).setIsDead();
619 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
620 int SPAdj, FrameIndexValue *Value,
621 RegScavenger *RS) const{
622 assert(SPAdj == 0 && "Unexpected");
625 MachineInstr &MI = *II;
626 MachineFunction &MF = *MI.getParent()->getParent();
628 while (!MI.getOperand(i).isFI()) {
630 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
633 int FrameIndex = MI.getOperand(i).getIndex();
636 unsigned Opc = MI.getOpcode();
637 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
638 if (needsStackRealignment(MF))
639 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
643 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
645 // This must be part of a four operand memory reference. Replace the
646 // FrameIndex with base register with EBP. Add an offset to the offset.
647 MI.getOperand(i).ChangeToRegister(BasePtr, false);
649 // Now add the frame object offset to the offset from EBP.
652 // Tail call jmp happens after FP is popped.
653 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
654 const MachineFrameInfo *MFI = MF.getFrameInfo();
655 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
657 FIOffset = getFrameIndexOffset(MF, FrameIndex);
659 if (MI.getOperand(i+3).isImm()) {
660 // Offset is a 32-bit integer.
661 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
662 MI.getOperand(i + 3).ChangeToImmediate(Offset);
664 // Offset is symbolic. This is extremely rare.
665 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
666 MI.getOperand(i+3).setOffset(Offset);
672 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
673 RegScavenger *RS) const {
674 MachineFrameInfo *MFI = MF.getFrameInfo();
676 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
677 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
679 if (TailCallReturnAddrDelta < 0) {
680 // create RETURNADDR area
689 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
690 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
694 assert((TailCallReturnAddrDelta <= 0) &&
695 "The Delta should always be zero or negative");
696 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
698 // Create a frame entry for the EBP register that must be saved.
699 int FrameIdx = MFI->CreateFixedObject(SlotSize,
701 TFI.getOffsetOfLocalArea() +
702 TailCallReturnAddrDelta,
704 assert(FrameIdx == MFI->getObjectIndexBegin() &&
705 "Slot for EBP register must be last in order to be found!");
710 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
711 /// stack pointer by a constant value.
713 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
714 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
715 const TargetInstrInfo &TII) {
716 bool isSub = NumBytes < 0;
717 uint64_t Offset = isSub ? -NumBytes : NumBytes;
718 unsigned Opc = isSub ?
719 getSUBriOpcode(Is64Bit, Offset) :
720 getADDriOpcode(Is64Bit, Offset);
721 uint64_t Chunk = (1LL << 31) - 1;
722 DebugLoc DL = MBB.findDebugLoc(MBBI);
725 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
727 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
730 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
735 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
737 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
738 unsigned StackPtr, uint64_t *NumBytes = NULL) {
739 if (MBBI == MBB.begin()) return;
741 MachineBasicBlock::iterator PI = prior(MBBI);
742 unsigned Opc = PI->getOpcode();
743 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
744 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
745 PI->getOperand(0).getReg() == StackPtr) {
747 *NumBytes += PI->getOperand(2).getImm();
749 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
750 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
751 PI->getOperand(0).getReg() == StackPtr) {
753 *NumBytes -= PI->getOperand(2).getImm();
758 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
760 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
761 MachineBasicBlock::iterator &MBBI,
762 unsigned StackPtr, uint64_t *NumBytes = NULL) {
763 // FIXME: THIS ISN'T RUN!!!
766 if (MBBI == MBB.end()) return;
768 MachineBasicBlock::iterator NI = llvm::next(MBBI);
769 if (NI == MBB.end()) return;
771 unsigned Opc = NI->getOpcode();
772 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
773 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
774 NI->getOperand(0).getReg() == StackPtr) {
776 *NumBytes -= NI->getOperand(2).getImm();
779 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
780 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
781 NI->getOperand(0).getReg() == StackPtr) {
783 *NumBytes += NI->getOperand(2).getImm();
789 /// mergeSPUpdates - Checks the instruction before/after the passed
790 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
791 /// stack adjustment is returned as a positive value for ADD and a negative for
793 static int mergeSPUpdates(MachineBasicBlock &MBB,
794 MachineBasicBlock::iterator &MBBI,
796 bool doMergeWithPrevious) {
797 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
798 (!doMergeWithPrevious && MBBI == MBB.end()))
801 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
802 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
803 unsigned Opc = PI->getOpcode();
806 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
807 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
808 PI->getOperand(0).getReg() == StackPtr){
809 Offset += PI->getOperand(2).getImm();
811 if (!doMergeWithPrevious) MBBI = NI;
812 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
813 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
814 PI->getOperand(0).getReg() == StackPtr) {
815 Offset -= PI->getOperand(2).getImm();
817 if (!doMergeWithPrevious) MBBI = NI;
823 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
825 unsigned FramePtr) const {
826 MachineFrameInfo *MFI = MF.getFrameInfo();
827 MachineModuleInfo &MMI = MF.getMMI();
829 // Add callee saved registers to move list.
830 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
831 if (CSI.empty()) return;
833 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
834 const TargetData *TD = MF.getTarget().getTargetData();
835 bool HasFP = hasFP(MF);
837 // Calculate amount of bytes used for return address storing.
839 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
840 TargetFrameInfo::StackGrowsUp ?
841 TD->getPointerSize() : -TD->getPointerSize());
843 // FIXME: This is dirty hack. The code itself is pretty mess right now.
844 // It should be rewritten from scratch and generalized sometimes.
846 // Determine maximum offset (minumum due to stack growth).
847 int64_t MaxOffset = 0;
848 for (std::vector<CalleeSavedInfo>::const_iterator
849 I = CSI.begin(), E = CSI.end(); I != E; ++I)
850 MaxOffset = std::min(MaxOffset,
851 MFI->getObjectOffset(I->getFrameIdx()));
853 // Calculate offsets.
854 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
855 for (std::vector<CalleeSavedInfo>::const_iterator
856 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
857 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
858 unsigned Reg = I->getReg();
859 Offset = MaxOffset - Offset + saveAreaOffset;
861 // Don't output a new machine move if we're re-saving the frame
862 // pointer. This happens when the PrologEpilogInserter has inserted an extra
863 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
864 // generates one when frame pointers are used. If we generate a "machine
865 // move" for this extra "PUSH", the linker will lose track of the fact that
866 // the frame pointer should have the value of the first "PUSH" when it's
869 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
870 // another bug. I.e., one where we generate a prolog like this:
878 // The immediate re-push of EBP is unnecessary. At the least, it's an
879 // optimization bug. EBP can be used as a scratch register in certain
880 // cases, but probably not when we have a frame pointer.
881 if (HasFP && FramePtr == Reg)
884 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
885 MachineLocation CSSrc(Reg);
886 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
890 /// emitPrologue - Push callee-saved registers onto the stack, which
891 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
892 /// space for local variables. Also emit labels used by the exception handler to
893 /// generate the exception handling frames.
894 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
895 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
896 MachineBasicBlock::iterator MBBI = MBB.begin();
897 MachineFrameInfo *MFI = MF.getFrameInfo();
898 const Function *Fn = MF.getFunction();
899 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
900 MachineModuleInfo &MMI = MF.getMMI();
901 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
902 bool needsFrameMoves = MMI.hasDebugInfo() ||
903 !Fn->doesNotThrow() || UnwindTablesMandatory;
904 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
905 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
906 bool HasFP = hasFP(MF);
909 // Add RETADDR move area to callee saved frame size.
910 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
911 if (TailCallReturnAddrDelta < 0)
912 X86FI->setCalleeSavedFrameSize(
913 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
915 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
916 // function, and use up to 128 bytes of stack space, don't have a frame
917 // pointer, calls, or dynamic alloca then we do not need to adjust the
918 // stack pointer (we fit in the Red Zone).
919 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
920 !needsStackRealignment(MF) &&
921 !MFI->hasVarSizedObjects() && // No dynamic alloca.
922 !MFI->adjustsStack() && // No calls.
923 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
924 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
925 if (HasFP) MinSize += SlotSize;
926 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
927 MFI->setStackSize(StackSize);
928 } else if (Subtarget->isTargetWin64()) {
929 // We need to always allocate 32 bytes as register spill area.
930 // FIXME: We might reuse these 32 bytes for leaf functions.
932 MFI->setStackSize(StackSize);
935 // Insert stack pointer adjustment for later moving of return addr. Only
936 // applies to tail call optimized functions where the callee argument stack
937 // size is bigger than the callers.
938 if (TailCallReturnAddrDelta < 0) {
940 BuildMI(MBB, MBBI, DL,
941 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
944 .addImm(-TailCallReturnAddrDelta);
945 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
948 // Mapping for machine moves:
950 // DST: VirtualFP AND
951 // SRC: VirtualFP => DW_CFA_def_cfa_offset
952 // ELSE => DW_CFA_def_cfa
954 // SRC: VirtualFP AND
955 // DST: Register => DW_CFA_def_cfa_register
958 // OFFSET < 0 => DW_CFA_offset_extended_sf
959 // REG < 64 => DW_CFA_offset + Reg
960 // ELSE => DW_CFA_offset_extended
962 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
963 const TargetData *TD = MF.getTarget().getTargetData();
964 uint64_t NumBytes = 0;
965 int stackGrowth = -TD->getPointerSize();
968 // Calculate required stack adjustment.
969 uint64_t FrameSize = StackSize - SlotSize;
970 if (needsStackRealignment(MF))
971 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
973 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
975 // Get the offset of the stack slot for the EBP register, which is
976 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
977 // Update the frame offset adjustment.
978 MFI->setOffsetAdjustment(-NumBytes);
980 // Save EBP/RBP into the appropriate stack slot.
981 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
982 .addReg(FramePtr, RegState::Kill);
984 if (needsFrameMoves) {
985 // Mark the place where EBP/RBP was saved.
986 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
987 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
989 // Define the current CFA rule to use the provided offset.
991 MachineLocation SPDst(MachineLocation::VirtualFP);
992 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
993 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
995 // FIXME: Verify & implement for FP
996 MachineLocation SPDst(StackPtr);
997 MachineLocation SPSrc(StackPtr, stackGrowth);
998 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1001 // Change the rule for the FramePtr to be an "offset" rule.
1002 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
1003 MachineLocation FPSrc(FramePtr);
1004 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1007 // Update EBP with the new base value...
1008 BuildMI(MBB, MBBI, DL,
1009 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1012 if (needsFrameMoves) {
1013 // Mark effective beginning of when frame pointer becomes valid.
1014 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1015 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel);
1017 // Define the current CFA to use the EBP/RBP register.
1018 MachineLocation FPDst(FramePtr);
1019 MachineLocation FPSrc(MachineLocation::VirtualFP);
1020 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1023 // Mark the FramePtr as live-in in every block except the entry.
1024 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1026 I->addLiveIn(FramePtr);
1029 if (needsStackRealignment(MF)) {
1031 BuildMI(MBB, MBBI, DL,
1032 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1033 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1035 // The EFLAGS implicit def is dead.
1036 MI->getOperand(3).setIsDead();
1039 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1042 // Skip the callee-saved push instructions.
1043 bool PushedRegs = false;
1044 int StackOffset = 2 * stackGrowth;
1046 while (MBBI != MBB.end() &&
1047 (MBBI->getOpcode() == X86::PUSH32r ||
1048 MBBI->getOpcode() == X86::PUSH64r)) {
1052 if (!HasFP && needsFrameMoves) {
1053 // Mark callee-saved push instruction.
1054 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1055 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
1057 // Define the current CFA rule to use the provided offset.
1058 unsigned Ptr = StackSize ?
1059 MachineLocation::VirtualFP : StackPtr;
1060 MachineLocation SPDst(Ptr);
1061 MachineLocation SPSrc(Ptr, StackOffset);
1062 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1063 StackOffset += stackGrowth;
1067 DL = MBB.findDebugLoc(MBBI);
1069 // Adjust stack pointer: ESP -= numbytes.
1070 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1071 // Check, whether EAX is livein for this function.
1072 bool isEAXAlive = false;
1073 for (MachineRegisterInfo::livein_iterator
1074 II = MF.getRegInfo().livein_begin(),
1075 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1076 unsigned Reg = II->first;
1077 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1078 Reg == X86::AH || Reg == X86::AL);
1081 // Function prologue calls _alloca to probe the stack when allocating more
1082 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1083 // to ensure that the guard pages used by the OS virtual memory manager are
1084 // allocated in correct sequence.
1086 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1088 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1089 .addExternalSymbol("_alloca")
1090 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1093 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1094 .addReg(X86::EAX, RegState::Kill);
1096 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1097 // allocated bytes for EAX.
1098 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1099 .addImm(NumBytes - 4);
1100 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1101 .addExternalSymbol("_alloca")
1102 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1105 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1107 StackPtr, false, NumBytes - 4);
1108 MBB.insert(MBBI, MI);
1110 } else if (NumBytes) {
1111 // If there is an SUB32ri of ESP immediately before this instruction, merge
1112 // the two. This can be the case when tail call elimination is enabled and
1113 // the callee has more arguments then the caller.
1114 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1116 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1117 // instruction, merge the two instructions.
1118 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1121 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1124 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1125 // Mark end of stack pointer adjustment.
1126 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1127 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
1129 if (!HasFP && NumBytes) {
1130 // Define the current CFA rule to use the provided offset.
1132 MachineLocation SPDst(MachineLocation::VirtualFP);
1133 MachineLocation SPSrc(MachineLocation::VirtualFP,
1134 -StackSize + stackGrowth);
1135 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1137 // FIXME: Verify & implement for FP
1138 MachineLocation SPDst(StackPtr);
1139 MachineLocation SPSrc(StackPtr, stackGrowth);
1140 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1144 // Emit DWARF info specifying the offsets of the callee-saved registers.
1146 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1150 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1151 MachineBasicBlock &MBB) const {
1152 const MachineFrameInfo *MFI = MF.getFrameInfo();
1153 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1154 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1155 unsigned RetOpcode = MBBI->getOpcode();
1156 DebugLoc DL = MBBI->getDebugLoc();
1158 switch (RetOpcode) {
1160 llvm_unreachable("Can only insert epilog into returning blocks");
1163 case X86::TCRETURNdi:
1164 case X86::TCRETURNri:
1165 case X86::TCRETURNmi:
1166 case X86::TCRETURNdi64:
1167 case X86::TCRETURNri64:
1168 case X86::TCRETURNmi64:
1169 case X86::EH_RETURN:
1170 case X86::EH_RETURN64:
1171 break; // These are ok
1174 // Get the number of bytes to allocate from the FrameInfo.
1175 uint64_t StackSize = MFI->getStackSize();
1176 uint64_t MaxAlign = MFI->getMaxAlignment();
1177 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1178 uint64_t NumBytes = 0;
1181 // Calculate required stack adjustment.
1182 uint64_t FrameSize = StackSize - SlotSize;
1183 if (needsStackRealignment(MF))
1184 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1186 NumBytes = FrameSize - CSSize;
1189 BuildMI(MBB, MBBI, DL,
1190 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1192 NumBytes = StackSize - CSSize;
1195 // Skip the callee-saved pop instructions.
1196 MachineBasicBlock::iterator LastCSPop = MBBI;
1197 while (MBBI != MBB.begin()) {
1198 MachineBasicBlock::iterator PI = prior(MBBI);
1199 unsigned Opc = PI->getOpcode();
1201 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1202 !PI->getDesc().isTerminator())
1208 DL = MBBI->getDebugLoc();
1210 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1211 // instruction, merge the two instructions.
1212 if (NumBytes || MFI->hasVarSizedObjects())
1213 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1215 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1216 // slot before popping them off! Same applies for the case, when stack was
1218 if (needsStackRealignment(MF)) {
1219 // We cannot use LEA here, because stack pointer was realigned. We need to
1220 // deallocate local frame back.
1222 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1223 MBBI = prior(LastCSPop);
1226 BuildMI(MBB, MBBI, DL,
1227 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1228 StackPtr).addReg(FramePtr);
1229 } else if (MFI->hasVarSizedObjects()) {
1231 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1233 addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1234 FramePtr, false, -CSSize);
1235 MBB.insert(MBBI, MI);
1237 BuildMI(MBB, MBBI, DL,
1238 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1241 } else if (NumBytes) {
1242 // Adjust stack pointer back: ESP += numbytes.
1243 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1246 // We're returning from function via eh_return.
1247 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1248 MBBI = prior(MBB.end());
1249 MachineOperand &DestAddr = MBBI->getOperand(0);
1250 assert(DestAddr.isReg() && "Offset should be in register!");
1251 BuildMI(MBB, MBBI, DL,
1252 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1253 StackPtr).addReg(DestAddr.getReg());
1254 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1255 RetOpcode == X86::TCRETURNmi ||
1256 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1257 RetOpcode == X86::TCRETURNmi64) {
1258 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1259 // Tail call return: adjust the stack pointer and jump to callee.
1260 MBBI = prior(MBB.end());
1261 MachineOperand &JumpTarget = MBBI->getOperand(0);
1262 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1263 assert(StackAdjust.isImm() && "Expecting immediate value.");
1265 // Adjust stack pointer.
1266 int StackAdj = StackAdjust.getImm();
1267 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1269 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1271 // Incoporate the retaddr area.
1272 Offset = StackAdj-MaxTCDelta;
1273 assert(Offset >= 0 && "Offset should never be negative");
1276 // Check for possible merge with preceeding ADD instruction.
1277 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1278 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1281 // Jump to label or value in register.
1282 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1283 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1284 ? X86::TAILJMPd : X86::TAILJMPd64)).
1285 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1286 JumpTarget.getTargetFlags());
1287 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1288 MachineInstrBuilder MIB =
1289 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1290 ? X86::TAILJMPm : X86::TAILJMPm64));
1291 for (unsigned i = 0; i != 5; ++i)
1292 MIB.addOperand(MBBI->getOperand(i));
1293 } else if (RetOpcode == X86::TCRETURNri64) {
1294 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1295 addReg(JumpTarget.getReg(), RegState::Kill);
1297 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1298 addReg(JumpTarget.getReg(), RegState::Kill);
1301 MachineInstr *NewMI = prior(MBBI);
1302 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1303 NewMI->addOperand(MBBI->getOperand(i));
1305 // Delete the pseudo instruction TCRETURN.
1307 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1308 (X86FI->getTCReturnAddrDelta() < 0)) {
1309 // Add the return addr area delta back since we are not tail calling.
1310 int delta = -1*X86FI->getTCReturnAddrDelta();
1311 MBBI = prior(MBB.end());
1313 // Check for possible merge with preceeding ADD instruction.
1314 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1315 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1319 unsigned X86RegisterInfo::getRARegister() const {
1320 return Is64Bit ? X86::RIP // Should have dwarf #16.
1321 : X86::EIP; // Should have dwarf #8.
1324 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1325 return hasFP(MF) ? FramePtr : StackPtr;
1329 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1330 // Calculate amount of bytes used for return address storing
1331 int stackGrowth = (Is64Bit ? -8 : -4);
1333 // Initial state of the frame pointer is esp+stackGrowth.
1334 MachineLocation Dst(MachineLocation::VirtualFP);
1335 MachineLocation Src(StackPtr, stackGrowth);
1336 Moves.push_back(MachineMove(0, Dst, Src));
1338 // Add return address to move list
1339 MachineLocation CSDst(StackPtr, stackGrowth);
1340 MachineLocation CSSrc(getRARegister());
1341 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1344 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1345 llvm_unreachable("What is the exception register");
1349 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1350 llvm_unreachable("What is the exception handler register");
1355 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1356 switch (VT.getSimpleVT().SimpleTy) {
1357 default: return Reg;
1362 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1364 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1366 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1368 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1374 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1376 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1378 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1380 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1382 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1384 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1386 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1388 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1390 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1392 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1394 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1396 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1398 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1400 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1402 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1404 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1410 default: return Reg;
1411 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1413 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1415 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1417 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1419 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1421 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1423 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1425 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1427 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1429 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1431 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1433 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1435 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1437 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1439 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1441 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1446 default: return Reg;
1447 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1449 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1451 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1453 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1455 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1457 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1459 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1461 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1463 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1465 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1467 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1469 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1471 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1473 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1475 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1477 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1482 default: return Reg;
1483 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1485 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1487 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1489 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1491 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1493 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1495 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1497 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1499 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1501 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1503 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1505 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1507 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1509 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1511 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1513 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1522 #include "X86GenRegisterInfo.inc"
1525 struct MSAH : public MachineFunctionPass {
1527 MSAH() : MachineFunctionPass(&ID) {}
1529 virtual bool runOnMachineFunction(MachineFunction &MF) {
1530 const X86TargetMachine *TM =
1531 static_cast<const X86TargetMachine *>(&MF.getTarget());
1532 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1533 MachineRegisterInfo &RI = MF.getRegInfo();
1534 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1535 unsigned StackAlignment = X86RI->getStackAlignment();
1537 // Be over-conservative: scan over all vreg defs and find whether vector
1538 // registers are used. If yes, there is a possibility that vector register
1539 // will be spilled and thus require dynamic stack realignment.
1540 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1541 RegNum < RI.getLastVirtReg(); ++RegNum)
1542 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1543 FuncInfo->setReserveFP(true);
1551 virtual const char *getPassName() const {
1552 return "X86 Maximal Stack Alignment Check";
1555 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1556 AU.setPreservesCFG();
1557 MachineFunctionPass::getAnalysisUsage(AU);
1565 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }