1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on X86.
13 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
17 #include "X86Subtarget.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Type.h"
23 #include "llvm/Function.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/ADT/STLExtras.h"
40 NoFusing("disable-spill-fusing",
41 cl::desc("Disable fusing of spill code into instructions"));
43 PrintFailedFusing("print-failed-fuse-candidates",
44 cl::desc("Print instructions that the allocator wants to"
45 " fuse, but the X86 backend currently can't"),
49 X86RegisterInfo::X86RegisterInfo(const TargetInstrInfo &tii)
50 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP), TII(tii) {}
52 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MI,
54 unsigned SrcReg, int FrameIdx,
55 const TargetRegisterClass *RC) const {
57 if (RC == &X86::GR32RegClass) {
59 } else if (RC == &X86::GR16RegClass) {
61 } else if (RC == &X86::GR8RegClass) {
63 } else if (RC == &X86::GR32_RegClass) {
65 } else if (RC == &X86::GR16_RegClass) {
67 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
69 } else if (RC == &X86::FR32RegClass) {
71 } else if (RC == &X86::FR64RegClass) {
73 } else if (RC == &X86::VR128RegClass) {
76 assert(0 && "Unknown regclass");
79 addFrameReference(BuildMI(MBB, MI, Opc, 5), FrameIdx).addReg(SrcReg);
82 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MI,
84 unsigned DestReg, int FrameIdx,
85 const TargetRegisterClass *RC) const{
87 if (RC == &X86::GR32RegClass) {
89 } else if (RC == &X86::GR16RegClass) {
91 } else if (RC == &X86::GR8RegClass) {
93 } else if (RC == &X86::GR32_RegClass) {
95 } else if (RC == &X86::GR16_RegClass) {
97 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
99 } else if (RC == &X86::FR32RegClass) {
101 } else if (RC == &X86::FR64RegClass) {
103 } else if (RC == &X86::VR128RegClass) {
106 assert(0 && "Unknown regclass");
109 addFrameReference(BuildMI(MBB, MI, Opc, 4, DestReg), FrameIdx);
112 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
113 MachineBasicBlock::iterator MI,
114 unsigned DestReg, unsigned SrcReg,
115 const TargetRegisterClass *RC) const {
117 if (RC == &X86::GR32RegClass) {
119 } else if (RC == &X86::GR16RegClass) {
121 } else if (RC == &X86::GR8RegClass) {
123 } else if (RC == &X86::GR32_RegClass) {
125 } else if (RC == &X86::GR16_RegClass) {
127 } else if (RC == &X86::RFPRegClass || RC == &X86::RSTRegClass) {
129 } else if (RC == &X86::FR32RegClass) {
130 Opc = X86::FsMOVAPSrr;
131 } else if (RC == &X86::FR64RegClass) {
132 Opc = X86::FsMOVAPDrr;
133 } else if (RC == &X86::VR128RegClass) {
136 assert(0 && "Unknown regclass");
139 BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg);
142 static MachineInstr *FuseTwoAddrInst(unsigned Opcode, unsigned FrameIndex,
144 unsigned NumOps = MI->getNumOperands()-2;
145 // Create the base instruction with the memory operand as the first part.
146 MachineInstrBuilder MIB = addFrameReference(BuildMI(Opcode, 4+NumOps),
149 // Loop over the rest of the ri operands, converting them over.
150 for (unsigned i = 0; i != NumOps; ++i) {
151 if (MI->getOperand(i+2).isReg())
152 MIB = MIB.addReg(MI->getOperand(i+2).getReg());
154 assert(MI->getOperand(i+2).isImm() && "Unknown operand type!");
155 MIB = MIB.addImm(MI->getOperand(i+2).getImm());
161 static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo,
162 unsigned FrameIndex, MachineInstr *MI) {
163 MachineInstrBuilder MIB = BuildMI(Opcode, MI->getNumOperands()+3);
165 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
166 MachineOperand &MO = MI->getOperand(i);
168 assert(MO.isReg() && "Expected to fold into reg operand!");
169 MIB = addFrameReference(MIB, FrameIndex);
170 } else if (MO.isReg())
171 MIB = MIB.addReg(MO.getReg(), MO.getUseType());
173 MIB = MIB.addImm(MO.getImm());
174 else if (MO.isGlobalAddress())
175 MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
176 else if (MO.isJumpTableIndex())
177 MIB = MIB.addJumpTableIndex(MO.getJumpTableIndex());
179 assert(0 && "Unknown operand for FuseInst!");
184 static MachineInstr *MakeM0Inst(unsigned Opcode, unsigned FrameIndex,
186 return addFrameReference(BuildMI(Opcode, 5), FrameIndex).addImm(0);
190 //===----------------------------------------------------------------------===//
191 // Efficient Lookup Table Support
192 //===----------------------------------------------------------------------===//
195 /// TableEntry - Maps the 'from' opcode to a fused form of the 'to' opcode.
198 unsigned from; // Original opcode.
199 unsigned to; // New opcode.
201 // less operators used by STL search.
202 bool operator<(const TableEntry &TE) const { return from < TE.from; }
203 friend bool operator<(const TableEntry &TE, unsigned V) {
206 friend bool operator<(unsigned V, const TableEntry &TE) {
212 /// TableIsSorted - Return true if the table is in 'from' opcode order.
214 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
215 for (unsigned i = 1; i != NumEntries; ++i)
216 if (!(Table[i-1] < Table[i])) {
217 std::cerr << "Entries out of order " << Table[i-1].from
218 << " " << Table[i].from << "\n";
224 /// TableLookup - Return the table entry matching the specified opcode.
225 /// Otherwise return NULL.
226 static const TableEntry *TableLookup(const TableEntry *Table, unsigned N,
228 const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
229 if (I != Table+N && I->from == Opcode)
234 #define ARRAY_SIZE(TABLE) \
235 (sizeof(TABLE)/sizeof(TABLE[0]))
238 #define ASSERT_SORTED(TABLE)
240 #define ASSERT_SORTED(TABLE) \
241 { static bool TABLE##Checked = false; \
242 if (!TABLE##Checked) { \
243 assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
244 "All lookup tables must be sorted for efficient access!"); \
245 TABLE##Checked = true; \
251 MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
253 int FrameIndex) const {
255 if (NoFusing) return NULL;
257 // Table (and size) to search
258 const TableEntry *OpcodeTablePtr = NULL;
259 unsigned OpcodeTableSize = 0;
260 bool isTwoAddrFold = false;
262 // Folding a memory location into the two-address part of a two-address
263 // instruction is different than folding it other places. It requires
264 // replacing the *two* registers with the memory location.
265 if (MI->getNumOperands() >= 2 && MI->getOperand(0).isReg() &&
266 MI->getOperand(1).isReg() && i < 2 &&
267 MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
268 TII.isTwoAddrInstr(MI->getOpcode())) {
269 static const TableEntry OpcodeTable[] = {
270 { X86::ADC32ri, X86::ADC32mi },
271 { X86::ADC32ri8, X86::ADC32mi8 },
272 { X86::ADC32rr, X86::ADC32mr },
273 { X86::ADD16ri, X86::ADD16mi },
274 { X86::ADD16ri8, X86::ADD16mi8 },
275 { X86::ADD16rr, X86::ADD16mr },
276 { X86::ADD32ri, X86::ADD32mi },
277 { X86::ADD32ri8, X86::ADD32mi8 },
278 { X86::ADD32rr, X86::ADD32mr },
279 { X86::ADD8ri, X86::ADD8mi },
280 { X86::ADD8rr, X86::ADD8mr },
281 { X86::AND16ri, X86::AND16mi },
282 { X86::AND16ri8, X86::AND16mi8 },
283 { X86::AND16rr, X86::AND16mr },
284 { X86::AND32ri, X86::AND32mi },
285 { X86::AND32ri8, X86::AND32mi8 },
286 { X86::AND32rr, X86::AND32mr },
287 { X86::AND8ri, X86::AND8mi },
288 { X86::AND8rr, X86::AND8mr },
289 { X86::DEC16r, X86::DEC16m },
290 { X86::DEC32r, X86::DEC32m },
291 { X86::DEC8r, X86::DEC8m },
292 { X86::INC16r, X86::INC16m },
293 { X86::INC32r, X86::INC32m },
294 { X86::INC8r, X86::INC8m },
295 { X86::NEG16r, X86::NEG16m },
296 { X86::NEG32r, X86::NEG32m },
297 { X86::NEG8r, X86::NEG8m },
298 { X86::NOT16r, X86::NOT16m },
299 { X86::NOT32r, X86::NOT32m },
300 { X86::NOT8r, X86::NOT8m },
301 { X86::OR16ri, X86::OR16mi },
302 { X86::OR16ri8, X86::OR16mi8 },
303 { X86::OR16rr, X86::OR16mr },
304 { X86::OR32ri, X86::OR32mi },
305 { X86::OR32ri8, X86::OR32mi8 },
306 { X86::OR32rr, X86::OR32mr },
307 { X86::OR8ri, X86::OR8mi },
308 { X86::OR8rr, X86::OR8mr },
309 { X86::ROL16r1, X86::ROL16m1 },
310 { X86::ROL16rCL, X86::ROL16mCL },
311 { X86::ROL16ri, X86::ROL16mi },
312 { X86::ROL32r1, X86::ROL32m1 },
313 { X86::ROL32rCL, X86::ROL32mCL },
314 { X86::ROL32ri, X86::ROL32mi },
315 { X86::ROL8r1, X86::ROL8m1 },
316 { X86::ROL8rCL, X86::ROL8mCL },
317 { X86::ROL8ri, X86::ROL8mi },
318 { X86::ROR16r1, X86::ROR16m1 },
319 { X86::ROR16rCL, X86::ROR16mCL },
320 { X86::ROR16ri, X86::ROR16mi },
321 { X86::ROR32r1, X86::ROR32m1 },
322 { X86::ROR32rCL, X86::ROR32mCL },
323 { X86::ROR32ri, X86::ROR32mi },
324 { X86::ROR8r1, X86::ROR8m1 },
325 { X86::ROR8rCL, X86::ROR8mCL },
326 { X86::ROR8ri, X86::ROR8mi },
327 { X86::SAR16r1, X86::SAR16m1 },
328 { X86::SAR16rCL, X86::SAR16mCL },
329 { X86::SAR16ri, X86::SAR16mi },
330 { X86::SAR32r1, X86::SAR32m1 },
331 { X86::SAR32rCL, X86::SAR32mCL },
332 { X86::SAR32ri, X86::SAR32mi },
333 { X86::SAR8r1, X86::SAR8m1 },
334 { X86::SAR8rCL, X86::SAR8mCL },
335 { X86::SAR8ri, X86::SAR8mi },
336 { X86::SBB32ri, X86::SBB32mi },
337 { X86::SBB32ri8, X86::SBB32mi8 },
338 { X86::SBB32rr, X86::SBB32mr },
339 { X86::SHL16r1, X86::SHL16m1 },
340 { X86::SHL16rCL, X86::SHL16mCL },
341 { X86::SHL16ri, X86::SHL16mi },
342 { X86::SHL32r1, X86::SHL32m1 },
343 { X86::SHL32rCL, X86::SHL32mCL },
344 { X86::SHL32ri, X86::SHL32mi },
345 { X86::SHL8r1, X86::SHL8m1 },
346 { X86::SHL8rCL, X86::SHL8mCL },
347 { X86::SHL8ri, X86::SHL8mi },
348 { X86::SHLD16rrCL, X86::SHLD16mrCL },
349 { X86::SHLD16rri8, X86::SHLD16mri8 },
350 { X86::SHLD32rrCL, X86::SHLD32mrCL },
351 { X86::SHLD32rri8, X86::SHLD32mri8 },
352 { X86::SHR16r1, X86::SHR16m1 },
353 { X86::SHR16rCL, X86::SHR16mCL },
354 { X86::SHR16ri, X86::SHR16mi },
355 { X86::SHR32r1, X86::SHR32m1 },
356 { X86::SHR32rCL, X86::SHR32mCL },
357 { X86::SHR32ri, X86::SHR32mi },
358 { X86::SHR8r1, X86::SHR8m1 },
359 { X86::SHR8rCL, X86::SHR8mCL },
360 { X86::SHR8ri, X86::SHR8mi },
361 { X86::SHRD16rrCL, X86::SHRD16mrCL },
362 { X86::SHRD16rri8, X86::SHRD16mri8 },
363 { X86::SHRD32rrCL, X86::SHRD32mrCL },
364 { X86::SHRD32rri8, X86::SHRD32mri8 },
365 { X86::SUB16ri, X86::SUB16mi },
366 { X86::SUB16ri8, X86::SUB16mi8 },
367 { X86::SUB16rr, X86::SUB16mr },
368 { X86::SUB32ri, X86::SUB32mi },
369 { X86::SUB32ri8, X86::SUB32mi8 },
370 { X86::SUB32rr, X86::SUB32mr },
371 { X86::SUB8ri, X86::SUB8mi },
372 { X86::SUB8rr, X86::SUB8mr },
373 { X86::XOR16ri, X86::XOR16mi },
374 { X86::XOR16ri8, X86::XOR16mi8 },
375 { X86::XOR16rr, X86::XOR16mr },
376 { X86::XOR32ri, X86::XOR32mi },
377 { X86::XOR32ri8, X86::XOR32mi8 },
378 { X86::XOR32rr, X86::XOR32mr },
379 { X86::XOR8ri, X86::XOR8mi },
380 { X86::XOR8rr, X86::XOR8mr }
382 ASSERT_SORTED(OpcodeTable);
383 OpcodeTablePtr = OpcodeTable;
384 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
385 isTwoAddrFold = true;
386 } else if (i == 0) { // If operand 0
387 if (MI->getOpcode() == X86::MOV16r0)
388 return MakeM0Inst(X86::MOV16mi, FrameIndex, MI);
389 else if (MI->getOpcode() == X86::MOV32r0)
390 return MakeM0Inst(X86::MOV32mi, FrameIndex, MI);
391 else if (MI->getOpcode() == X86::MOV8r0)
392 return MakeM0Inst(X86::MOV8mi, FrameIndex, MI);
394 static const TableEntry OpcodeTable[] = {
395 { X86::CMP16ri, X86::CMP16mi },
396 { X86::CMP16ri8, X86::CMP16mi8 },
397 { X86::CMP32ri, X86::CMP32mi },
398 { X86::CMP32ri8, X86::CMP32mi8 },
399 { X86::CMP8ri, X86::CMP8mi },
400 { X86::DIV16r, X86::DIV16m },
401 { X86::DIV32r, X86::DIV32m },
402 { X86::DIV8r, X86::DIV8m },
403 { X86::FsMOVAPDrr, X86::MOVSDmr },
404 { X86::FsMOVAPSrr, X86::MOVSSmr },
405 { X86::IDIV16r, X86::IDIV16m },
406 { X86::IDIV32r, X86::IDIV32m },
407 { X86::IDIV8r, X86::IDIV8m },
408 { X86::IMUL16r, X86::IMUL16m },
409 { X86::IMUL32r, X86::IMUL32m },
410 { X86::IMUL8r, X86::IMUL8m },
411 { X86::MOV16ri, X86::MOV16mi },
412 { X86::MOV16rr, X86::MOV16mr },
413 { X86::MOV32ri, X86::MOV32mi },
414 { X86::MOV32rr, X86::MOV32mr },
415 { X86::MOV8ri, X86::MOV8mi },
416 { X86::MOV8rr, X86::MOV8mr },
417 { X86::MOVAPDrr, X86::MOVAPDmr },
418 { X86::MOVAPSrr, X86::MOVAPSmr },
419 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr },
420 { X86::MOVPS2SSrr, X86::MOVPS2SSmr },
421 { X86::MOVSDrr, X86::MOVSDmr },
422 { X86::MOVSSrr, X86::MOVSSmr },
423 { X86::MOVUPDrr, X86::MOVUPDmr },
424 { X86::MOVUPSrr, X86::MOVUPSmr },
425 { X86::MUL16r, X86::MUL16m },
426 { X86::MUL32r, X86::MUL32m },
427 { X86::MUL8r, X86::MUL8m },
428 { X86::SETAEr, X86::SETAEm },
429 { X86::SETAr, X86::SETAm },
430 { X86::SETBEr, X86::SETBEm },
431 { X86::SETBr, X86::SETBm },
432 { X86::SETEr, X86::SETEm },
433 { X86::SETGEr, X86::SETGEm },
434 { X86::SETGr, X86::SETGm },
435 { X86::SETLEr, X86::SETLEm },
436 { X86::SETLr, X86::SETLm },
437 { X86::SETNEr, X86::SETNEm },
438 { X86::SETNPr, X86::SETNPm },
439 { X86::SETNSr, X86::SETNSm },
440 { X86::SETPr, X86::SETPm },
441 { X86::SETSr, X86::SETSm },
442 { X86::TEST16ri, X86::TEST16mi },
443 { X86::TEST32ri, X86::TEST32mi },
444 { X86::TEST8ri, X86::TEST8mi },
445 { X86::XCHG16rr, X86::XCHG16mr },
446 { X86::XCHG32rr, X86::XCHG32mr },
447 { X86::XCHG8rr, X86::XCHG8mr }
449 ASSERT_SORTED(OpcodeTable);
450 OpcodeTablePtr = OpcodeTable;
451 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
453 static const TableEntry OpcodeTable[] = {
454 { X86::CMP16rr, X86::CMP16rm },
455 { X86::CMP32rr, X86::CMP32rm },
456 { X86::CMP8rr, X86::CMP8rm },
457 { X86::CMPPDrri, X86::CMPPDrmi },
458 { X86::CMPPSrri, X86::CMPPSrmi },
459 { X86::CMPSDrr, X86::CMPSDrm },
460 { X86::CMPSSrr, X86::CMPSSrm },
461 { X86::CVTSD2SSrr, X86::CVTSD2SSrm },
462 { X86::CVTSI2SDrr, X86::CVTSI2SDrm },
463 { X86::CVTSI2SSrr, X86::CVTSI2SSrm },
464 { X86::CVTSS2SDrr, X86::CVTSS2SDrm },
465 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm },
466 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm },
467 { X86::FsMOVAPDrr, X86::MOVSDrm },
468 { X86::FsMOVAPSrr, X86::MOVSSrm },
469 { X86::IMUL16rri, X86::IMUL16rmi },
470 { X86::IMUL16rri8, X86::IMUL16rmi8 },
471 { X86::IMUL32rri, X86::IMUL32rmi },
472 { X86::IMUL32rri8, X86::IMUL32rmi8 },
473 { X86::Int_CMPSDrr, X86::Int_CMPSDrm },
474 { X86::Int_CMPSSrr, X86::Int_CMPSSrm },
475 { X86::Int_COMISDrr, X86::Int_COMISDrm },
476 { X86::Int_COMISSrr, X86::Int_COMISSrm },
477 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm },
478 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm },
479 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm },
480 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm },
481 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm },
482 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm },
483 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm },
484 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm },
485 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm },
486 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm },
487 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm },
488 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm },
489 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm },
490 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm },
491 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm },
492 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm },
493 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm },
494 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm },
495 { X86::MOV16rr, X86::MOV16rm },
496 { X86::MOV32rr, X86::MOV32rm },
497 { X86::MOV8rr, X86::MOV8rm },
498 { X86::MOVAPDrr, X86::MOVAPDrm },
499 { X86::MOVAPSrr, X86::MOVAPSrm },
500 { X86::MOVDDUPrr, X86::MOVDDUPrm },
501 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm },
502 { X86::MOVQI2PQIrr, X86::MOVQI2PQIrm },
503 { X86::MOVSD2PDrr, X86::MOVSD2PDrm },
504 { X86::MOVSDrr, X86::MOVSDrm },
505 { X86::MOVSHDUPrr, X86::MOVSHDUPrm },
506 { X86::MOVSLDUPrr, X86::MOVSLDUPrm },
507 { X86::MOVSS2PSrr, X86::MOVSS2PSrm },
508 { X86::MOVSSrr, X86::MOVSSrm },
509 { X86::MOVSX16rr8, X86::MOVSX16rm8 },
510 { X86::MOVSX32rr16, X86::MOVSX32rm16 },
511 { X86::MOVSX32rr8, X86::MOVSX32rm8 },
512 { X86::MOVUPDrr, X86::MOVUPDrm },
513 { X86::MOVUPSrr, X86::MOVUPSrm },
514 { X86::MOVZX16rr8, X86::MOVZX16rm8 },
515 { X86::MOVZX32rr16, X86::MOVZX32rm16 },
516 { X86::MOVZX32rr8, X86::MOVZX32rm8 },
517 { X86::PSHUFDri, X86::PSHUFDmi },
518 { X86::PSHUFHWri, X86::PSHUFHWmi },
519 { X86::PSHUFLWri, X86::PSHUFLWmi },
520 { X86::TEST16rr, X86::TEST16rm },
521 { X86::TEST32rr, X86::TEST32rm },
522 { X86::TEST8rr, X86::TEST8rm },
523 { X86::UCOMISDrr, X86::UCOMISDrm },
524 { X86::UCOMISSrr, X86::UCOMISSrm },
525 { X86::XCHG16rr, X86::XCHG16rm },
526 { X86::XCHG32rr, X86::XCHG32rm },
527 { X86::XCHG8rr, X86::XCHG8rm }
529 ASSERT_SORTED(OpcodeTable);
530 OpcodeTablePtr = OpcodeTable;
531 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
533 static const TableEntry OpcodeTable[] = {
534 { X86::ADC32rr, X86::ADC32rm },
535 { X86::ADD16rr, X86::ADD16rm },
536 { X86::ADD32rr, X86::ADD32rm },
537 { X86::ADD8rr, X86::ADD8rm },
538 { X86::ADDPDrr, X86::ADDPDrm },
539 { X86::ADDPSrr, X86::ADDPSrm },
540 { X86::ADDSDrr, X86::ADDSDrm },
541 { X86::ADDSSrr, X86::ADDSSrm },
542 { X86::ADDSUBPDrr, X86::ADDSUBPDrm },
543 { X86::ADDSUBPSrr, X86::ADDSUBPSrm },
544 { X86::AND16rr, X86::AND16rm },
545 { X86::AND32rr, X86::AND32rm },
546 { X86::AND8rr, X86::AND8rm },
547 { X86::ANDNPDrr, X86::ANDNPDrm },
548 { X86::ANDNPSrr, X86::ANDNPSrm },
549 { X86::ANDPDrr, X86::ANDPDrm },
550 { X86::ANDPSrr, X86::ANDPSrm },
551 { X86::CMOVA16rr, X86::CMOVA16rm },
552 { X86::CMOVA32rr, X86::CMOVA32rm },
553 { X86::CMOVAE16rr, X86::CMOVAE16rm },
554 { X86::CMOVAE32rr, X86::CMOVAE32rm },
555 { X86::CMOVB16rr, X86::CMOVB16rm },
556 { X86::CMOVB32rr, X86::CMOVB32rm },
557 { X86::CMOVBE16rr, X86::CMOVBE16rm },
558 { X86::CMOVBE32rr, X86::CMOVBE32rm },
559 { X86::CMOVE16rr, X86::CMOVE16rm },
560 { X86::CMOVE32rr, X86::CMOVE32rm },
561 { X86::CMOVG16rr, X86::CMOVG16rm },
562 { X86::CMOVG32rr, X86::CMOVG32rm },
563 { X86::CMOVGE16rr, X86::CMOVGE16rm },
564 { X86::CMOVGE32rr, X86::CMOVGE32rm },
565 { X86::CMOVL16rr, X86::CMOVL16rm },
566 { X86::CMOVL32rr, X86::CMOVL32rm },
567 { X86::CMOVLE16rr, X86::CMOVLE16rm },
568 { X86::CMOVLE32rr, X86::CMOVLE32rm },
569 { X86::CMOVNE16rr, X86::CMOVNE16rm },
570 { X86::CMOVNE32rr, X86::CMOVNE32rm },
571 { X86::CMOVNP16rr, X86::CMOVNP16rm },
572 { X86::CMOVNP32rr, X86::CMOVNP32rm },
573 { X86::CMOVNS16rr, X86::CMOVNS16rm },
574 { X86::CMOVNS32rr, X86::CMOVNS32rm },
575 { X86::CMOVP16rr, X86::CMOVP16rm },
576 { X86::CMOVP32rr, X86::CMOVP32rm },
577 { X86::CMOVS16rr, X86::CMOVS16rm },
578 { X86::CMOVS32rr, X86::CMOVS32rm },
579 { X86::DIVPDrr, X86::DIVPDrm },
580 { X86::DIVPSrr, X86::DIVPSrm },
581 { X86::DIVSDrr, X86::DIVSDrm },
582 { X86::DIVSSrr, X86::DIVSSrm },
583 { X86::HADDPDrr, X86::HADDPDrm },
584 { X86::HADDPSrr, X86::HADDPSrm },
585 { X86::HSUBPDrr, X86::HSUBPDrm },
586 { X86::HSUBPSrr, X86::HSUBPSrm },
587 { X86::IMUL16rr, X86::IMUL16rm },
588 { X86::IMUL32rr, X86::IMUL32rm },
589 { X86::MAXPDrr, X86::MAXPDrm },
590 { X86::MAXPSrr, X86::MAXPSrm },
591 { X86::MINPDrr, X86::MINPDrm },
592 { X86::MINPSrr, X86::MINPSrm },
593 { X86::MULPDrr, X86::MULPDrm },
594 { X86::MULPSrr, X86::MULPSrm },
595 { X86::MULSDrr, X86::MULSDrm },
596 { X86::MULSSrr, X86::MULSSrm },
597 { X86::OR16rr, X86::OR16rm },
598 { X86::OR32rr, X86::OR32rm },
599 { X86::OR8rr, X86::OR8rm },
600 { X86::ORPDrr, X86::ORPDrm },
601 { X86::ORPSrr, X86::ORPSrm },
602 { X86::PACKSSDWrr, X86::PACKSSDWrm },
603 { X86::PACKSSWBrr, X86::PACKSSWBrm },
604 { X86::PACKUSWBrr, X86::PACKUSWBrm },
605 { X86::PADDBrr, X86::PADDBrm },
606 { X86::PADDDrr, X86::PADDDrm },
607 { X86::PADDSBrr, X86::PADDSBrm },
608 { X86::PADDSWrr, X86::PADDSWrm },
609 { X86::PADDWrr, X86::PADDWrm },
610 { X86::PANDNrr, X86::PANDNrm },
611 { X86::PANDrr, X86::PANDrm },
612 { X86::PAVGBrr, X86::PAVGBrm },
613 { X86::PAVGWrr, X86::PAVGWrm },
614 { X86::PCMPEQBrr, X86::PCMPEQBrm },
615 { X86::PCMPEQDrr, X86::PCMPEQDrm },
616 { X86::PCMPEQWrr, X86::PCMPEQWrm },
617 { X86::PCMPGTBrr, X86::PCMPGTBrm },
618 { X86::PCMPGTDrr, X86::PCMPGTDrm },
619 { X86::PCMPGTWrr, X86::PCMPGTWrm },
620 { X86::PINSRWrri, X86::PINSRWrmi },
621 { X86::PMADDWDrr, X86::PMADDWDrm },
622 { X86::PMAXSWrr, X86::PMAXSWrm },
623 { X86::PMAXUBrr, X86::PMAXUBrm },
624 { X86::PMINSWrr, X86::PMINSWrm },
625 { X86::PMINUBrr, X86::PMINUBrm },
626 { X86::PMULHUWrr, X86::PMULHUWrm },
627 { X86::PMULHWrr, X86::PMULHWrm },
628 { X86::PMULLWrr, X86::PMULLWrm },
629 { X86::PMULUDQrr, X86::PMULUDQrm },
630 { X86::PORrr, X86::PORrm },
631 { X86::PSADBWrr, X86::PSADBWrm },
632 { X86::PSLLDrr, X86::PSLLDrm },
633 { X86::PSLLQrr, X86::PSLLQrm },
634 { X86::PSLLWrr, X86::PSLLWrm },
635 { X86::PSRADrr, X86::PSRADrm },
636 { X86::PSRAWrr, X86::PSRAWrm },
637 { X86::PSRLDrr, X86::PSRLDrm },
638 { X86::PSRLQrr, X86::PSRLQrm },
639 { X86::PSRLWrr, X86::PSRLWrm },
640 { X86::PSUBBrr, X86::PSUBBrm },
641 { X86::PSUBDrr, X86::PSUBDrm },
642 { X86::PSUBSBrr, X86::PSUBSBrm },
643 { X86::PSUBSWrr, X86::PSUBSWrm },
644 { X86::PSUBWrr, X86::PSUBWrm },
645 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm },
646 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm },
647 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm },
648 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm },
649 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm },
650 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm },
651 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm },
652 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm },
653 { X86::PXORrr, X86::PXORrm },
654 { X86::RCPPSr, X86::RCPPSm },
655 { X86::RSQRTPSr, X86::RSQRTPSm },
656 { X86::SBB32rr, X86::SBB32rm },
657 { X86::SHUFPDrri, X86::SHUFPDrmi },
658 { X86::SHUFPSrri, X86::SHUFPSrmi },
659 { X86::SQRTPDr, X86::SQRTPDm },
660 { X86::SQRTPSr, X86::SQRTPSm },
661 { X86::SQRTSDr, X86::SQRTSDm },
662 { X86::SQRTSSr, X86::SQRTSSm },
663 { X86::SUB16rr, X86::SUB16rm },
664 { X86::SUB32rr, X86::SUB32rm },
665 { X86::SUB8rr, X86::SUB8rm },
666 { X86::SUBPDrr, X86::SUBPDrm },
667 { X86::SUBPSrr, X86::SUBPSrm },
668 { X86::SUBSDrr, X86::SUBSDrm },
669 { X86::SUBSSrr, X86::SUBSSrm },
670 { X86::UNPCKHPDrr, X86::UNPCKHPDrm },
671 { X86::UNPCKHPSrr, X86::UNPCKHPSrm },
672 { X86::UNPCKLPDrr, X86::UNPCKLPDrm },
673 { X86::UNPCKLPSrr, X86::UNPCKLPSrm },
674 { X86::XOR16rr, X86::XOR16rm },
675 { X86::XOR32rr, X86::XOR32rm },
676 { X86::XOR8rr, X86::XOR8rm },
677 { X86::XORPDrr, X86::XORPDrm },
678 { X86::XORPSrr, X86::XORPSrm }
680 ASSERT_SORTED(OpcodeTable);
681 OpcodeTablePtr = OpcodeTable;
682 OpcodeTableSize = ARRAY_SIZE(OpcodeTable);
685 // If table selected...
686 if (OpcodeTablePtr) {
687 // Find the Opcode to fuse
688 unsigned fromOpcode = MI->getOpcode();
689 // Lookup fromOpcode in table
690 if (const TableEntry *Entry = TableLookup(OpcodeTablePtr, OpcodeTableSize,
693 return FuseTwoAddrInst(Entry->to, FrameIndex, MI);
695 return FuseInst(Entry->to, i, FrameIndex, MI);
700 if (PrintFailedFusing)
701 std::cerr << "We failed to fuse ("
702 << ((i == 1) ? "r" : "s") << "): " << *MI;
707 const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
708 static const unsigned CalleeSaveRegs[] = {
709 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
711 return CalleeSaveRegs;
714 const TargetRegisterClass* const*
715 X86RegisterInfo::getCalleeSaveRegClasses() const {
716 static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
717 &X86::GR32RegClass, &X86::GR32RegClass,
718 &X86::GR32RegClass, &X86::GR32RegClass, 0
720 return CalleeSaveRegClasses;
723 //===----------------------------------------------------------------------===//
724 // Stack Frame Processing methods
725 //===----------------------------------------------------------------------===//
727 // hasFP - Return true if the specified function should have a dedicated frame
728 // pointer register. This is true if the function has variable sized allocas or
729 // if frame pointer elimination is disabled.
731 static bool hasFP(const MachineFunction &MF) {
732 return (NoFramePointerElim ||
733 MF.getFrameInfo()->hasVarSizedObjects() ||
734 MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
737 void X86RegisterInfo::
738 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
739 MachineBasicBlock::iterator I) const {
741 // If we have a frame pointer, turn the adjcallstackup instruction into a
742 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
744 MachineInstr *Old = I;
745 unsigned Amount = Old->getOperand(0).getImmedValue();
747 // We need to keep the stack aligned properly. To do this, we round the
748 // amount of space needed for the outgoing arguments up to the next
749 // alignment boundary.
750 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
751 Amount = (Amount+Align-1)/Align*Align;
753 MachineInstr *New = 0;
754 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
755 New=BuildMI(X86::SUB32ri, 2, X86::ESP).addReg(X86::ESP).addImm(Amount);
757 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
758 // factor out the amount the callee already popped.
759 unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
762 unsigned Opc = Amount < 128 ? X86::ADD32ri8 : X86::ADD32ri;
763 New = BuildMI(Opc, 2, X86::ESP).addReg(X86::ESP).addImm(Amount);
767 // Replace the pseudo instruction with a new instruction...
768 if (New) MBB.insert(I, New);
770 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
771 // If we are performing frame pointer elimination and if the callee pops
772 // something off the stack pointer, add it back. We do this until we have
773 // more advanced stack pointer tracking ability.
774 if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
775 unsigned Opc = CalleeAmt < 128 ? X86::SUB32ri8 : X86::SUB32ri;
777 BuildMI(Opc, 1, X86::ESP).addReg(X86::ESP).addImm(CalleeAmt);
785 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
787 MachineInstr &MI = *II;
788 MachineFunction &MF = *MI.getParent()->getParent();
789 while (!MI.getOperand(i).isFrameIndex()) {
791 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
794 int FrameIndex = MI.getOperand(i).getFrameIndex();
796 // This must be part of a four operand memory reference. Replace the
797 // FrameIndex with base register with EBP. Add add an offset to the offset.
798 MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
800 // Now add the frame object offset to the offset from EBP.
801 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
802 MI.getOperand(i+3).getImmedValue()+4;
805 Offset += MF.getFrameInfo()->getStackSize();
807 Offset += 4; // Skip the saved EBP
809 MI.getOperand(i+3).ChangeToImmediate(Offset);
813 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
815 // Create a frame entry for the EBP register that must be saved.
816 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, -8);
817 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
818 "Slot for EBP register must be last in order to be found!");
822 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
823 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
824 MachineBasicBlock::iterator MBBI = MBB.begin();
825 MachineFrameInfo *MFI = MF.getFrameInfo();
826 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
827 const Function* Fn = MF.getFunction();
828 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
831 // Get the number of bytes to allocate from the FrameInfo
832 unsigned NumBytes = MFI->getStackSize();
833 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
834 // When we have no frame pointer, we reserve argument space for call sites
835 // in the function immediately on entry to the current function. This
836 // eliminates the need for add/sub ESP brackets around call sites.
839 NumBytes += MFI->getMaxCallFrameSize();
841 // Round the size to a multiple of the alignment (don't forget the 4 byte
843 NumBytes = ((NumBytes+4)+Align-1)/Align*Align - 4;
846 // Update frame info to pretend that this is part of the stack...
847 MFI->setStackSize(NumBytes);
849 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
850 if (NumBytes >= 4096 && Subtarget->TargetType == X86Subtarget::isCygwin) {
851 // Function prologue calls _alloca to probe the stack when allocating
852 // more than 4k bytes in one go. Touching the stack at 4K increments is
853 // necessary to ensure that the guard pages used by the OS virtual memory
854 // manager are allocated in correct sequence.
855 MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(NumBytes);
856 MBB.insert(MBBI, MI);
857 MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
858 MBB.insert(MBBI, MI);
860 unsigned Opc = NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
861 MI = BuildMI(Opc, 2, X86::ESP).addReg(X86::ESP).addImm(NumBytes);
862 MBB.insert(MBBI, MI);
867 // Get the offset of the stack slot for the EBP register... which is
868 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
869 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexBegin())+4;
871 // Save EBP into the appropriate stack slot...
872 MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
873 X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
874 MBB.insert(MBBI, MI);
876 // Update EBP with the new base value...
877 if (NumBytes == 4) // mov EBP, ESP
878 MI = BuildMI(X86::MOV32rr, 2, X86::EBP).addReg(X86::ESP);
879 else // lea EBP, [ESP+StackSize]
880 MI = addRegOffset(BuildMI(X86::LEA32r, 5, X86::EBP), X86::ESP,NumBytes-4);
882 MBB.insert(MBBI, MI);
885 // If it's main() on Cygwin\Mingw32 we should align stack as well
886 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
887 Subtarget->TargetType == X86Subtarget::isCygwin) {
888 MI = BuildMI(X86::AND32ri, 2, X86::ESP).addReg(X86::ESP).addImm(-Align);
889 MBB.insert(MBBI, MI);
892 MI = BuildMI(X86::MOV32ri, 2, X86::EAX).addImm(Align);
893 MBB.insert(MBBI, MI);
894 MI = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("_alloca");
895 MBB.insert(MBBI, MI);
899 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
900 MachineBasicBlock &MBB) const {
901 const MachineFrameInfo *MFI = MF.getFrameInfo();
902 MachineBasicBlock::iterator MBBI = prior(MBB.end());
904 switch (MBBI->getOpcode()) {
909 case X86::TAILJMPm: break; // These are ok
911 assert(0 && "Can only insert epilog into returning blocks");
915 // Get the offset of the stack slot for the EBP register... which is
916 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
917 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1)+4;
920 BuildMI(MBB, MBBI, X86::MOV32rr, 1, X86::ESP).addReg(X86::EBP);
923 BuildMI(MBB, MBBI, X86::POP32r, 0, X86::EBP);
925 // Get the number of bytes allocated from the FrameInfo...
926 unsigned NumBytes = MFI->getStackSize();
928 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
929 // If there is an ADD32ri or SUB32ri of ESP immediately before this
930 // instruction, merge the two instructions.
931 if (MBBI != MBB.begin()) {
932 MachineBasicBlock::iterator PI = prior(MBBI);
933 if ((PI->getOpcode() == X86::ADD32ri ||
934 PI->getOpcode() == X86::ADD32ri8) &&
935 PI->getOperand(0).getReg() == X86::ESP) {
936 NumBytes += PI->getOperand(1).getImmedValue();
938 } else if ((PI->getOpcode() == X86::SUB32ri ||
939 PI->getOpcode() == X86::SUB32ri8) &&
940 PI->getOperand(0).getReg() == X86::ESP) {
941 NumBytes -= PI->getOperand(1).getImmedValue();
943 } else if (PI->getOpcode() == X86::ADJSTACKPTRri) {
944 NumBytes += PI->getOperand(1).getImmedValue();
950 unsigned Opc = NumBytes < 128 ? X86::ADD32ri8 : X86::ADD32ri;
951 BuildMI(MBB, MBBI, Opc, 2, X86::ESP).addReg(X86::ESP).addImm(NumBytes);
952 } else if ((int)NumBytes < 0) {
953 unsigned Opc = -NumBytes < 128 ? X86::SUB32ri8 : X86::SUB32ri;
954 BuildMI(MBB, MBBI, Opc, 2, X86::ESP).addReg(X86::ESP).addImm(-NumBytes);
960 unsigned X86RegisterInfo::getRARegister() const {
961 return X86::ST0; // use a non-register register
964 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
965 return hasFP(MF) ? X86::EBP : X86::ESP;
969 unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) {
976 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
978 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
980 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
982 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
988 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
990 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
992 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
994 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
1000 default: return Reg;
1001 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
1003 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
1005 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
1007 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
1020 default: return true;
1021 case X86::AH: case X86::AL: case X86::AX: case X86::EAX:
1023 case X86::DH: case X86::DL: case X86::DX: case X86::EDX:
1025 case X86::CH: case X86::CL: case X86::CX: case X86::ECX:
1027 case X86::BH: case X86::BL: case X86::BX: case X86::EBX:
1044 #include "X86GenRegisterInfo.inc"