1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // This file contains the X86 implementation of the MRegisterInfo class. This
4 // file is responsible for the frame pointer elimination optimization on X86.
6 //===----------------------------------------------------------------------===//
9 #include "X86RegisterInfo.h"
10 #include "X86InstrBuilder.h"
11 #include "llvm/Constants.h"
12 #include "llvm/Type.h"
13 #include "llvm/CodeGen/MachineInstrBuilder.h"
14 #include "llvm/CodeGen/MachineFunction.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "Support/CommandLine.h"
20 NoFPElim("no-fp-elim",
21 cl::desc("Disable frame pointer elimination optimization"));
24 static unsigned getIdx(const TargetRegisterClass *RC) {
25 switch (RC->getSize()) {
26 default: assert(0 && "Invalid data size!");
34 void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
35 MachineBasicBlock::iterator &MBBI,
36 unsigned SrcReg, int FrameIdx,
37 const TargetRegisterClass *RC) const {
38 static const unsigned Opcode[] =
39 { X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
40 MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
41 FrameIdx).addReg(SrcReg);
42 MBBI = MBB.insert(MBBI, MI)+1;
45 void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator &MBBI,
47 unsigned DestReg, int FrameIdx,
48 const TargetRegisterClass *RC) const{
49 static const unsigned Opcode[] =
50 { X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
51 MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
53 MBBI = MBB.insert(MBBI, MI)+1;
56 void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
57 MachineBasicBlock::iterator &MBBI,
58 unsigned DestReg, unsigned SrcReg,
59 const TargetRegisterClass *RC) const {
60 static const unsigned Opcode[] =
61 { X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
62 MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
63 MBBI = MBB.insert(MBBI, MI)+1;
66 const unsigned* X86RegisterInfo::getCalleeSaveRegs() const {
67 static const unsigned CalleeSaveRegs[] = {
68 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
70 return CalleeSaveRegs;
74 //===----------------------------------------------------------------------===//
75 // Stack Frame Processing methods
76 //===----------------------------------------------------------------------===//
78 // hasFP - Return true if the specified function should have a dedicated frame
79 // pointer register. This is true if the function has variable sized allocas or
80 // if frame pointer elimination is disabled.
82 static bool hasFP(MachineFunction &MF) {
83 return NoFPElim || MF.getFrameInfo()->hasVarSizedObjects();
86 // hasSPAdjust - Return true if this function has ESP adjustment instructions in
87 // the prolog and epilog which allocate local stack space. This is neccesary
88 // because we elide these instructions if there are no function calls in the
89 // current function (ie, this is a leaf function). In this case, we can refer
90 // beyond the stack pointer because we know that nothing will trample on that
93 static bool hasSPAdjust(MachineFunction &MF) {
94 assert(!hasFP(MF) && "Can only eliminate SP adjustment if no frame-pointer!");
95 return MF.getFrameInfo()->hasCalls();
98 void X86RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
99 MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator &I) const {
101 MachineInstr *New = 0, *Old = *I;;
103 // If we have a frame pointer, turn the adjcallstackup instruction into a
104 // 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
106 unsigned Amount = Old->getOperand(0).getImmedValue();
108 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
109 New=BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
111 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
112 New=BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(Amount);
118 *I = New; // Replace the pseudo instruction with a new instruction...
120 I = MBB.erase(I);// Just delete the pseudo instruction...
124 void X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
125 MachineBasicBlock::iterator &II) const {
127 MachineInstr &MI = **II;
128 while (!MI.getOperand(i).isFrameIndex()) {
130 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
133 int FrameIndex = MI.getOperand(i).getFrameIndex();
135 // This must be part of a four operand memory reference. Replace the
136 // FrameIndex with base register with EBP. Add add an offset to the offset.
137 MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
139 // Now add the frame object offset to the offset from EBP.
140 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
141 MI.getOperand(i+3).getImmedValue();
143 if (!hasFP(MF) && hasSPAdjust(MF)) {
144 const MachineFrameInfo *MFI = MF.getFrameInfo();
145 Offset += MFI->getStackSize() + MFI->getMaxCallFrameSize();
148 MI.SetMachineOperandConst(i+3, MachineOperand::MO_SignExtendedImmed, Offset);
151 void X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF)
154 // Create a frame entry for the EBP register that must be saved.
155 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4);
156 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexEnd()-1 &&
157 "Slot for EBP register must be last in order to be found!");
161 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
162 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
163 MachineBasicBlock::iterator MBBI = MBB.begin();
164 const MachineFrameInfo *MFI = MF.getFrameInfo();
167 // Get the number of bytes to allocate from the FrameInfo
168 unsigned NumBytes = MFI->getStackSize();
170 // Get the offset of the stack slot for the EBP register... which is
171 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
172 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1);
174 MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
175 X86::ESP, EBPOffset).addReg(X86::EBP);
176 MBBI = MBB.insert(MBBI, MI)+1;
178 MI = BuildMI(X86::MOVrr32, 2, X86::EBP).addReg(X86::ESP);
179 MBBI = MBB.insert(MBBI, MI)+1;
181 // If we don't have a frame pointer, and the function contains no call sites
182 // (it's a leaf function), we don't have to emit ANY stack adjustment
183 // instructions at all, we can just refer to the area beyond the stack
184 // pointer. This can be important for small functions.
186 if (!hasSPAdjust(MF)) return;
188 // When we have no frame pointer, we reserve argument space for call sites
189 // in the function immediately on entry to the current function. This
190 // eliminates the need for add/sub ESP brackets around call sites.
192 NumBytes += MFI->getMaxCallFrameSize();
196 // adjust stack pointer: ESP -= numbytes
197 MI = BuildMI(X86::SUBri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
198 MBBI = 1+MBB.insert(MBBI, MI);
202 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
203 MachineBasicBlock &MBB) const {
204 const MachineFrameInfo *MFI = MF.getFrameInfo();
205 MachineBasicBlock::iterator MBBI = MBB.end()-1;
207 assert((*MBBI)->getOpcode() == X86::RET &&
208 "Can only insert epilog into returning blocks");
211 // Get the offset of the stack slot for the EBP register... which is
212 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
213 int EBPOffset = MFI->getObjectOffset(MFI->getObjectIndexEnd()-1);
216 MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
217 MBBI = 1+MBB.insert(MBBI, MI);
219 // mov EBP, [ESP-<offset>]
220 MI = addRegOffset(BuildMI(X86::MOVmr32, 5, X86::EBP), X86::ESP, EBPOffset);
221 MBBI = 1+MBB.insert(MBBI, MI);
223 if (!hasSPAdjust(MF)) return;
225 // Get the number of bytes allocated from the FrameInfo...
226 unsigned NumBytes = MFI->getStackSize();
227 NumBytes += MFI->getMaxCallFrameSize();
229 if (NumBytes) { // adjust stack pointer back: ESP += numbytes
230 MI =BuildMI(X86::ADDri32, 2, X86::ESP).addReg(X86::ESP).addZImm(NumBytes);
231 MBBI = 1+MBB.insert(MBBI, MI);
237 //===----------------------------------------------------------------------===//
238 // Register Class Implementation Code
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
242 // 8 Bit Integer Registers
245 const unsigned ByteRegClassRegs[] = {
246 X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, X86::DH, X86::BH,
249 TargetRegisterClass X86ByteRegisterClassInstance(1, 1, ByteRegClassRegs,
250 ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
252 //===----------------------------------------------------------------------===//
253 // 16 Bit Integer Registers
255 const unsigned ShortRegClassRegs[] = {
256 X86::AX, X86::CX, X86::DX, X86::BX, X86::SI, X86::DI, X86::BP, X86::SP
259 struct R16CL : public TargetRegisterClass {
260 R16CL():TargetRegisterClass(2, 2, ShortRegClassRegs, ShortRegClassRegs+8) {}
261 iterator allocation_order_end(MachineFunction &MF) const {
262 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
263 return end()-2; // Don't allocate SP or BP
265 return end()-1; // Don't allocate SP
267 } X86ShortRegisterClassInstance;
269 //===----------------------------------------------------------------------===//
270 // 32 Bit Integer Registers
272 const unsigned IntRegClassRegs[] = {
273 X86::EAX, X86::ECX, X86::EDX, X86::EBX,
274 X86::ESI, X86::EDI, X86::EBP, X86::ESP
277 struct R32CL : public TargetRegisterClass {
278 R32CL() : TargetRegisterClass(4, 4, IntRegClassRegs, IntRegClassRegs+8) {}
279 iterator allocation_order_end(MachineFunction &MF) const {
280 if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
281 return end()-2; // Don't allocate ESP or EBP
283 return end()-1; // Don't allocate ESP
285 } X86IntRegisterClassInstance;
287 //===----------------------------------------------------------------------===//
288 // Pseudo Floating Point Registers
290 const unsigned PFPRegClassRegs[] = {
291 #define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
292 #include "X86RegisterInfo.def"
295 TargetRegisterClass X86FPRegisterClassInstance(10, 4, PFPRegClassRegs,
296 PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
298 //===----------------------------------------------------------------------===//
299 // Register class array...
301 const TargetRegisterClass * const X86RegClasses[] = {
302 &X86ByteRegisterClassInstance,
303 &X86ShortRegisterClassInstance,
304 &X86IntRegisterClassInstance,
305 &X86FPRegisterClassInstance,
310 // Create static lists to contain register alias sets...
311 #define ALIASLIST(NAME, ...) \
312 static const unsigned NAME[] = { __VA_ARGS__ };
313 #include "X86RegisterInfo.def"
316 // X86Regs - Turn the X86RegisterInfo.def file into a bunch of register
319 static const MRegisterDesc X86Regs[] = {
320 #define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
321 { NAME, ALIAS_SET, FLAGS, TSFLAGS },
322 #include "X86RegisterInfo.def"
325 X86RegisterInfo::X86RegisterInfo()
326 : MRegisterInfo(X86Regs, sizeof(X86Regs)/sizeof(X86Regs[0]),
328 X86RegClasses+sizeof(X86RegClasses)/sizeof(X86RegClasses[0]),
329 X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP) {
334 const TargetRegisterClass*
335 X86RegisterInfo::getRegClassForType(const Type* Ty) const {
336 switch (Ty->getPrimitiveID()) {
338 case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
339 default: assert(0 && "Invalid type to getClass!");
341 case Type::SByteTyID:
342 case Type::UByteTyID: return &X86ByteRegisterClassInstance;
343 case Type::ShortTyID:
344 case Type::UShortTyID: return &X86ShortRegisterClassInstance;
347 case Type::PointerTyID: return &X86IntRegisterClassInstance;
349 case Type::FloatTyID:
350 case Type::DoubleTyID: return &X86FPRegisterClassInstance;