1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 // getDwarfRegNum - This function maps LLVM register identifiers to the
70 // Dwarf specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 // getX86RegNum - This function maps LLVM register identifiers to their X86
93 // specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 LLVM_UNREACHABLE("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const {
156 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
157 if (Subtarget->is64Bit())
158 return &X86::GR64RegClass;
160 return &X86::GR32RegClass;
163 const TargetRegisterClass *
164 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
165 if (RC == &X86::CCRRegClass) {
167 return &X86::GR64RegClass;
169 return &X86::GR32RegClass;
175 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
176 bool callsEHReturn = false;
179 const MachineFrameInfo *MFI = MF->getFrameInfo();
180 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
181 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
184 static const unsigned CalleeSavedRegs32Bit[] = {
185 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
188 static const unsigned CalleeSavedRegs32EHRet[] = {
189 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
192 static const unsigned CalleeSavedRegs64Bit[] = {
193 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
196 static const unsigned CalleeSavedRegs64EHRet[] = {
197 X86::RAX, X86::RDX, X86::RBX, X86::R12,
198 X86::R13, X86::R14, X86::R15, X86::RBP, 0
201 static const unsigned CalleeSavedRegsWin64[] = {
202 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
203 X86::R12, X86::R13, X86::R14, X86::R15,
204 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
205 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
206 X86::XMM14, X86::XMM15, 0
211 return CalleeSavedRegsWin64;
213 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
215 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
219 const TargetRegisterClass* const*
220 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
221 bool callsEHReturn = false;
224 const MachineFrameInfo *MFI = MF->getFrameInfo();
225 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
226 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
229 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
230 &X86::GR32RegClass, &X86::GR32RegClass,
231 &X86::GR32RegClass, &X86::GR32RegClass, 0
233 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
234 &X86::GR32RegClass, &X86::GR32RegClass,
235 &X86::GR32RegClass, &X86::GR32RegClass,
236 &X86::GR32RegClass, &X86::GR32RegClass, 0
238 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
239 &X86::GR64RegClass, &X86::GR64RegClass,
240 &X86::GR64RegClass, &X86::GR64RegClass,
241 &X86::GR64RegClass, &X86::GR64RegClass, 0
243 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
244 &X86::GR64RegClass, &X86::GR64RegClass,
245 &X86::GR64RegClass, &X86::GR64RegClass,
246 &X86::GR64RegClass, &X86::GR64RegClass,
247 &X86::GR64RegClass, &X86::GR64RegClass, 0
249 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
250 &X86::GR64RegClass, &X86::GR64RegClass,
251 &X86::GR64RegClass, &X86::GR64RegClass,
252 &X86::GR64RegClass, &X86::GR64RegClass,
253 &X86::GR64RegClass, &X86::GR64RegClass,
254 &X86::VR128RegClass, &X86::VR128RegClass,
255 &X86::VR128RegClass, &X86::VR128RegClass,
256 &X86::VR128RegClass, &X86::VR128RegClass,
257 &X86::VR128RegClass, &X86::VR128RegClass,
258 &X86::VR128RegClass, &X86::VR128RegClass, 0
263 return CalleeSavedRegClassesWin64;
265 return (callsEHReturn ?
266 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
268 return (callsEHReturn ?
269 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
273 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
274 BitVector Reserved(getNumRegs());
275 // Set the stack-pointer register and its aliases as reserved.
276 Reserved.set(X86::RSP);
277 Reserved.set(X86::ESP);
278 Reserved.set(X86::SP);
279 Reserved.set(X86::SPL);
280 // Set the frame-pointer register and its aliases as reserved if needed.
282 Reserved.set(X86::RBP);
283 Reserved.set(X86::EBP);
284 Reserved.set(X86::BP);
285 Reserved.set(X86::BPL);
287 // Mark the x87 stack registers as reserved, since they don't
288 // behave normally with respect to liveness. We don't fully
289 // model the effects of x87 stack pushes and pops after
291 Reserved.set(X86::ST0);
292 Reserved.set(X86::ST1);
293 Reserved.set(X86::ST2);
294 Reserved.set(X86::ST3);
295 Reserved.set(X86::ST4);
296 Reserved.set(X86::ST5);
297 Reserved.set(X86::ST6);
298 Reserved.set(X86::ST7);
302 //===----------------------------------------------------------------------===//
303 // Stack Frame Processing methods
304 //===----------------------------------------------------------------------===//
306 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
307 unsigned MaxAlign = 0;
308 for (int i = FFI->getObjectIndexBegin(),
309 e = FFI->getObjectIndexEnd(); i != e; ++i) {
310 if (FFI->isDeadObjectIndex(i))
312 unsigned Align = FFI->getObjectAlignment(i);
313 MaxAlign = std::max(MaxAlign, Align);
319 // hasFP - Return true if the specified function should have a dedicated frame
320 // pointer register. This is true if the function has variable sized allocas or
321 // if frame pointer elimination is disabled.
323 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
324 const MachineFrameInfo *MFI = MF.getFrameInfo();
325 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
327 return (NoFramePointerElim ||
328 needsStackRealignment(MF) ||
329 MFI->hasVarSizedObjects() ||
330 MFI->isFrameAddressTaken() ||
331 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
332 (MMI && MMI->callsUnwindInit()));
335 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
336 const MachineFrameInfo *MFI = MF.getFrameInfo();
338 // FIXME: Currently we don't support stack realignment for functions with
339 // variable-sized allocas
340 return (RealignStack &&
341 (MFI->getMaxAlignment() > StackAlign &&
342 !MFI->hasVarSizedObjects()));
345 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
346 return !MF.getFrameInfo()->hasVarSizedObjects();
349 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
350 int &FrameIdx) const {
351 if (Reg == FramePtr && hasFP(MF)) {
352 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
360 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
361 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
362 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
364 if (needsStackRealignment(MF)) {
366 // Skip the saved EBP
369 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
370 assert( (-(Offset + StackSize)) % Align == 0);
372 return Offset + StackSize;
375 // FIXME: Support tail calls
378 return Offset + StackSize;
380 // Skip the saved EBP
383 // Skip the RETADDR move area
384 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
385 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
386 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
392 void X86RegisterInfo::
393 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
394 MachineBasicBlock::iterator I) const {
395 if (!hasReservedCallFrame(MF)) {
396 // If the stack pointer can be changed after prologue, turn the
397 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
398 // adjcallstackdown instruction into 'add ESP, <amt>'
399 // TODO: consider using push / pop instead of sub + store / add
400 MachineInstr *Old = I;
401 uint64_t Amount = Old->getOperand(0).getImm();
403 // We need to keep the stack aligned properly. To do this, we round the
404 // amount of space needed for the outgoing arguments up to the next
405 // alignment boundary.
406 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
408 MachineInstr *New = 0;
409 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
410 New = BuildMI(MF, Old->getDebugLoc(),
411 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
412 StackPtr).addReg(StackPtr).addImm(Amount);
414 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
415 // factor out the amount the callee already popped.
416 uint64_t CalleeAmt = Old->getOperand(1).getImm();
419 unsigned Opc = (Amount < 128) ?
420 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
421 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
422 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
423 .addReg(StackPtr).addImm(Amount);
428 // The EFLAGS implicit def is dead.
429 New->getOperand(3).setIsDead();
431 // Replace the pseudo instruction with a new instruction...
435 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
436 // If we are performing frame pointer elimination and if the callee pops
437 // something off the stack pointer, add it back. We do this until we have
438 // more advanced stack pointer tracking ability.
439 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
440 unsigned Opc = (CalleeAmt < 128) ?
441 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
442 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
443 MachineInstr *Old = I;
445 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
446 StackPtr).addReg(StackPtr).addImm(CalleeAmt);
447 // The EFLAGS implicit def is dead.
448 New->getOperand(3).setIsDead();
457 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
458 int SPAdj, RegScavenger *RS) const{
459 assert(SPAdj == 0 && "Unexpected");
462 MachineInstr &MI = *II;
463 MachineFunction &MF = *MI.getParent()->getParent();
464 while (!MI.getOperand(i).isFI()) {
466 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
469 int FrameIndex = MI.getOperand(i).getIndex();
472 if (needsStackRealignment(MF))
473 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
475 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
477 // This must be part of a four operand memory reference. Replace the
478 // FrameIndex with base register with EBP. Add an offset to the offset.
479 MI.getOperand(i).ChangeToRegister(BasePtr, false);
481 // Now add the frame object offset to the offset from EBP.
482 if (MI.getOperand(i+3).isImm()) {
483 // Offset is a 32-bit integer.
484 int Offset = getFrameIndexOffset(MF, FrameIndex) +
485 (int)(MI.getOperand(i+3).getImm());
487 MI.getOperand(i+3).ChangeToImmediate(Offset);
489 // Offset is symbolic. This is extremely rare.
490 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
491 (uint64_t)MI.getOperand(i+3).getOffset();
492 MI.getOperand(i+3).setOffset(Offset);
497 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
498 RegScavenger *RS) const {
499 MachineFrameInfo *FFI = MF.getFrameInfo();
501 // Calculate and set max stack object alignment early, so we can decide
502 // whether we will need stack realignment (and thus FP).
503 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
504 calculateMaxStackAlignment(FFI));
506 FFI->setMaxAlignment(MaxAlign);
508 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
509 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
510 if (TailCallReturnAddrDelta < 0) {
511 // create RETURNADDR area
521 CreateFixedObject(-TailCallReturnAddrDelta,
522 (-1*SlotSize)+TailCallReturnAddrDelta);
525 assert((TailCallReturnAddrDelta <= 0) &&
526 "The Delta should always be zero or negative");
527 // Create a frame entry for the EBP register that must be saved.
528 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
530 TailCallReturnAddrDelta);
531 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
532 "Slot for EBP register must be last in order to be found!");
537 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
538 /// stack pointer by a constant value.
540 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
541 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
542 const TargetInstrInfo &TII) {
543 bool isSub = NumBytes < 0;
544 uint64_t Offset = isSub ? -NumBytes : NumBytes;
547 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
548 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
550 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
551 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
552 uint64_t Chunk = (1LL << 31) - 1;
553 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
554 DebugLoc::getUnknownLoc());
557 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
559 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
560 .addReg(StackPtr).addImm(ThisVal);
561 // The EFLAGS implicit def is dead.
562 MI->getOperand(3).setIsDead();
567 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
569 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
570 unsigned StackPtr, uint64_t *NumBytes = NULL) {
571 if (MBBI == MBB.begin()) return;
573 MachineBasicBlock::iterator PI = prior(MBBI);
574 unsigned Opc = PI->getOpcode();
575 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
576 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
577 PI->getOperand(0).getReg() == StackPtr) {
579 *NumBytes += PI->getOperand(2).getImm();
581 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
582 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
583 PI->getOperand(0).getReg() == StackPtr) {
585 *NumBytes -= PI->getOperand(2).getImm();
590 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
592 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
593 MachineBasicBlock::iterator &MBBI,
594 unsigned StackPtr, uint64_t *NumBytes = NULL) {
597 if (MBBI == MBB.end()) return;
599 MachineBasicBlock::iterator NI = next(MBBI);
600 if (NI == MBB.end()) return;
602 unsigned Opc = NI->getOpcode();
603 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
604 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
605 NI->getOperand(0).getReg() == StackPtr) {
607 *NumBytes -= NI->getOperand(2).getImm();
610 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
611 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
612 NI->getOperand(0).getReg() == StackPtr) {
614 *NumBytes += NI->getOperand(2).getImm();
620 /// mergeSPUpdates - Checks the instruction before/after the passed
621 /// instruction. If it is an ADD/SUB instruction it is deleted
622 /// argument and the stack adjustment is returned as a positive value for ADD
623 /// and a negative for SUB.
624 static int mergeSPUpdates(MachineBasicBlock &MBB,
625 MachineBasicBlock::iterator &MBBI,
627 bool doMergeWithPrevious) {
629 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
630 (!doMergeWithPrevious && MBBI == MBB.end()))
635 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
636 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
637 unsigned Opc = PI->getOpcode();
638 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
639 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
640 PI->getOperand(0).getReg() == StackPtr){
641 Offset += PI->getOperand(2).getImm();
643 if (!doMergeWithPrevious) MBBI = NI;
644 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
645 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
646 PI->getOperand(0).getReg() == StackPtr) {
647 Offset -= PI->getOperand(2).getImm();
649 if (!doMergeWithPrevious) MBBI = NI;
655 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
657 unsigned FramePtr) const {
658 MachineFrameInfo *MFI = MF.getFrameInfo();
659 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
662 // Add callee saved registers to move list.
663 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
664 if (CSI.empty()) return;
666 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
667 const TargetData *TD = MF.getTarget().getTargetData();
668 bool HasFP = hasFP(MF);
670 // Calculate amount of bytes used for return address storing
672 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
673 TargetFrameInfo::StackGrowsUp ?
674 TD->getPointerSize() : -TD->getPointerSize());
676 // FIXME: This is dirty hack. The code itself is pretty mess right now.
677 // It should be rewritten from scratch and generalized sometimes.
679 // Determine maximum offset (minumum due to stack growth)
680 int64_t MaxOffset = 0;
681 for (std::vector<CalleeSavedInfo>::const_iterator
682 I = CSI.begin(), E = CSI.end(); I != E; ++I)
683 MaxOffset = std::min(MaxOffset,
684 MFI->getObjectOffset(I->getFrameIdx()));
686 // Calculate offsets.
687 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
688 for (std::vector<CalleeSavedInfo>::const_iterator
689 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
690 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
691 unsigned Reg = I->getReg();
692 Offset = MaxOffset - Offset + saveAreaOffset;
694 // Don't output a new machine move if we're re-saving the frame
695 // pointer. This happens when the PrologEpilogInserter has inserted an extra
696 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
697 // generates one when frame pointers are used. If we generate a "machine
698 // move" for this extra "PUSH", the linker will lose track of the fact that
699 // the frame pointer should have the value of the first "PUSH" when it's
702 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
703 // another bug. I.e., one where we generate a prolog like this:
711 // The immediate re-push of EBP is unnecessary. At the least, it's an
712 // optimization bug. EBP can be used as a scratch register in certain
713 // cases, but probably not when we have a frame pointer.
714 if (HasFP && FramePtr == Reg)
717 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
718 MachineLocation CSSrc(Reg);
719 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
723 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
724 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
725 MachineFrameInfo *MFI = MF.getFrameInfo();
726 const Function* Fn = MF.getFunction();
727 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
728 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
729 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
730 MachineBasicBlock::iterator MBBI = MBB.begin();
731 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
732 !Fn->doesNotThrow() ||
733 UnwindTablesMandatory;
734 bool HasFP = hasFP(MF);
737 // Get the number of bytes to allocate from the FrameInfo.
738 uint64_t StackSize = MFI->getStackSize();
740 // Get desired stack alignment
741 uint64_t MaxAlign = MFI->getMaxAlignment();
743 // Add RETADDR move area to callee saved frame size.
744 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
745 if (TailCallReturnAddrDelta < 0)
746 X86FI->setCalleeSavedFrameSize(
747 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
749 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
750 // function, and use up to 128 bytes of stack space, don't have a frame
751 // pointer, calls, or dynamic alloca then we do not need to adjust the
752 // stack pointer (we fit in the Red Zone).
753 bool DisableRedZone = Fn->hasFnAttr(Attribute::NoRedZone);
754 if (Is64Bit && !DisableRedZone &&
755 !needsStackRealignment(MF) &&
756 !MFI->hasVarSizedObjects() && // No dynamic alloca.
757 !MFI->hasCalls() && // No calls.
758 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
759 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
760 if (HasFP) MinSize += SlotSize;
761 StackSize = std::max(MinSize,
762 StackSize > 128 ? StackSize - 128 : 0);
763 MFI->setStackSize(StackSize);
766 // Insert stack pointer adjustment for later moving of return addr. Only
767 // applies to tail call optimized functions where the callee argument stack
768 // size is bigger than the callers.
769 if (TailCallReturnAddrDelta < 0) {
771 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
772 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
773 // The EFLAGS implicit def is dead.
774 MI->getOperand(3).setIsDead();
777 // uint64_t StackSize = MFI->getStackSize();
778 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
779 const TargetData *TD = MF.getTarget().getTargetData();
781 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
782 TargetFrameInfo::StackGrowsUp ?
783 TD->getPointerSize() : -TD->getPointerSize());
785 uint64_t NumBytes = 0;
787 // Calculate required stack adjustment
788 uint64_t FrameSize = StackSize - SlotSize;
789 if (needsStackRealignment(MF))
790 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
792 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
794 // Get the offset of the stack slot for the EBP register, which is
795 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
796 // Update the frame offset adjustment.
797 MFI->setOffsetAdjustment(-NumBytes);
799 // Save EBP/RBP into the appropriate stack slot...
800 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
801 .addReg(FramePtr, RegState::Kill);
803 if (needsFrameMoves) {
804 // Mark effective beginning of when frame pointer becomes valid.
805 unsigned FrameLabelId = MMI->NextLabelID();
806 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
808 // Define the current CFA rule to use the provided offset.
810 MachineLocation SPDst(MachineLocation::VirtualFP);
811 MachineLocation SPSrc(MachineLocation::VirtualFP,
812 HasFP ? 2 * stackGrowth :
813 -StackSize + stackGrowth);
814 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
816 // FIXME: Verify & implement for FP
817 MachineLocation SPDst(StackPtr);
818 MachineLocation SPSrc(StackPtr, stackGrowth);
819 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
822 // Change the rule for the FramePtr to be an "offset" rule.
823 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
824 MachineLocation FPSrc(FramePtr);
825 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
828 // Update EBP with the new base value...
829 BuildMI(MBB, MBBI, DL,
830 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
833 if (needsFrameMoves) {
834 unsigned FrameLabelId = MMI->NextLabelID();
835 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
837 // Define the current CFA to use the EBP/RBP register.
838 MachineLocation FPDst(FramePtr);
839 MachineLocation FPSrc(MachineLocation::VirtualFP);
840 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
843 // Mark the FramePtr as live-in in every block except the entry.
844 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
846 I->addLiveIn(FramePtr);
849 if (needsStackRealignment(MF)) {
851 BuildMI(MBB, MBBI, DL,
852 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
853 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
855 // The EFLAGS implicit def is dead.
856 MI->getOperand(3).setIsDead();
859 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
862 // Skip the callee-saved push instructions.
863 bool RegsSaved = false;
864 while (MBBI != MBB.end() &&
865 (MBBI->getOpcode() == X86::PUSH32r ||
866 MBBI->getOpcode() == X86::PUSH64r)) {
871 if (RegsSaved && needsFrameMoves) {
872 // Mark end of callee-saved push instructions.
873 unsigned LabelId = MMI->NextLabelID();
874 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
876 // Emit DWARF info specifying the offsets of the callee-saved registers.
877 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
880 if (MBBI != MBB.end())
881 DL = MBBI->getDebugLoc();
883 // Adjust stack pointer: ESP -= numbytes.
884 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
885 // Check, whether EAX is livein for this function.
886 bool isEAXAlive = false;
887 for (MachineRegisterInfo::livein_iterator
888 II = MF.getRegInfo().livein_begin(),
889 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
890 unsigned Reg = II->first;
891 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
892 Reg == X86::AH || Reg == X86::AL);
895 // Function prologue calls _alloca to probe the stack when allocating more
896 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
897 // to ensure that the guard pages used by the OS virtual memory manager are
898 // allocated in correct sequence.
900 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
902 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
903 .addExternalSymbol("_alloca");
906 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
907 .addReg(X86::EAX, RegState::Kill);
909 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
910 // allocated bytes for EAX.
911 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
912 .addImm(NumBytes - 4);
913 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
914 .addExternalSymbol("_alloca");
917 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
919 StackPtr, false, NumBytes - 4);
920 MBB.insert(MBBI, MI);
922 } else if (NumBytes) {
923 // If there is an SUB32ri of ESP immediately before this instruction, merge
924 // the two. This can be the case when tail call elimination is enabled and
925 // the callee has more arguments then the caller.
926 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
928 // If there is an ADD32ri or SUB32ri of ESP immediately after this
929 // instruction, merge the two instructions.
930 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
933 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
936 if (!HasFP && needsFrameMoves && NumBytes) {
937 // Mark end of stack pointer adjustment.
938 unsigned LabelId = MMI->NextLabelID();
939 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
941 // Define the current CFA rule to use the provided offset.
943 MachineLocation SPDst(MachineLocation::VirtualFP);
944 MachineLocation SPSrc(MachineLocation::VirtualFP,
945 -StackSize + stackGrowth);
946 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
948 // FIXME: Verify & implement for FP
949 MachineLocation SPDst(StackPtr);
950 MachineLocation SPSrc(StackPtr, stackGrowth);
951 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
956 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
957 MachineBasicBlock &MBB) const {
958 const MachineFrameInfo *MFI = MF.getFrameInfo();
959 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
960 MachineBasicBlock::iterator MBBI = prior(MBB.end());
961 unsigned RetOpcode = MBBI->getOpcode();
962 DebugLoc DL = MBBI->getDebugLoc();
967 case X86::TCRETURNdi:
968 case X86::TCRETURNri:
969 case X86::TCRETURNri64:
970 case X86::TCRETURNdi64:
972 case X86::EH_RETURN64:
975 case X86::TAILJMPm: break; // These are ok
977 LLVM_UNREACHABLE("Can only insert epilog into returning blocks");
980 // Get the number of bytes to allocate from the FrameInfo
981 uint64_t StackSize = MFI->getStackSize();
982 uint64_t MaxAlign = MFI->getMaxAlignment();
983 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
984 uint64_t NumBytes = 0;
987 // Calculate required stack adjustment
988 uint64_t FrameSize = StackSize - SlotSize;
989 if (needsStackRealignment(MF))
990 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
992 NumBytes = FrameSize - CSSize;
995 BuildMI(MBB, MBBI, DL,
996 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
998 NumBytes = StackSize - CSSize;
1001 // Skip the callee-saved pop instructions.
1002 MachineBasicBlock::iterator LastCSPop = MBBI;
1003 while (MBBI != MBB.begin()) {
1004 MachineBasicBlock::iterator PI = prior(MBBI);
1005 unsigned Opc = PI->getOpcode();
1006 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1007 !PI->getDesc().isTerminator())
1012 DL = MBBI->getDebugLoc();
1014 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1015 // instruction, merge the two instructions.
1016 if (NumBytes || MFI->hasVarSizedObjects())
1017 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1019 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1020 // slot before popping them off! Same applies for the case, when stack was
1022 if (needsStackRealignment(MF)) {
1023 // We cannot use LEA here, because stack pointer was realigned. We need to
1024 // deallocate local frame back
1026 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1027 MBBI = prior(LastCSPop);
1030 BuildMI(MBB, MBBI, DL,
1031 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1032 StackPtr).addReg(FramePtr);
1033 } else if (MFI->hasVarSizedObjects()) {
1035 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1036 MachineInstr *MI = addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1037 FramePtr, false, -CSSize);
1038 MBB.insert(MBBI, MI);
1040 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1041 StackPtr).addReg(FramePtr);
1044 // adjust stack pointer back: ESP += numbytes
1046 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1049 // We're returning from function via eh_return.
1050 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1051 MBBI = prior(MBB.end());
1052 MachineOperand &DestAddr = MBBI->getOperand(0);
1053 assert(DestAddr.isReg() && "Offset should be in register!");
1054 BuildMI(MBB, MBBI, DL,
1055 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1056 StackPtr).addReg(DestAddr.getReg());
1057 // Tail call return: adjust the stack pointer and jump to callee
1058 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1059 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1060 MBBI = prior(MBB.end());
1061 MachineOperand &JumpTarget = MBBI->getOperand(0);
1062 MachineOperand &StackAdjust = MBBI->getOperand(1);
1063 assert(StackAdjust.isImm() && "Expecting immediate value.");
1065 // Adjust stack pointer.
1066 int StackAdj = StackAdjust.getImm();
1067 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1069 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1070 // Incoporate the retaddr area.
1071 Offset = StackAdj-MaxTCDelta;
1072 assert(Offset >= 0 && "Offset should never be negative");
1075 // Check for possible merge with preceeding ADD instruction.
1076 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1077 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1080 // Jump to label or value in register.
1081 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
1082 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1083 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1084 else if (RetOpcode== X86::TCRETURNri64)
1085 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1087 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1089 // Delete the pseudo instruction TCRETURN.
1091 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1092 (X86FI->getTCReturnAddrDelta() < 0)) {
1093 // Add the return addr area delta back since we are not tail calling.
1094 int delta = -1*X86FI->getTCReturnAddrDelta();
1095 MBBI = prior(MBB.end());
1096 // Check for possible merge with preceeding ADD instruction.
1097 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1098 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1102 unsigned X86RegisterInfo::getRARegister() const {
1104 return X86::RIP; // Should have dwarf #16
1106 return X86::EIP; // Should have dwarf #8
1109 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
1110 return hasFP(MF) ? FramePtr : StackPtr;
1113 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
1115 // Calculate amount of bytes used for return address storing
1116 int stackGrowth = (Is64Bit ? -8 : -4);
1118 // Initial state of the frame pointer is esp+4.
1119 MachineLocation Dst(MachineLocation::VirtualFP);
1120 MachineLocation Src(StackPtr, stackGrowth);
1121 Moves.push_back(MachineMove(0, Dst, Src));
1123 // Add return address to move list
1124 MachineLocation CSDst(StackPtr, stackGrowth);
1125 MachineLocation CSSrc(getRARegister());
1126 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1129 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1130 LLVM_UNREACHABLE("What is the exception register");
1134 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1135 LLVM_UNREACHABLE("What is the exception handler register");
1140 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
1141 switch (VT.getSimpleVT()) {
1142 default: return Reg;
1147 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1149 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1151 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1153 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1159 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1161 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1163 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1165 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1167 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1169 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1171 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1173 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1175 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1177 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1179 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1181 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1183 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1185 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1187 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1189 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1195 default: return Reg;
1196 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1198 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1200 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1202 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1204 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1206 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1208 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1210 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1212 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1214 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1216 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1218 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1220 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1222 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1224 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1226 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1231 default: return Reg;
1232 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1234 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1236 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1238 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1240 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1242 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1244 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1246 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1248 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1250 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1252 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1254 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1256 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1258 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1260 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1262 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1267 default: return Reg;
1268 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1270 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1272 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1274 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1276 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1278 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1280 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1282 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1284 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1286 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1288 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1290 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1292 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1294 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1296 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1298 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1307 #include "X86GenRegisterInfo.inc"
1310 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1312 MSAC() : MachineFunctionPass(&ID) {}
1314 virtual bool runOnMachineFunction(MachineFunction &MF) {
1315 MachineFrameInfo *FFI = MF.getFrameInfo();
1316 MachineRegisterInfo &RI = MF.getRegInfo();
1318 // Calculate max stack alignment of all already allocated stack objects.
1319 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1321 // Be over-conservative: scan over all vreg defs and find, whether vector
1322 // registers are used. If yes - there is probability, that vector register
1323 // will be spilled and thus stack needs to be aligned properly.
1324 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1325 RegNum < RI.getLastVirtReg(); ++RegNum)
1326 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1328 FFI->setMaxAlignment(MaxAlign);
1333 virtual const char *getPassName() const {
1334 return "X86 Maximal Stack Alignment Calculator";
1342 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }