1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/CommandLine.h"
45 ForceStackAlign("force-align-stack",
46 cl::desc("Force align the stack to the minimum alignment"
47 " needed for the function."),
48 cl::init(false), cl::Hidden);
50 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
51 const TargetInstrInfo &tii)
52 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
53 X86::ADJCALLSTACKDOWN64 :
54 X86::ADJCALLSTACKDOWN32,
55 tm.getSubtarget<X86Subtarget>().is64Bit() ?
56 X86::ADJCALLSTACKUP64 :
57 X86::ADJCALLSTACKUP32),
59 // Cache some information.
60 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
61 Is64Bit = Subtarget->is64Bit();
62 IsWin64 = Subtarget->isTargetWin64();
63 StackAlign = TM.getFrameLowering()->getStackAlignment();
76 static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
77 if (!Subtarget->is64Bit()) {
78 if (Subtarget->isTargetDarwin()) {
80 return DWARFFlavour::X86_32_DarwinEH;
82 return DWARFFlavour::X86_32_Generic;
83 } else if (Subtarget->isTargetCygMing()) {
84 // Unsupported by now, just quick fallback
85 return DWARFFlavour::X86_32_Generic;
87 return DWARFFlavour::X86_32_Generic;
90 return DWARFFlavour::X86_64;
93 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
94 /// specific numbering, used in debug info and exception tables.
95 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
96 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
97 unsigned Flavour = getFlavour(Subtarget, isEH);
99 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
102 /// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
103 int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
104 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
105 unsigned Flavour = getFlavour(Subtarget, isEH);
107 return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
111 X86RegisterInfo::getSEHRegNum(unsigned i) const {
112 int reg = getX86RegNum(i);
114 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
115 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
116 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
117 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
120 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
121 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
122 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
123 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
124 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
125 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
131 /// getX86RegNum - This function maps LLVM register identifiers to their X86
132 /// specific numbering, which is used in various places encoding instructions.
133 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
135 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
136 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
137 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
138 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
139 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
141 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
143 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
145 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
148 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
150 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
152 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
154 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
156 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
158 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
160 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
162 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
165 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
166 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
167 return RegNo-X86::ST0;
169 case X86::XMM0: case X86::XMM8:
170 case X86::YMM0: case X86::YMM8: case X86::MM0:
172 case X86::XMM1: case X86::XMM9:
173 case X86::YMM1: case X86::YMM9: case X86::MM1:
175 case X86::XMM2: case X86::XMM10:
176 case X86::YMM2: case X86::YMM10: case X86::MM2:
178 case X86::XMM3: case X86::XMM11:
179 case X86::YMM3: case X86::YMM11: case X86::MM3:
181 case X86::XMM4: case X86::XMM12:
182 case X86::YMM4: case X86::YMM12: case X86::MM4:
184 case X86::XMM5: case X86::XMM13:
185 case X86::YMM5: case X86::YMM13: case X86::MM5:
187 case X86::XMM6: case X86::XMM14:
188 case X86::YMM6: case X86::YMM14: case X86::MM6:
190 case X86::XMM7: case X86::XMM15:
191 case X86::YMM7: case X86::YMM15: case X86::MM7:
194 case X86::ES: return 0;
195 case X86::CS: return 1;
196 case X86::SS: return 2;
197 case X86::DS: return 3;
198 case X86::FS: return 4;
199 case X86::GS: return 5;
201 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
202 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
203 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
204 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
205 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
206 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
207 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
208 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
210 // Pseudo index registers are equivalent to a "none"
211 // scaled index (See Intel Manual 2A, table 2-3)
217 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
218 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
223 const TargetRegisterClass *
224 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
225 const TargetRegisterClass *B,
226 unsigned SubIdx) const {
230 if (B == &X86::GR8RegClass) {
231 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
233 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
234 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
235 A == &X86::GR64_NOREXRegClass ||
236 A == &X86::GR64_NOSPRegClass ||
237 A == &X86::GR64_NOREX_NOSPRegClass)
238 return &X86::GR64_ABCDRegClass;
239 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
240 A == &X86::GR32_NOREXRegClass ||
241 A == &X86::GR32_NOSPRegClass)
242 return &X86::GR32_ABCDRegClass;
243 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
244 A == &X86::GR16_NOREXRegClass)
245 return &X86::GR16_ABCDRegClass;
246 } else if (B == &X86::GR8_NOREXRegClass) {
247 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
248 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
249 return &X86::GR64_NOREXRegClass;
250 else if (A == &X86::GR64_ABCDRegClass)
251 return &X86::GR64_ABCDRegClass;
252 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
253 A == &X86::GR32_NOSPRegClass)
254 return &X86::GR32_NOREXRegClass;
255 else if (A == &X86::GR32_ABCDRegClass)
256 return &X86::GR32_ABCDRegClass;
257 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
258 return &X86::GR16_NOREXRegClass;
259 else if (A == &X86::GR16_ABCDRegClass)
260 return &X86::GR16_ABCDRegClass;
263 case X86::sub_8bit_hi:
264 if (B == &X86::GR8_ABCD_HRegClass ||
265 B->hasSubClass(&X86::GR8_ABCD_HRegClass))
266 switch (A->getSize()) {
267 case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
268 case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
269 case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
274 if (B == &X86::GR16RegClass) {
275 if (A->getSize() == 4 || A->getSize() == 8)
277 } else if (B == &X86::GR16_ABCDRegClass) {
278 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
279 A == &X86::GR64_NOREXRegClass ||
280 A == &X86::GR64_NOSPRegClass ||
281 A == &X86::GR64_NOREX_NOSPRegClass)
282 return &X86::GR64_ABCDRegClass;
283 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
284 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
285 return &X86::GR32_ABCDRegClass;
286 } else if (B == &X86::GR16_NOREXRegClass) {
287 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
288 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
289 return &X86::GR64_NOREXRegClass;
290 else if (A == &X86::GR64_ABCDRegClass)
291 return &X86::GR64_ABCDRegClass;
292 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
293 A == &X86::GR32_NOSPRegClass)
294 return &X86::GR32_NOREXRegClass;
295 else if (A == &X86::GR32_ABCDRegClass)
296 return &X86::GR64_ABCDRegClass;
300 if (B == &X86::GR32RegClass) {
301 if (A->getSize() == 8)
303 } else if (B == &X86::GR32_NOSPRegClass) {
304 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
305 return &X86::GR64_NOSPRegClass;
306 if (A->getSize() == 8)
307 return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
308 } else if (B == &X86::GR32_ABCDRegClass) {
309 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
310 A == &X86::GR64_NOREXRegClass ||
311 A == &X86::GR64_NOSPRegClass ||
312 A == &X86::GR64_NOREX_NOSPRegClass)
313 return &X86::GR64_ABCDRegClass;
314 } else if (B == &X86::GR32_NOREXRegClass) {
315 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
316 return &X86::GR64_NOREXRegClass;
317 else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
318 return &X86::GR64_NOREX_NOSPRegClass;
319 else if (A == &X86::GR64_ABCDRegClass)
320 return &X86::GR64_ABCDRegClass;
321 } else if (B == &X86::GR32_NOREX_NOSPRegClass) {
322 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
323 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
324 return &X86::GR64_NOREX_NOSPRegClass;
325 else if (A == &X86::GR64_ABCDRegClass)
326 return &X86::GR64_ABCDRegClass;
330 if (B == &X86::FR32RegClass)
334 if (B == &X86::FR64RegClass)
338 if (B == &X86::VR128RegClass)
345 const TargetRegisterClass*
346 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
347 const TargetRegisterClass *Super = RC;
348 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
350 switch (Super->getID()) {
351 case X86::GR8RegClassID:
352 case X86::GR16RegClassID:
353 case X86::GR32RegClassID:
354 case X86::GR64RegClassID:
355 case X86::FR32RegClassID:
356 case X86::FR64RegClassID:
357 case X86::RFP32RegClassID:
358 case X86::RFP64RegClassID:
359 case X86::RFP80RegClassID:
360 case X86::VR128RegClassID:
361 case X86::VR256RegClassID:
362 // Don't return a super-class that would shrink the spill size.
363 // That can happen with the vector and float classes.
364 if (Super->getSize() == RC->getSize())
372 const TargetRegisterClass *
373 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
375 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
376 case 0: // Normal GPRs.
377 if (TM.getSubtarget<X86Subtarget>().is64Bit())
378 return &X86::GR64RegClass;
379 return &X86::GR32RegClass;
380 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
381 if (TM.getSubtarget<X86Subtarget>().is64Bit())
382 return &X86::GR64_NOSPRegClass;
383 return &X86::GR32_NOSPRegClass;
384 case 2: // Available for tailcall (not callee-saved GPRs).
385 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
386 return &X86::GR64_TCW64RegClass;
387 if (TM.getSubtarget<X86Subtarget>().is64Bit())
388 return &X86::GR64_TCRegClass;
389 return &X86::GR32_TCRegClass;
393 const TargetRegisterClass *
394 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
395 if (RC == &X86::CCRRegClass) {
397 return &X86::GR64RegClass;
399 return &X86::GR32RegClass;
405 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
406 MachineFunction &MF) const {
407 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
409 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
410 switch (RC->getID()) {
413 case X86::GR32RegClassID:
415 case X86::GR64RegClassID:
417 case X86::VR128RegClassID:
418 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
419 case X86::VR64RegClassID:
425 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
426 bool callsEHReturn = false;
427 bool ghcCall = false;
430 callsEHReturn = MF->getMMI().callsEHReturn();
431 const Function *F = MF->getFunction();
432 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
435 static const unsigned GhcCalleeSavedRegs[] = {
439 static const unsigned CalleeSavedRegs32Bit[] = {
440 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
443 static const unsigned CalleeSavedRegs32EHRet[] = {
444 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
447 static const unsigned CalleeSavedRegs64Bit[] = {
448 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
451 static const unsigned CalleeSavedRegs64EHRet[] = {
452 X86::RAX, X86::RDX, X86::RBX, X86::R12,
453 X86::R13, X86::R14, X86::R15, X86::RBP, 0
456 static const unsigned CalleeSavedRegsWin64[] = {
457 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
458 X86::R12, X86::R13, X86::R14, X86::R15,
459 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
460 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
461 X86::XMM14, X86::XMM15, 0
465 return GhcCalleeSavedRegs;
466 } else if (Is64Bit) {
468 return CalleeSavedRegsWin64;
470 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
472 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
476 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
477 BitVector Reserved(getNumRegs());
478 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
480 // Set the stack-pointer register and its aliases as reserved.
481 Reserved.set(X86::RSP);
482 Reserved.set(X86::ESP);
483 Reserved.set(X86::SP);
484 Reserved.set(X86::SPL);
486 // Set the instruction pointer register and its aliases as reserved.
487 Reserved.set(X86::RIP);
488 Reserved.set(X86::EIP);
489 Reserved.set(X86::IP);
491 // Set the frame-pointer register and its aliases as reserved if needed.
492 if (TFI->hasFP(MF)) {
493 Reserved.set(X86::RBP);
494 Reserved.set(X86::EBP);
495 Reserved.set(X86::BP);
496 Reserved.set(X86::BPL);
499 // Mark the x87 stack registers as reserved, since they don't behave normally
500 // with respect to liveness. We don't fully model the effects of x87 stack
501 // pushes and pops after stackification.
502 Reserved.set(X86::ST0);
503 Reserved.set(X86::ST1);
504 Reserved.set(X86::ST2);
505 Reserved.set(X86::ST3);
506 Reserved.set(X86::ST4);
507 Reserved.set(X86::ST5);
508 Reserved.set(X86::ST6);
509 Reserved.set(X86::ST7);
511 // Mark the segment registers as reserved.
512 Reserved.set(X86::CS);
513 Reserved.set(X86::SS);
514 Reserved.set(X86::DS);
515 Reserved.set(X86::ES);
516 Reserved.set(X86::FS);
517 Reserved.set(X86::GS);
522 //===----------------------------------------------------------------------===//
523 // Stack Frame Processing methods
524 //===----------------------------------------------------------------------===//
526 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
527 const MachineFrameInfo *MFI = MF.getFrameInfo();
528 return (RealignStack &&
529 !MFI->hasVarSizedObjects());
532 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
533 const MachineFrameInfo *MFI = MF.getFrameInfo();
534 const Function *F = MF.getFunction();
535 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
536 F->hasFnAttr(Attribute::StackAlignment));
538 // FIXME: Currently we don't support stack realignment for functions with
539 // variable-sized allocas.
540 // FIXME: It's more complicated than this...
541 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
543 "Stack realignment in presence of dynamic allocas is not supported");
545 // If we've requested that we force align the stack do so now.
547 return canRealignStack(MF);
549 return requiresRealignment && canRealignStack(MF);
552 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
553 unsigned Reg, int &FrameIdx) const {
554 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
556 if (Reg == FramePtr && TFI->hasFP(MF)) {
557 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
563 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
566 return X86::SUB64ri8;
567 return X86::SUB64ri32;
570 return X86::SUB32ri8;
575 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
578 return X86::ADD64ri8;
579 return X86::ADD64ri32;
582 return X86::ADD32ri8;
587 void X86RegisterInfo::
588 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
589 MachineBasicBlock::iterator I) const {
590 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
591 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
592 int Opcode = I->getOpcode();
593 bool isDestroy = Opcode == getCallFrameDestroyOpcode();
594 DebugLoc DL = I->getDebugLoc();
595 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
596 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
599 if (!reseveCallFrame) {
600 // If the stack pointer can be changed after prologue, turn the
601 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
602 // adjcallstackdown instruction into 'add ESP, <amt>'
603 // TODO: consider using push / pop instead of sub + store / add
607 // We need to keep the stack aligned properly. To do this, we round the
608 // amount of space needed for the outgoing arguments up to the next
609 // alignment boundary.
610 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
612 MachineInstr *New = 0;
613 if (Opcode == getCallFrameSetupOpcode()) {
614 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
619 assert(Opcode == getCallFrameDestroyOpcode());
621 // Factor out the amount the callee already popped.
625 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
626 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
627 .addReg(StackPtr).addImm(Amount);
632 // The EFLAGS implicit def is dead.
633 New->getOperand(3).setIsDead();
635 // Replace the pseudo instruction with a new instruction.
642 if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) {
643 // If we are performing frame pointer elimination and if the callee pops
644 // something off the stack pointer, add it back. We do this until we have
645 // more advanced stack pointer tracking ability.
646 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
647 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
648 .addReg(StackPtr).addImm(CalleeAmt);
650 // The EFLAGS implicit def is dead.
651 New->getOperand(3).setIsDead();
657 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
658 int SPAdj, RegScavenger *RS) const{
659 assert(SPAdj == 0 && "Unexpected");
662 MachineInstr &MI = *II;
663 MachineFunction &MF = *MI.getParent()->getParent();
664 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
666 while (!MI.getOperand(i).isFI()) {
668 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
671 int FrameIndex = MI.getOperand(i).getIndex();
674 unsigned Opc = MI.getOpcode();
675 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
676 if (needsStackRealignment(MF))
677 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
681 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
683 // This must be part of a four operand memory reference. Replace the
684 // FrameIndex with base register with EBP. Add an offset to the offset.
685 MI.getOperand(i).ChangeToRegister(BasePtr, false);
687 // Now add the frame object offset to the offset from EBP.
690 // Tail call jmp happens after FP is popped.
691 const MachineFrameInfo *MFI = MF.getFrameInfo();
692 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
694 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
696 if (MI.getOperand(i+3).isImm()) {
697 // Offset is a 32-bit integer.
698 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
699 MI.getOperand(i + 3).ChangeToImmediate(Offset);
701 // Offset is symbolic. This is extremely rare.
702 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
703 MI.getOperand(i+3).setOffset(Offset);
707 unsigned X86RegisterInfo::getRARegister() const {
708 return Is64Bit ? X86::RIP // Should have dwarf #16.
709 : X86::EIP; // Should have dwarf #8.
712 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
713 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
714 return TFI->hasFP(MF) ? FramePtr : StackPtr;
717 unsigned X86RegisterInfo::getEHExceptionRegister() const {
718 llvm_unreachable("What is the exception register");
722 unsigned X86RegisterInfo::getEHHandlerRegister() const {
723 llvm_unreachable("What is the exception handler register");
728 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
729 switch (VT.getSimpleVT().SimpleTy) {
735 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
737 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
739 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
741 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
747 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
749 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
751 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
753 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
755 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
757 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
759 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
761 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
763 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
765 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
767 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
769 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
771 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
773 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
775 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
777 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
784 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
786 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
788 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
790 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
792 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
794 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
796 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
798 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
800 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
802 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
804 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
806 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
808 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
810 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
812 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
814 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
820 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
822 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
824 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
826 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
828 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
830 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
832 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
834 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
836 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
838 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
840 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
842 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
844 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
846 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
848 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
850 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
856 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
858 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
860 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
862 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
864 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
866 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
868 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
870 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
872 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
874 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
876 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
878 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
880 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
882 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
884 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
886 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
895 #include "X86GenRegisterInfo.inc"
898 struct MSAH : public MachineFunctionPass {
900 MSAH() : MachineFunctionPass(ID) {}
902 virtual bool runOnMachineFunction(MachineFunction &MF) {
903 const X86TargetMachine *TM =
904 static_cast<const X86TargetMachine *>(&MF.getTarget());
905 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
906 MachineRegisterInfo &RI = MF.getRegInfo();
907 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
908 unsigned StackAlignment = X86RI->getStackAlignment();
910 // Be over-conservative: scan over all vreg defs and find whether vector
911 // registers are used. If yes, there is a possibility that vector register
912 // will be spilled and thus require dynamic stack realignment.
913 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
914 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
915 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
916 FuncInfo->setReserveFP(true);
924 virtual const char *getPassName() const {
925 return "X86 Maximal Stack Alignment Check";
928 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
929 AU.setPreservesCFG();
930 MachineFunctionPass::getAnalysisUsage(AU);
938 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }