1 //===-- X86RegisterInfo.cpp - X86 Register Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
16 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/MC/MCAsmInfo.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/ADT/BitVector.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/CommandLine.h"
42 #define GET_REGINFO_TARGET_DESC
43 #include "X86GenRegisterInfo.inc"
48 ForceStackAlign("force-align-stack",
49 cl::desc("Force align the stack to the minimum alignment"
50 " needed for the function."),
51 cl::init(false), cl::Hidden);
54 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
55 cl::desc("Enable use of a base pointer for complex stack frames"));
57 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
58 const TargetInstrInfo &tii)
59 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit()
60 ? X86::RIP : X86::EIP,
61 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
62 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
64 X86_MC::InitLLVM2SEHRegisterMapping(this);
66 // Cache some information.
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 Is64Bit = Subtarget->is64Bit();
69 IsWin64 = Subtarget->isTargetWin64();
80 // Use a callee-saved register as the base pointer. These registers must
81 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
82 // requires GOT in the EBX register before function calls via PLT GOT pointer.
83 BasePtr = Is64Bit ? X86::RBX : X86::ESI;
86 /// getCompactUnwindRegNum - This function maps the register to the number for
87 /// compact unwind encoding. Return -1 if the register isn't valid.
88 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const {
89 switch (getLLVMRegNum(RegNum, isEH)) {
90 case X86::EBX: case X86::RBX: return 1;
91 case X86::ECX: case X86::R12: return 2;
92 case X86::EDX: case X86::R13: return 3;
93 case X86::EDI: case X86::R14: return 4;
94 case X86::ESI: case X86::R15: return 5;
95 case X86::EBP: case X86::RBP: return 6;
102 X86RegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
103 // Only enable when post-RA scheduling is enabled and this is needed.
104 return TM.getSubtargetImpl()->postRAScheduler();
108 X86RegisterInfo::getSEHRegNum(unsigned i) const {
109 return getEncodingValue(i);
112 const TargetRegisterClass *
113 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
114 unsigned Idx) const {
115 // The sub_8bit sub-register index is more constrained in 32-bit mode.
116 // It behaves just like the sub_8bit_hi index.
117 if (!Is64Bit && Idx == X86::sub_8bit)
118 Idx = X86::sub_8bit_hi;
120 // Forward to TableGen's default version.
121 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
124 const TargetRegisterClass *
125 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
126 const TargetRegisterClass *B,
127 unsigned SubIdx) const {
128 // The sub_8bit sub-register index is more constrained in 32-bit mode.
129 if (!Is64Bit && SubIdx == X86::sub_8bit) {
130 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
134 return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
137 const TargetRegisterClass*
138 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
139 // Don't allow super-classes of GR8_NOREX. This class is only used after
140 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied
141 // to the full GR8 register class in 64-bit mode, so we cannot allow the
142 // reigster class inflation.
144 // The GR8_NOREX class is always used in a way that won't be constrained to a
145 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
147 if (RC == &X86::GR8_NOREXRegClass)
150 const TargetRegisterClass *Super = RC;
151 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
153 switch (Super->getID()) {
154 case X86::GR8RegClassID:
155 case X86::GR16RegClassID:
156 case X86::GR32RegClassID:
157 case X86::GR64RegClassID:
158 case X86::FR32RegClassID:
159 case X86::FR64RegClassID:
160 case X86::RFP32RegClassID:
161 case X86::RFP64RegClassID:
162 case X86::RFP80RegClassID:
163 case X86::VR128RegClassID:
164 case X86::VR256RegClassID:
165 // Don't return a super-class that would shrink the spill size.
166 // That can happen with the vector and float classes.
167 if (Super->getSize() == RC->getSize())
175 const TargetRegisterClass *
176 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
179 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
180 case 0: // Normal GPRs.
181 if (TM.getSubtarget<X86Subtarget>().is64Bit())
182 return &X86::GR64RegClass;
183 return &X86::GR32RegClass;
184 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
185 if (TM.getSubtarget<X86Subtarget>().is64Bit())
186 return &X86::GR64_NOSPRegClass;
187 return &X86::GR32_NOSPRegClass;
188 case 2: // Available for tailcall (not callee-saved GPRs).
189 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
190 return &X86::GR64_TCW64RegClass;
191 if (TM.getSubtarget<X86Subtarget>().is64Bit())
192 return &X86::GR64_TCRegClass;
193 return &X86::GR32_TCRegClass;
197 const TargetRegisterClass *
198 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
199 if (RC == &X86::CCRRegClass) {
201 return &X86::GR64RegClass;
203 return &X86::GR32RegClass;
209 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
210 MachineFunction &MF) const {
211 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
213 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
214 switch (RC->getID()) {
217 case X86::GR32RegClassID:
219 case X86::GR64RegClassID:
221 case X86::VR128RegClassID:
222 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
223 case X86::VR64RegClassID:
229 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
230 bool callsEHReturn = false;
231 bool ghcCall = false;
234 callsEHReturn = MF->getMMI().callsEHReturn();
235 const Function *F = MF->getFunction();
236 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
240 return CSR_NoRegs_SaveList;
243 return CSR_Win64_SaveList;
245 return CSR_64EHRet_SaveList;
246 return CSR_64_SaveList;
249 return CSR_32EHRet_SaveList;
250 return CSR_32_SaveList;
254 X86RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
255 if (CC == CallingConv::GHC)
256 return CSR_NoRegs_RegMask;
258 return CSR_32_RegMask;
260 return CSR_Win64_RegMask;
261 return CSR_64_RegMask;
265 X86RegisterInfo::getNoPreservedMask() const {
266 return CSR_NoRegs_RegMask;
269 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
270 BitVector Reserved(getNumRegs());
271 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
273 // Set the stack-pointer register and its aliases as reserved.
274 Reserved.set(X86::RSP);
275 for (MCSubRegIterator I(X86::RSP, this); I.isValid(); ++I)
278 // Set the instruction pointer register and its aliases as reserved.
279 Reserved.set(X86::RIP);
280 for (MCSubRegIterator I(X86::RIP, this); I.isValid(); ++I)
283 // Set the frame-pointer register and its aliases as reserved if needed.
284 if (TFI->hasFP(MF)) {
285 Reserved.set(X86::RBP);
286 for (MCSubRegIterator I(X86::RBP, this); I.isValid(); ++I)
290 // Set the base-pointer register and its aliases as reserved if needed.
291 if (hasBasePointer(MF)) {
292 CallingConv::ID CC = MF.getFunction()->getCallingConv();
293 const uint32_t* RegMask = getCallPreservedMask(CC);
294 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister()))
296 "Stack realignment in presence of dynamic allocas is not supported with"
297 "this calling convention.");
299 Reserved.set(getBaseRegister());
300 for (MCSubRegIterator I(getBaseRegister(), this); I.isValid(); ++I)
304 // Mark the segment registers as reserved.
305 Reserved.set(X86::CS);
306 Reserved.set(X86::SS);
307 Reserved.set(X86::DS);
308 Reserved.set(X86::ES);
309 Reserved.set(X86::FS);
310 Reserved.set(X86::GS);
312 // Mark the floating point stack registers as reserved.
313 Reserved.set(X86::ST0);
314 Reserved.set(X86::ST1);
315 Reserved.set(X86::ST2);
316 Reserved.set(X86::ST3);
317 Reserved.set(X86::ST4);
318 Reserved.set(X86::ST5);
319 Reserved.set(X86::ST6);
320 Reserved.set(X86::ST7);
322 // Reserve the registers that only exist in 64-bit mode.
324 // These 8-bit registers are part of the x86-64 extension even though their
325 // super-registers are old 32-bits.
326 Reserved.set(X86::SIL);
327 Reserved.set(X86::DIL);
328 Reserved.set(X86::BPL);
329 Reserved.set(X86::SPL);
331 for (unsigned n = 0; n != 8; ++n) {
333 static const uint16_t GPR64[] = {
334 X86::R8, X86::R9, X86::R10, X86::R11,
335 X86::R12, X86::R13, X86::R14, X86::R15
337 for (MCRegAliasIterator AI(GPR64[n], this, true); AI.isValid(); ++AI)
341 assert(X86::XMM15 == X86::XMM8+7);
342 for (MCRegAliasIterator AI(X86::XMM8 + n, this, true); AI.isValid(); ++AI)
350 //===----------------------------------------------------------------------===//
351 // Stack Frame Processing methods
352 //===----------------------------------------------------------------------===//
354 bool X86RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
355 const MachineFrameInfo *MFI = MF.getFrameInfo();
357 if (!EnableBasePointer)
360 // When we need stack realignment and there are dynamic allocas, we can't
361 // reference off of the stack pointer, so we reserve a base pointer.
362 if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
368 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
369 const MachineFrameInfo *MFI = MF.getFrameInfo();
370 const MachineRegisterInfo *MRI = &MF.getRegInfo();
371 if (!MF.getTarget().Options.RealignStack)
374 // Stack realignment requires a frame pointer. If we already started
375 // register allocation with frame pointer elimination, it is too late now.
376 if (!MRI->canReserveReg(FramePtr))
379 // If a base pointer is necessary. Check that it isn't too late to reserve
381 if (MFI->hasVarSizedObjects())
382 return MRI->canReserveReg(BasePtr);
386 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
387 const MachineFrameInfo *MFI = MF.getFrameInfo();
388 const Function *F = MF.getFunction();
389 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
390 bool requiresRealignment =
391 ((MFI->getMaxAlignment() > StackAlign) ||
392 F->getFnAttributes().hasAttribute(Attributes::StackAlignment));
394 // If we've requested that we force align the stack do so now.
396 return canRealignStack(MF);
398 return requiresRealignment && canRealignStack(MF);
401 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
402 unsigned Reg, int &FrameIdx) const {
403 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
405 if (Reg == FramePtr && TFI->hasFP(MF)) {
406 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
412 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
415 return X86::SUB64ri8;
416 return X86::SUB64ri32;
419 return X86::SUB32ri8;
424 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
427 return X86::ADD64ri8;
428 return X86::ADD64ri32;
431 return X86::ADD32ri8;
436 void X86RegisterInfo::
437 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
438 MachineBasicBlock::iterator I) const {
439 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
440 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
441 int Opcode = I->getOpcode();
442 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
443 DebugLoc DL = I->getDebugLoc();
444 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
445 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
448 if (!reseveCallFrame) {
449 // If the stack pointer can be changed after prologue, turn the
450 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
451 // adjcallstackdown instruction into 'add ESP, <amt>'
452 // TODO: consider using push / pop instead of sub + store / add
456 // We need to keep the stack aligned properly. To do this, we round the
457 // amount of space needed for the outgoing arguments up to the next
458 // alignment boundary.
459 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
460 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
462 MachineInstr *New = 0;
463 if (Opcode == TII.getCallFrameSetupOpcode()) {
464 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
469 assert(Opcode == TII.getCallFrameDestroyOpcode());
471 // Factor out the amount the callee already popped.
475 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
476 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
477 .addReg(StackPtr).addImm(Amount);
482 // The EFLAGS implicit def is dead.
483 New->getOperand(3).setIsDead();
485 // Replace the pseudo instruction with a new instruction.
492 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
493 // If we are performing frame pointer elimination and if the callee pops
494 // something off the stack pointer, add it back. We do this until we have
495 // more advanced stack pointer tracking ability.
496 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
497 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
498 .addReg(StackPtr).addImm(CalleeAmt);
500 // The EFLAGS implicit def is dead.
501 New->getOperand(3).setIsDead();
503 // We are not tracking the stack pointer adjustment by the callee, so make
504 // sure we restore the stack pointer immediately after the call, there may
505 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
506 MachineBasicBlock::iterator B = MBB.begin();
507 while (I != B && !llvm::prior(I)->isCall())
514 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
515 int SPAdj, RegScavenger *RS) const {
516 assert(SPAdj == 0 && "Unexpected");
519 MachineInstr &MI = *II;
520 MachineFunction &MF = *MI.getParent()->getParent();
521 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
523 while (!MI.getOperand(i).isFI()) {
525 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
528 int FrameIndex = MI.getOperand(i).getIndex();
531 unsigned Opc = MI.getOpcode();
532 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
533 if (hasBasePointer(MF))
534 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
535 else if (needsStackRealignment(MF))
536 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
540 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
542 // This must be part of a four operand memory reference. Replace the
543 // FrameIndex with base register with EBP. Add an offset to the offset.
544 MI.getOperand(i).ChangeToRegister(BasePtr, false);
546 // Now add the frame object offset to the offset from EBP.
549 // Tail call jmp happens after FP is popped.
550 const MachineFrameInfo *MFI = MF.getFrameInfo();
551 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
553 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
555 if (MI.getOperand(i+3).isImm()) {
556 // Offset is a 32-bit integer.
557 int Imm = (int)(MI.getOperand(i + 3).getImm());
558 int Offset = FIOffset + Imm;
559 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
560 "Requesting 64-bit offset in 32-bit immediate!");
561 MI.getOperand(i + 3).ChangeToImmediate(Offset);
563 // Offset is symbolic. This is extremely rare.
564 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
565 MI.getOperand(i+3).setOffset(Offset);
569 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
570 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
571 return TFI->hasFP(MF) ? FramePtr : StackPtr;
574 unsigned X86RegisterInfo::getEHExceptionRegister() const {
575 llvm_unreachable("What is the exception register");
578 unsigned X86RegisterInfo::getEHHandlerRegister() const {
579 llvm_unreachable("What is the exception handler register");
583 unsigned getX86SubSuperRegister(unsigned Reg, MVT::SimpleValueType VT,
586 default: llvm_unreachable("Unexpected VT");
590 default: return getX86SubSuperRegister(Reg, MVT::i64, High);
591 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
593 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
595 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
597 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
602 default: llvm_unreachable("Unexpected register");
603 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
605 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
607 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
609 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
611 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
613 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
615 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
617 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
619 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
621 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
623 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
625 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
627 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
629 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
631 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
633 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
639 default: llvm_unreachable("Unexpected register");
640 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
642 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
644 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
646 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
648 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
650 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
652 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
654 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
656 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
658 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
660 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
662 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
664 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
666 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
668 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
670 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
675 default: llvm_unreachable("Unexpected register");
676 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
678 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
680 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
682 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
684 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
686 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
688 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
690 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
692 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
694 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
696 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
698 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
700 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
702 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
704 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
706 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
710 // For 64-bit mode if we've requested a "high" register and the
711 // Q or r constraints we want one of these high registers or
712 // just the register name otherwise.
715 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
717 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
719 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
721 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
727 default: llvm_unreachable("Unexpected register");
728 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
730 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
732 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
734 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
736 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
738 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
740 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
742 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
744 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
746 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
748 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
750 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
752 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
754 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
756 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
758 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
766 struct MSAH : public MachineFunctionPass {
768 MSAH() : MachineFunctionPass(ID) {}
770 virtual bool runOnMachineFunction(MachineFunction &MF) {
771 const X86TargetMachine *TM =
772 static_cast<const X86TargetMachine *>(&MF.getTarget());
773 const TargetFrameLowering *TFI = TM->getFrameLowering();
774 MachineRegisterInfo &RI = MF.getRegInfo();
775 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
776 unsigned StackAlignment = TFI->getStackAlignment();
778 // Be over-conservative: scan over all vreg defs and find whether vector
779 // registers are used. If yes, there is a possibility that vector register
780 // will be spilled and thus require dynamic stack realignment.
781 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
782 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
783 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
784 FuncInfo->setForceFramePointer(true);
792 virtual const char *getPassName() const {
793 return "X86 Maximal Stack Alignment Check";
796 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
797 AU.setPreservesCFG();
798 MachineFunctionPass::getAnalysisUsage(AU);
806 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }