1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/Target/TargetAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/Compiler.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP),
47 // Cache some information.
48 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
49 Is64Bit = Subtarget->is64Bit();
50 IsWin64 = Subtarget->isTargetWin64();
51 StackAlign = TM.getFrameInfo()->getStackAlignment();
63 // getDwarfRegNum - This function maps LLVM register identifiers to the
64 // Dwarf specific numbering, used in debug info and exception tables.
66 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
67 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
68 unsigned Flavour = DWARFFlavour::X86_64;
69 if (!Subtarget->is64Bit()) {
70 if (Subtarget->isTargetDarwin()) {
72 Flavour = DWARFFlavour::X86_32_DarwinEH;
74 Flavour = DWARFFlavour::X86_32_Generic;
75 } else if (Subtarget->isTargetCygMing()) {
76 // Unsupported by now, just quick fallback
77 Flavour = DWARFFlavour::X86_32_Generic;
79 Flavour = DWARFFlavour::X86_32_Generic;
83 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
86 // getX86RegNum - This function maps LLVM register identifiers to their X86
87 // specific numbering, which is used in various places encoding instructions.
89 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
91 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
92 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
93 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
94 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
95 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
97 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
99 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
101 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
104 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
106 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
108 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
110 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
112 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
114 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
116 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
118 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
121 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
122 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
123 return RegNo-X86::ST0;
125 case X86::XMM0: case X86::XMM8: case X86::MM0:
127 case X86::XMM1: case X86::XMM9: case X86::MM1:
129 case X86::XMM2: case X86::XMM10: case X86::MM2:
131 case X86::XMM3: case X86::XMM11: case X86::MM3:
133 case X86::XMM4: case X86::XMM12: case X86::MM4:
135 case X86::XMM5: case X86::XMM13: case X86::MM5:
137 case X86::XMM6: case X86::XMM14: case X86::MM6:
139 case X86::XMM7: case X86::XMM15: case X86::MM7:
143 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
144 assert(0 && "Register allocator hasn't allocated reg correctly yet!");
149 const TargetRegisterClass *
150 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
151 if (RC == &X86::CCRRegClass) {
153 return &X86::GR64RegClass;
155 return &X86::GR32RegClass;
161 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
162 bool callsEHReturn = false;
165 const MachineFrameInfo *MFI = MF->getFrameInfo();
166 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
167 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
170 static const unsigned CalleeSavedRegs32Bit[] = {
171 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
174 static const unsigned CalleeSavedRegs32EHRet[] = {
175 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
178 static const unsigned CalleeSavedRegs64Bit[] = {
179 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
182 static const unsigned CalleeSavedRegs64EHRet[] = {
183 X86::RAX, X86::RDX, X86::RBX, X86::R12,
184 X86::R13, X86::R14, X86::R15, X86::RBP, 0
187 static const unsigned CalleeSavedRegsWin64[] = {
188 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
189 X86::R12, X86::R13, X86::R14, X86::R15, 0
194 return CalleeSavedRegsWin64;
196 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
198 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
202 const TargetRegisterClass* const*
203 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
204 bool callsEHReturn = false;
207 const MachineFrameInfo *MFI = MF->getFrameInfo();
208 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
209 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
212 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
213 &X86::GR32RegClass, &X86::GR32RegClass,
214 &X86::GR32RegClass, &X86::GR32RegClass, 0
216 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
217 &X86::GR32RegClass, &X86::GR32RegClass,
218 &X86::GR32RegClass, &X86::GR32RegClass,
219 &X86::GR32RegClass, &X86::GR32RegClass, 0
221 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
222 &X86::GR64RegClass, &X86::GR64RegClass,
223 &X86::GR64RegClass, &X86::GR64RegClass,
224 &X86::GR64RegClass, &X86::GR64RegClass, 0
226 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
227 &X86::GR64RegClass, &X86::GR64RegClass,
228 &X86::GR64RegClass, &X86::GR64RegClass,
229 &X86::GR64RegClass, &X86::GR64RegClass,
230 &X86::GR64RegClass, &X86::GR64RegClass, 0
232 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
233 &X86::GR64RegClass, &X86::GR64RegClass,
234 &X86::GR64RegClass, &X86::GR64RegClass,
235 &X86::GR64RegClass, &X86::GR64RegClass,
236 &X86::GR64RegClass, &X86::GR64RegClass, 0
241 return CalleeSavedRegClassesWin64;
243 return (callsEHReturn ?
244 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
246 return (callsEHReturn ?
247 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
251 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
252 BitVector Reserved(getNumRegs());
253 Reserved.set(X86::RSP);
254 Reserved.set(X86::ESP);
255 Reserved.set(X86::SP);
256 Reserved.set(X86::SPL);
258 Reserved.set(X86::RBP);
259 Reserved.set(X86::EBP);
260 Reserved.set(X86::BP);
261 Reserved.set(X86::BPL);
266 //===----------------------------------------------------------------------===//
267 // Stack Frame Processing methods
268 //===----------------------------------------------------------------------===//
270 static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) {
271 unsigned MaxAlign = 0;
272 for (int i = FFI->getObjectIndexBegin(),
273 e = FFI->getObjectIndexEnd(); i != e; ++i) {
274 if (FFI->isDeadObjectIndex(i))
276 unsigned Align = FFI->getObjectAlignment(i);
277 MaxAlign = std::max(MaxAlign, Align);
283 // hasFP - Return true if the specified function should have a dedicated frame
284 // pointer register. This is true if the function has variable sized allocas or
285 // if frame pointer elimination is disabled.
287 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
288 const MachineFrameInfo *MFI = MF.getFrameInfo();
289 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
291 return (NoFramePointerElim ||
292 needsStackRealignment(MF) ||
293 MFI->hasVarSizedObjects() ||
294 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
295 (MMI && MMI->callsUnwindInit()));
298 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
299 const MachineFrameInfo *MFI = MF.getFrameInfo();;
301 // FIXME: Currently we don't support stack realignment for functions with
302 // variable-sized allocas
303 return (RealignStack &&
304 (MFI->getMaxAlignment() > StackAlign &&
305 !MFI->hasVarSizedObjects()));
308 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
309 return !MF.getFrameInfo()->hasVarSizedObjects();
313 X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
314 int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize;
315 uint64_t StackSize = MF.getFrameInfo()->getStackSize();
317 if (needsStackRealignment(MF)) {
319 // Skip the saved EBP
322 unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI);
323 assert( (-(Offset + StackSize)) % Align == 0);
324 return Offset + StackSize;
327 // FIXME: Support tail calls
330 return Offset + StackSize;
332 // Skip the saved EBP
335 // Skip the RETADDR move area
336 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
337 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
338 if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta;
344 void X86RegisterInfo::
345 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
346 MachineBasicBlock::iterator I) const {
347 if (!hasReservedCallFrame(MF)) {
348 // If the stack pointer can be changed after prologue, turn the
349 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
350 // adjcallstackdown instruction into 'add ESP, <amt>'
351 // TODO: consider using push / pop instead of sub + store / add
352 MachineInstr *Old = I;
353 uint64_t Amount = Old->getOperand(0).getImm();
355 // We need to keep the stack aligned properly. To do this, we round the
356 // amount of space needed for the outgoing arguments up to the next
357 // alignment boundary.
358 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
360 MachineInstr *New = 0;
361 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
362 New = BuildMI(MF, TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
363 StackPtr).addReg(StackPtr).addImm(Amount);
365 assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
366 // factor out the amount the callee already popped.
367 uint64_t CalleeAmt = Old->getOperand(1).getImm();
370 unsigned Opc = (Amount < 128) ?
371 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
372 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
373 New = BuildMI(MF, TII.get(Opc), StackPtr)
374 .addReg(StackPtr).addImm(Amount);
378 // Replace the pseudo instruction with a new instruction...
379 if (New) MBB.insert(I, New);
381 } else if (I->getOpcode() == X86::ADJCALLSTACKUP) {
382 // If we are performing frame pointer elimination and if the callee pops
383 // something off the stack pointer, add it back. We do this until we have
384 // more advanced stack pointer tracking ability.
385 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
386 unsigned Opc = (CalleeAmt < 128) ?
387 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
388 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
390 BuildMI(MF, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt);
398 void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
399 int SPAdj, RegScavenger *RS) const{
400 assert(SPAdj == 0 && "Unexpected");
403 MachineInstr &MI = *II;
404 MachineFunction &MF = *MI.getParent()->getParent();
405 while (!MI.getOperand(i).isFrameIndex()) {
407 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
410 int FrameIndex = MI.getOperand(i).getIndex();
413 if (needsStackRealignment(MF))
414 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
416 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
418 // This must be part of a four operand memory reference. Replace the
419 // FrameIndex with base register with EBP. Add an offset to the offset.
420 MI.getOperand(i).ChangeToRegister(BasePtr, false);
422 // Now add the frame object offset to the offset from EBP.
423 int64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
424 MI.getOperand(i+3).getImm();
426 MI.getOperand(i+3).ChangeToImmediate(Offset);
430 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
431 RegScavenger *RS) const {
432 MachineFrameInfo *FFI = MF.getFrameInfo();
434 // Calculate and set max stack object alignment early, so we can decide
435 // whether we will need stack realignment (and thus FP).
436 unsigned MaxAlign = std::max(FFI->getMaxAlignment(),
437 calculateMaxStackAlignment(FFI));
439 FFI->setMaxAlignment(MaxAlign);
443 X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{
444 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
445 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
446 if (TailCallReturnAddrDelta < 0) {
447 // create RETURNADDR area
457 CreateFixedObject(-TailCallReturnAddrDelta,
458 (-1*SlotSize)+TailCallReturnAddrDelta);
461 assert((TailCallReturnAddrDelta <= 0) &&
462 "The Delta should always be zero or negative");
463 // Create a frame entry for the EBP register that must be saved.
464 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize,
466 TailCallReturnAddrDelta);
467 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() &&
468 "Slot for EBP register must be last in order to be found!");
472 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
473 /// stack pointer by a constant value.
475 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
476 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
477 const TargetInstrInfo &TII) {
478 bool isSub = NumBytes < 0;
479 uint64_t Offset = isSub ? -NumBytes : NumBytes;
482 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
483 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
485 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
486 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
487 uint64_t Chunk = (1LL << 31) - 1;
490 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
491 BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal);
496 // mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
498 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
499 unsigned StackPtr, uint64_t *NumBytes = NULL) {
500 if (MBBI == MBB.begin()) return;
502 MachineBasicBlock::iterator PI = prior(MBBI);
503 unsigned Opc = PI->getOpcode();
504 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
505 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
506 PI->getOperand(0).getReg() == StackPtr) {
508 *NumBytes += PI->getOperand(2).getImm();
510 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
511 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
512 PI->getOperand(0).getReg() == StackPtr) {
514 *NumBytes -= PI->getOperand(2).getImm();
519 // mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
521 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
522 MachineBasicBlock::iterator &MBBI,
523 unsigned StackPtr, uint64_t *NumBytes = NULL) {
526 if (MBBI == MBB.end()) return;
528 MachineBasicBlock::iterator NI = next(MBBI);
529 if (NI == MBB.end()) return;
531 unsigned Opc = NI->getOpcode();
532 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
533 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
534 NI->getOperand(0).getReg() == StackPtr) {
536 *NumBytes -= NI->getOperand(2).getImm();
539 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
540 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
541 NI->getOperand(0).getReg() == StackPtr) {
543 *NumBytes += NI->getOperand(2).getImm();
549 /// mergeSPUpdates - Checks the instruction before/after the passed
550 /// instruction. If it is an ADD/SUB instruction it is deleted
551 /// argument and the stack adjustment is returned as a positive value for ADD
552 /// and a negative for SUB.
553 static int mergeSPUpdates(MachineBasicBlock &MBB,
554 MachineBasicBlock::iterator &MBBI,
556 bool doMergeWithPrevious) {
558 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
559 (!doMergeWithPrevious && MBBI == MBB.end()))
564 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
565 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : next(MBBI);
566 unsigned Opc = PI->getOpcode();
567 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
568 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
569 PI->getOperand(0).getReg() == StackPtr){
570 Offset += PI->getOperand(2).getImm();
572 if (!doMergeWithPrevious) MBBI = NI;
573 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
574 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
575 PI->getOperand(0).getReg() == StackPtr) {
576 Offset -= PI->getOperand(2).getImm();
578 if (!doMergeWithPrevious) MBBI = NI;
584 void X86RegisterInfo::emitFrameMoves(MachineFunction &MF,
585 unsigned FrameLabelId,
586 unsigned ReadyLabelId) const {
587 MachineFrameInfo *MFI = MF.getFrameInfo();
588 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
592 uint64_t StackSize = MFI->getStackSize();
593 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
594 const TargetData *TD = MF.getTarget().getTargetData();
596 // Calculate amount of bytes used for return address storing
598 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
599 TargetFrameInfo::StackGrowsUp ?
600 TD->getPointerSize() : -TD->getPointerSize());
603 // Show update of SP.
606 MachineLocation SPDst(MachineLocation::VirtualFP);
607 MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth);
608 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
610 MachineLocation SPDst(MachineLocation::VirtualFP);
611 MachineLocation SPSrc(MachineLocation::VirtualFP,
612 -StackSize+stackGrowth);
613 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
616 //FIXME: Verify & implement for FP
617 MachineLocation SPDst(StackPtr);
618 MachineLocation SPSrc(StackPtr, stackGrowth);
619 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
622 // Add callee saved registers to move list.
623 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
625 // FIXME: This is dirty hack. The code itself is pretty mess right now.
626 // It should be rewritten from scratch and generalized sometimes.
628 // Determine maximum offset (minumum due to stack growth)
629 int64_t MaxOffset = 0;
630 for (unsigned I = 0, E = CSI.size(); I!=E; ++I)
631 MaxOffset = std::min(MaxOffset,
632 MFI->getObjectOffset(CSI[I].getFrameIdx()));
635 int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth;
636 for (unsigned I = 0, E = CSI.size(); I!=E; ++I) {
637 int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
638 unsigned Reg = CSI[I].getReg();
639 Offset = (MaxOffset-Offset+saveAreaOffset);
640 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
641 MachineLocation CSSrc(Reg);
642 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
647 MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth);
648 MachineLocation FPSrc(FramePtr);
649 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
652 MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr);
653 MachineLocation FPSrc(MachineLocation::VirtualFP);
654 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
658 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
659 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
660 MachineFrameInfo *MFI = MF.getFrameInfo();
661 const Function* Fn = MF.getFunction();
662 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
663 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
664 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
665 MachineBasicBlock::iterator MBBI = MBB.begin();
666 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
667 !Fn->doesNotThrow() ||
668 UnwindTablesMandatory;
669 // Prepare for frame info.
670 unsigned FrameLabelId = 0;
672 // Get the number of bytes to allocate from the FrameInfo.
673 uint64_t StackSize = MFI->getStackSize();
674 // Get desired stack alignment
675 uint64_t MaxAlign = MFI->getMaxAlignment();
677 // Add RETADDR move area to callee saved frame size.
678 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
679 if (TailCallReturnAddrDelta < 0)
680 X86FI->setCalleeSavedFrameSize(
681 X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta));
683 // Insert stack pointer adjustment for later moving of return addr. Only
684 // applies to tail call optimized functions where the callee argument stack
685 // size is bigger than the callers.
686 if (TailCallReturnAddrDelta < 0) {
687 BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
688 StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta);
691 uint64_t NumBytes = 0;
693 // Calculate required stack adjustment
694 uint64_t FrameSize = StackSize - SlotSize;
695 if (needsStackRealignment(MF))
696 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
698 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
700 // Get the offset of the stack slot for the EBP register... which is
701 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
702 // Update the frame offset adjustment.
703 MFI->setOffsetAdjustment(-NumBytes);
705 // Save EBP into the appropriate stack slot...
706 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
709 if (needsFrameMoves) {
710 // Mark effective beginning of when frame pointer becomes valid.
711 FrameLabelId = MMI->NextLabelID();
712 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
715 // Update EBP with the new base value...
716 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
720 if (needsStackRealignment(MF))
722 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
723 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
725 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
727 unsigned ReadyLabelId = 0;
728 if (needsFrameMoves) {
729 // Mark effective beginning of when frame pointer is ready.
730 ReadyLabelId = MMI->NextLabelID();
731 BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
734 // Skip the callee-saved push instructions.
735 while (MBBI != MBB.end() &&
736 (MBBI->getOpcode() == X86::PUSH32r ||
737 MBBI->getOpcode() == X86::PUSH64r))
740 if (NumBytes) { // adjust stack pointer: ESP -= numbytes
741 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
742 // Check, whether EAX is livein for this function
743 bool isEAXAlive = false;
744 for (MachineRegisterInfo::livein_iterator
745 II = MF.getRegInfo().livein_begin(),
746 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
747 unsigned Reg = II->first;
748 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
749 Reg == X86::AH || Reg == X86::AL);
752 // Function prologue calls _alloca to probe the stack when allocating
753 // more than 4k bytes in one go. Touching the stack at 4K increments is
754 // necessary to ensure that the guard pages used by the OS virtual memory
755 // manager are allocated in correct sequence.
757 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes);
758 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
759 .addExternalSymbol("_alloca");
762 BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX);
763 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
764 // allocated bytes for EAX.
765 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4);
766 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32))
767 .addExternalSymbol("_alloca");
769 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(X86::MOV32rm),X86::EAX),
770 StackPtr, false, NumBytes-4);
771 MBB.insert(MBBI, MI);
774 // If there is an SUB32ri of ESP immediately before this instruction,
775 // merge the two. This can be the case when tail call elimination is
776 // enabled and the callee has more arguments then the caller.
777 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
778 // If there is an ADD32ri or SUB32ri of ESP immediately after this
779 // instruction, merge the two instructions.
780 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
783 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
788 emitFrameMoves(MF, FrameLabelId, ReadyLabelId);
791 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
792 MachineBasicBlock &MBB) const {
793 const MachineFrameInfo *MFI = MF.getFrameInfo();
794 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
795 MachineBasicBlock::iterator MBBI = prior(MBB.end());
796 unsigned RetOpcode = MBBI->getOpcode();
801 case X86::TCRETURNdi:
802 case X86::TCRETURNri:
803 case X86::TCRETURNri64:
804 case X86::TCRETURNdi64:
806 case X86::EH_RETURN64:
809 case X86::TAILJMPm: break; // These are ok
811 assert(0 && "Can only insert epilog into returning blocks");
814 // Get the number of bytes to allocate from the FrameInfo
815 uint64_t StackSize = MFI->getStackSize();
816 uint64_t MaxAlign = MFI->getMaxAlignment();
817 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
818 uint64_t NumBytes = 0;
821 // Calculate required stack adjustment
822 uint64_t FrameSize = StackSize - SlotSize;
823 if (needsStackRealignment(MF))
824 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
826 NumBytes = FrameSize - CSSize;
829 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
831 NumBytes = StackSize - CSSize;
833 // Skip the callee-saved pop instructions.
834 MachineBasicBlock::iterator LastCSPop = MBBI;
835 while (MBBI != MBB.begin()) {
836 MachineBasicBlock::iterator PI = prior(MBBI);
837 unsigned Opc = PI->getOpcode();
838 if (Opc != X86::POP32r && Opc != X86::POP64r &&
839 !PI->getDesc().isTerminator())
844 // If there is an ADD32ri or SUB32ri of ESP immediately before this
845 // instruction, merge the two instructions.
846 if (NumBytes || MFI->hasVarSizedObjects())
847 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
849 // If dynamic alloca is used, then reset esp to point to the last callee-saved
850 // slot before popping them off! Same applies for the case, when stack was
852 if (needsStackRealignment(MF)) {
853 // We cannot use LEA here, because stack pointer was realigned. We need to
854 // deallocate local frame back
856 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
857 MBBI = prior(LastCSPop);
861 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
862 StackPtr).addReg(FramePtr);
863 } else if (MFI->hasVarSizedObjects()) {
865 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
866 MachineInstr *MI = addRegOffset(BuildMI(MF, TII.get(Opc), StackPtr),
867 FramePtr, false, -CSSize);
868 MBB.insert(MBBI, MI);
870 BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
871 StackPtr).addReg(FramePtr);
874 // adjust stack pointer back: ESP += numbytes
876 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
879 // We're returning from function via eh_return.
880 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
881 MBBI = prior(MBB.end());
882 MachineOperand &DestAddr = MBBI->getOperand(0);
883 assert(DestAddr.isRegister() && "Offset should be in register!");
885 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
886 StackPtr).addReg(DestAddr.getReg());
887 // Tail call return: adjust the stack pointer and jump to callee
888 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
889 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
890 MBBI = prior(MBB.end());
891 MachineOperand &JumpTarget = MBBI->getOperand(0);
892 MachineOperand &StackAdjust = MBBI->getOperand(1);
893 assert( StackAdjust.isImmediate() && "Expecting immediate value.");
895 // Adjust stack pointer.
896 int StackAdj = StackAdjust.getImm();
897 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
899 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
900 // Incoporate the retaddr area.
901 Offset = StackAdj-MaxTCDelta;
902 assert(Offset >= 0 && "Offset should never be negative");
904 // Check for possible merge with preceeding ADD instruction.
905 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
906 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
908 // Jump to label or value in register.
909 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64)
910 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)).
911 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
912 else if (RetOpcode== X86::TCRETURNri64) {
913 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
915 BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg());
916 // Delete the pseudo instruction TCRETURN.
918 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
919 (X86FI->getTCReturnAddrDelta() < 0)) {
920 // Add the return addr area delta back since we are not tail calling.
921 int delta = -1*X86FI->getTCReturnAddrDelta();
922 MBBI = prior(MBB.end());
923 // Check for possible merge with preceeding ADD instruction.
924 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
925 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
929 unsigned X86RegisterInfo::getRARegister() const {
931 return X86::RIP; // Should have dwarf #16
933 return X86::EIP; // Should have dwarf #8
936 unsigned X86RegisterInfo::getFrameRegister(MachineFunction &MF) const {
937 return hasFP(MF) ? FramePtr : StackPtr;
940 void X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
942 // Calculate amount of bytes used for return address storing
943 int stackGrowth = (Is64Bit ? -8 : -4);
945 // Initial state of the frame pointer is esp+4.
946 MachineLocation Dst(MachineLocation::VirtualFP);
947 MachineLocation Src(StackPtr, stackGrowth);
948 Moves.push_back(MachineMove(0, Dst, Src));
950 // Add return address to move list
951 MachineLocation CSDst(StackPtr, stackGrowth);
952 MachineLocation CSSrc(getRARegister());
953 Moves.push_back(MachineMove(0, CSDst, CSSrc));
956 unsigned X86RegisterInfo::getEHExceptionRegister() const {
957 assert(0 && "What is the exception register");
961 unsigned X86RegisterInfo::getEHHandlerRegister() const {
962 assert(0 && "What is the exception handler register");
967 unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) {
968 switch (VT.getSimpleVT()) {
974 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
976 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
978 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
980 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
986 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
988 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
990 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
992 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
994 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
996 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
998 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1000 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1002 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1004 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1006 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1008 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1010 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1012 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1014 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1016 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1022 default: return Reg;
1023 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1025 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1027 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1029 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1031 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1033 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1035 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1037 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1039 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1041 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1043 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1045 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1047 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1049 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1051 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1053 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1058 default: return Reg;
1059 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1061 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1063 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1065 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1067 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1069 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1071 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1073 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1075 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1077 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1079 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1081 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1083 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1085 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1087 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1089 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1094 default: return Reg;
1095 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1097 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1099 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1101 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1103 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1105 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1107 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1109 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1111 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1113 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1115 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1117 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1119 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1121 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1123 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1125 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1134 #include "X86GenRegisterInfo.inc"
1137 struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass {
1139 MSAC() : MachineFunctionPass(&ID) {}
1141 virtual bool runOnMachineFunction(MachineFunction &MF) {
1142 MachineFrameInfo *FFI = MF.getFrameInfo();
1143 MachineRegisterInfo &RI = MF.getRegInfo();
1145 // Calculate max stack alignment of all already allocated stack objects.
1146 unsigned MaxAlign = calculateMaxStackAlignment(FFI);
1148 // Be over-conservative: scan over all vreg defs and find, whether vector
1149 // registers are used. If yes - there is probability, that vector register
1150 // will be spilled and thus stack needs to be aligned properly.
1151 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1152 RegNum < RI.getLastVirtReg(); ++RegNum)
1153 MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment());
1155 FFI->setMaxAlignment(MaxAlign);
1160 virtual const char *getPassName() const {
1161 return "X86 Maximal Stack Alignment Calculator";
1169 llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }