1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/CommandLine.h"
43 #define GET_REGINFO_MC_DESC
44 #define GET_REGINFO_TARGET_DESC
45 #include "X86GenRegisterInfo.inc"
50 ForceStackAlign("force-align-stack",
51 cl::desc("Force align the stack to the minimum alignment"
52 " needed for the function."),
53 cl::init(false), cl::Hidden);
55 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
56 const TargetInstrInfo &tii)
57 : X86GenRegisterInfo(), TM(tm), TII(tii) {
58 // Cache some information.
59 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
60 Is64Bit = Subtarget->is64Bit();
61 IsWin64 = Subtarget->isTargetWin64();
74 static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 return DWARFFlavour::X86_32_DarwinEH;
80 return DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 return DWARFFlavour::X86_32_Generic;
85 return DWARFFlavour::X86_32_Generic;
88 return DWARFFlavour::X86_64;
91 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
92 /// specific numbering, used in debug info and exception tables.
93 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
94 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
95 unsigned Flavour = getFlavour(Subtarget, isEH);
97 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
100 /// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
101 int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
102 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
103 unsigned Flavour = getFlavour(Subtarget, isEH);
105 return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
108 /// getCompactUnwindRegNum - This function maps the register to the number for
109 /// compact unwind encoding. Return -1 if the register isn't valid.
110 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum) const {
112 case X86::EBX: case X86::RBX: return 1;
113 case X86::ECX: case X86::RCX: return 2;
114 case X86::EDX: case X86::RDX: return 3;
115 case X86::EDI: case X86::RDI: return 4;
116 case X86::ESI: case X86::RSI: return 5;
117 case X86::EBP: case X86::RBP: return 6;
124 X86RegisterInfo::getSEHRegNum(unsigned i) const {
125 int reg = getX86RegNum(i);
127 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
128 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
129 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
130 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
131 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
132 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
133 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
134 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
135 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11:
136 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
137 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11:
138 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15:
144 /// getX86RegNum - This function maps LLVM register identifiers to their X86
145 /// specific numbering, which is used in various places encoding instructions.
146 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
148 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
149 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
150 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
151 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
152 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
154 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
156 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
158 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
161 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
163 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
165 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
167 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
169 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
171 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
173 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
175 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
178 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
179 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
180 return RegNo-X86::ST0;
182 case X86::XMM0: case X86::XMM8:
183 case X86::YMM0: case X86::YMM8: case X86::MM0:
185 case X86::XMM1: case X86::XMM9:
186 case X86::YMM1: case X86::YMM9: case X86::MM1:
188 case X86::XMM2: case X86::XMM10:
189 case X86::YMM2: case X86::YMM10: case X86::MM2:
191 case X86::XMM3: case X86::XMM11:
192 case X86::YMM3: case X86::YMM11: case X86::MM3:
194 case X86::XMM4: case X86::XMM12:
195 case X86::YMM4: case X86::YMM12: case X86::MM4:
197 case X86::XMM5: case X86::XMM13:
198 case X86::YMM5: case X86::YMM13: case X86::MM5:
200 case X86::XMM6: case X86::XMM14:
201 case X86::YMM6: case X86::YMM14: case X86::MM6:
203 case X86::XMM7: case X86::XMM15:
204 case X86::YMM7: case X86::YMM15: case X86::MM7:
207 case X86::ES: return 0;
208 case X86::CS: return 1;
209 case X86::SS: return 2;
210 case X86::DS: return 3;
211 case X86::FS: return 4;
212 case X86::GS: return 5;
214 case X86::CR0: case X86::CR8 : case X86::DR0: return 0;
215 case X86::CR1: case X86::CR9 : case X86::DR1: return 1;
216 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
217 case X86::CR3: case X86::CR11: case X86::DR3: return 3;
218 case X86::CR4: case X86::CR12: case X86::DR4: return 4;
219 case X86::CR5: case X86::CR13: case X86::DR5: return 5;
220 case X86::CR6: case X86::CR14: case X86::DR6: return 6;
221 case X86::CR7: case X86::CR15: case X86::DR7: return 7;
223 // Pseudo index registers are equivalent to a "none"
224 // scaled index (See Intel Manual 2A, table 2-3)
230 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
231 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
236 const TargetRegisterClass *
237 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
238 const TargetRegisterClass *B,
239 unsigned SubIdx) const {
243 if (B == &X86::GR8RegClass) {
244 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
246 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
247 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
248 A == &X86::GR64_NOREXRegClass ||
249 A == &X86::GR64_NOSPRegClass ||
250 A == &X86::GR64_NOREX_NOSPRegClass)
251 return &X86::GR64_ABCDRegClass;
252 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
253 A == &X86::GR32_NOREXRegClass ||
254 A == &X86::GR32_NOSPRegClass)
255 return &X86::GR32_ABCDRegClass;
256 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
257 A == &X86::GR16_NOREXRegClass)
258 return &X86::GR16_ABCDRegClass;
259 } else if (B == &X86::GR8_NOREXRegClass) {
260 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
261 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
262 return &X86::GR64_NOREXRegClass;
263 else if (A == &X86::GR64_ABCDRegClass)
264 return &X86::GR64_ABCDRegClass;
265 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
266 A == &X86::GR32_NOSPRegClass)
267 return &X86::GR32_NOREXRegClass;
268 else if (A == &X86::GR32_ABCDRegClass)
269 return &X86::GR32_ABCDRegClass;
270 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
271 return &X86::GR16_NOREXRegClass;
272 else if (A == &X86::GR16_ABCDRegClass)
273 return &X86::GR16_ABCDRegClass;
276 case X86::sub_8bit_hi:
277 if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass))
278 switch (A->getSize()) {
279 case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass);
280 case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass);
281 case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass);
286 if (B == &X86::GR16RegClass) {
287 if (A->getSize() == 4 || A->getSize() == 8)
289 } else if (B == &X86::GR16_ABCDRegClass) {
290 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
291 A == &X86::GR64_NOREXRegClass ||
292 A == &X86::GR64_NOSPRegClass ||
293 A == &X86::GR64_NOREX_NOSPRegClass)
294 return &X86::GR64_ABCDRegClass;
295 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
296 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
297 return &X86::GR32_ABCDRegClass;
298 } else if (B == &X86::GR16_NOREXRegClass) {
299 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
300 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
301 return &X86::GR64_NOREXRegClass;
302 else if (A == &X86::GR64_ABCDRegClass)
303 return &X86::GR64_ABCDRegClass;
304 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
305 A == &X86::GR32_NOSPRegClass)
306 return &X86::GR32_NOREXRegClass;
307 else if (A == &X86::GR32_ABCDRegClass)
308 return &X86::GR64_ABCDRegClass;
312 if (B == &X86::GR32RegClass) {
313 if (A->getSize() == 8)
315 } else if (B == &X86::GR32_NOSPRegClass) {
316 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass)
317 return &X86::GR64_NOSPRegClass;
318 if (A->getSize() == 8)
319 return getCommonSubClass(A, &X86::GR64_NOSPRegClass);
320 } else if (B == &X86::GR32_ABCDRegClass) {
321 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
322 A == &X86::GR64_NOREXRegClass ||
323 A == &X86::GR64_NOSPRegClass ||
324 A == &X86::GR64_NOREX_NOSPRegClass)
325 return &X86::GR64_ABCDRegClass;
326 } else if (B == &X86::GR32_NOREXRegClass) {
327 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass)
328 return &X86::GR64_NOREXRegClass;
329 else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
330 return &X86::GR64_NOREX_NOSPRegClass;
331 else if (A == &X86::GR64_ABCDRegClass)
332 return &X86::GR64_ABCDRegClass;
333 } else if (B == &X86::GR32_NOREX_NOSPRegClass) {
334 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
335 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
336 return &X86::GR64_NOREX_NOSPRegClass;
337 else if (A == &X86::GR64_ABCDRegClass)
338 return &X86::GR64_ABCDRegClass;
342 if (B == &X86::FR32RegClass)
346 if (B == &X86::FR64RegClass)
350 if (B == &X86::VR128RegClass)
357 const TargetRegisterClass*
358 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
359 const TargetRegisterClass *Super = RC;
360 TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
362 switch (Super->getID()) {
363 case X86::GR8RegClassID:
364 case X86::GR16RegClassID:
365 case X86::GR32RegClassID:
366 case X86::GR64RegClassID:
367 case X86::FR32RegClassID:
368 case X86::FR64RegClassID:
369 case X86::RFP32RegClassID:
370 case X86::RFP64RegClassID:
371 case X86::RFP80RegClassID:
372 case X86::VR128RegClassID:
373 case X86::VR256RegClassID:
374 // Don't return a super-class that would shrink the spill size.
375 // That can happen with the vector and float classes.
376 if (Super->getSize() == RC->getSize())
384 const TargetRegisterClass *
385 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
387 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
388 case 0: // Normal GPRs.
389 if (TM.getSubtarget<X86Subtarget>().is64Bit())
390 return &X86::GR64RegClass;
391 return &X86::GR32RegClass;
392 case 1: // Normal GPRs except the stack pointer (for encoding reasons).
393 if (TM.getSubtarget<X86Subtarget>().is64Bit())
394 return &X86::GR64_NOSPRegClass;
395 return &X86::GR32_NOSPRegClass;
396 case 2: // Available for tailcall (not callee-saved GPRs).
397 if (TM.getSubtarget<X86Subtarget>().isTargetWin64())
398 return &X86::GR64_TCW64RegClass;
399 if (TM.getSubtarget<X86Subtarget>().is64Bit())
400 return &X86::GR64_TCRegClass;
401 return &X86::GR32_TCRegClass;
405 const TargetRegisterClass *
406 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
407 if (RC == &X86::CCRRegClass) {
409 return &X86::GR64RegClass;
411 return &X86::GR32RegClass;
417 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
418 MachineFunction &MF) const {
419 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
421 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
422 switch (RC->getID()) {
425 case X86::GR32RegClassID:
427 case X86::GR64RegClassID:
429 case X86::VR128RegClassID:
430 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4;
431 case X86::VR64RegClassID:
437 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
438 bool callsEHReturn = false;
439 bool ghcCall = false;
442 callsEHReturn = MF->getMMI().callsEHReturn();
443 const Function *F = MF->getFunction();
444 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
447 static const unsigned GhcCalleeSavedRegs[] = {
451 static const unsigned CalleeSavedRegs32Bit[] = {
452 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
455 static const unsigned CalleeSavedRegs32EHRet[] = {
456 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
459 static const unsigned CalleeSavedRegs64Bit[] = {
460 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
463 static const unsigned CalleeSavedRegs64EHRet[] = {
464 X86::RAX, X86::RDX, X86::RBX, X86::R12,
465 X86::R13, X86::R14, X86::R15, X86::RBP, 0
468 static const unsigned CalleeSavedRegsWin64[] = {
469 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
470 X86::R12, X86::R13, X86::R14, X86::R15,
471 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
472 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
473 X86::XMM14, X86::XMM15, 0
477 return GhcCalleeSavedRegs;
478 } else if (Is64Bit) {
480 return CalleeSavedRegsWin64;
482 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
484 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
488 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
489 BitVector Reserved(getNumRegs());
490 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
492 // Set the stack-pointer register and its aliases as reserved.
493 Reserved.set(X86::RSP);
494 Reserved.set(X86::ESP);
495 Reserved.set(X86::SP);
496 Reserved.set(X86::SPL);
498 // Set the instruction pointer register and its aliases as reserved.
499 Reserved.set(X86::RIP);
500 Reserved.set(X86::EIP);
501 Reserved.set(X86::IP);
503 // Set the frame-pointer register and its aliases as reserved if needed.
504 if (TFI->hasFP(MF)) {
505 Reserved.set(X86::RBP);
506 Reserved.set(X86::EBP);
507 Reserved.set(X86::BP);
508 Reserved.set(X86::BPL);
511 // Mark the segment registers as reserved.
512 Reserved.set(X86::CS);
513 Reserved.set(X86::SS);
514 Reserved.set(X86::DS);
515 Reserved.set(X86::ES);
516 Reserved.set(X86::FS);
517 Reserved.set(X86::GS);
519 // Reserve the registers that only exist in 64-bit mode.
521 // These 8-bit registers are part of the x86-64 extension even though their
522 // super-registers are old 32-bits.
523 Reserved.set(X86::SIL);
524 Reserved.set(X86::DIL);
525 Reserved.set(X86::BPL);
526 Reserved.set(X86::SPL);
528 for (unsigned n = 0; n != 8; ++n) {
530 const unsigned GPR64[] = {
531 X86::R8, X86::R9, X86::R10, X86::R11,
532 X86::R12, X86::R13, X86::R14, X86::R15
534 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
538 assert(X86::XMM15 == X86::XMM8+7);
539 for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI;
548 //===----------------------------------------------------------------------===//
549 // Stack Frame Processing methods
550 //===----------------------------------------------------------------------===//
552 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
553 const MachineFrameInfo *MFI = MF.getFrameInfo();
554 return (RealignStack &&
555 !MFI->hasVarSizedObjects());
558 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
559 const MachineFrameInfo *MFI = MF.getFrameInfo();
560 const Function *F = MF.getFunction();
561 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
562 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
563 F->hasFnAttr(Attribute::StackAlignment));
565 // FIXME: Currently we don't support stack realignment for functions with
566 // variable-sized allocas.
567 // FIXME: It's more complicated than this...
568 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
570 "Stack realignment in presence of dynamic allocas is not supported");
572 // If we've requested that we force align the stack do so now.
574 return canRealignStack(MF);
576 return requiresRealignment && canRealignStack(MF);
579 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
580 unsigned Reg, int &FrameIdx) const {
581 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
583 if (Reg == FramePtr && TFI->hasFP(MF)) {
584 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
590 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
593 return X86::SUB64ri8;
594 return X86::SUB64ri32;
597 return X86::SUB32ri8;
602 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
605 return X86::ADD64ri8;
606 return X86::ADD64ri32;
609 return X86::ADD32ri8;
614 void X86RegisterInfo::
615 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
616 MachineBasicBlock::iterator I) const {
617 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
618 bool reseveCallFrame = TFI->hasReservedCallFrame(MF);
619 int Opcode = I->getOpcode();
620 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
621 DebugLoc DL = I->getDebugLoc();
622 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
623 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
626 if (!reseveCallFrame) {
627 // If the stack pointer can be changed after prologue, turn the
628 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
629 // adjcallstackdown instruction into 'add ESP, <amt>'
630 // TODO: consider using push / pop instead of sub + store / add
634 // We need to keep the stack aligned properly. To do this, we round the
635 // amount of space needed for the outgoing arguments up to the next
636 // alignment boundary.
637 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
638 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
640 MachineInstr *New = 0;
641 if (Opcode == TII.getCallFrameSetupOpcode()) {
642 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)),
647 assert(Opcode == TII.getCallFrameDestroyOpcode());
649 // Factor out the amount the callee already popped.
653 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
654 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
655 .addReg(StackPtr).addImm(Amount);
660 // The EFLAGS implicit def is dead.
661 New->getOperand(3).setIsDead();
663 // Replace the pseudo instruction with a new instruction.
670 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
671 // If we are performing frame pointer elimination and if the callee pops
672 // something off the stack pointer, add it back. We do this until we have
673 // more advanced stack pointer tracking ability.
674 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
675 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
676 .addReg(StackPtr).addImm(CalleeAmt);
678 // The EFLAGS implicit def is dead.
679 New->getOperand(3).setIsDead();
681 // We are not tracking the stack pointer adjustment by the callee, so make
682 // sure we restore the stack pointer immediately after the call, there may
683 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
684 MachineBasicBlock::iterator B = MBB.begin();
685 while (I != B && !llvm::prior(I)->getDesc().isCall())
692 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
693 int SPAdj, RegScavenger *RS) const{
694 assert(SPAdj == 0 && "Unexpected");
697 MachineInstr &MI = *II;
698 MachineFunction &MF = *MI.getParent()->getParent();
699 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
701 while (!MI.getOperand(i).isFI()) {
703 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
706 int FrameIndex = MI.getOperand(i).getIndex();
709 unsigned Opc = MI.getOpcode();
710 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
711 if (needsStackRealignment(MF))
712 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
716 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr);
718 // This must be part of a four operand memory reference. Replace the
719 // FrameIndex with base register with EBP. Add an offset to the offset.
720 MI.getOperand(i).ChangeToRegister(BasePtr, false);
722 // Now add the frame object offset to the offset from EBP.
725 // Tail call jmp happens after FP is popped.
726 const MachineFrameInfo *MFI = MF.getFrameInfo();
727 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea();
729 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex);
731 if (MI.getOperand(i+3).isImm()) {
732 // Offset is a 32-bit integer.
733 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
734 MI.getOperand(i + 3).ChangeToImmediate(Offset);
736 // Offset is symbolic. This is extremely rare.
737 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
738 MI.getOperand(i+3).setOffset(Offset);
742 unsigned X86RegisterInfo::getRARegister() const {
743 return Is64Bit ? X86::RIP // Should have dwarf #16.
744 : X86::EIP; // Should have dwarf #8.
747 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
748 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
749 return TFI->hasFP(MF) ? FramePtr : StackPtr;
752 unsigned X86RegisterInfo::getEHExceptionRegister() const {
753 llvm_unreachable("What is the exception register");
757 unsigned X86RegisterInfo::getEHHandlerRegister() const {
758 llvm_unreachable("What is the exception handler register");
763 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
764 switch (VT.getSimpleVT().SimpleTy) {
770 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
772 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
774 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
776 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
782 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
784 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
786 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
788 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
790 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
792 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
794 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
796 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
798 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
800 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
802 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
804 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
806 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
808 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
810 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
812 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
819 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
821 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
823 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
825 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
827 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
829 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
831 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
833 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
835 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
837 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
839 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
841 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
843 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
845 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
847 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
849 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
855 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
857 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
859 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
861 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
863 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
865 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
867 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
869 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
871 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
873 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
875 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
877 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
879 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
881 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
883 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
885 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
891 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
893 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
895 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
897 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
899 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
901 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
903 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
905 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
907 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
909 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
911 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
913 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
915 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
917 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
919 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
921 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
931 struct MSAH : public MachineFunctionPass {
933 MSAH() : MachineFunctionPass(ID) {}
935 virtual bool runOnMachineFunction(MachineFunction &MF) {
936 const X86TargetMachine *TM =
937 static_cast<const X86TargetMachine *>(&MF.getTarget());
938 const TargetFrameLowering *TFI = TM->getFrameLowering();
939 MachineRegisterInfo &RI = MF.getRegInfo();
940 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
941 unsigned StackAlignment = TFI->getStackAlignment();
943 // Be over-conservative: scan over all vreg defs and find whether vector
944 // registers are used. If yes, there is a possibility that vector register
945 // will be spilled and thus require dynamic stack realignment.
946 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) {
947 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
948 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) {
949 FuncInfo->setReserveFP(true);
957 virtual const char *getPassName() const {
958 return "X86 Maximal Stack Alignment Check";
961 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
962 AU.setPreservesCFG();
963 MachineFunctionPass::getAnalysisUsage(AU);
971 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }