1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/ErrorHandling.h"
44 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
45 const TargetInstrInfo &tii)
46 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
47 X86::ADJCALLSTACKDOWN64 :
48 X86::ADJCALLSTACKDOWN32,
49 tm.getSubtarget<X86Subtarget>().is64Bit() ?
50 X86::ADJCALLSTACKUP64 :
51 X86::ADJCALLSTACKUP32),
53 // Cache some information.
54 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
55 Is64Bit = Subtarget->is64Bit();
56 IsWin64 = Subtarget->isTargetWin64();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
70 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
71 /// specific numbering, used in debug info and exception tables.
72 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
73 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
74 unsigned Flavour = DWARFFlavour::X86_64;
76 if (!Subtarget->is64Bit()) {
77 if (Subtarget->isTargetDarwin()) {
79 Flavour = DWARFFlavour::X86_32_DarwinEH;
81 Flavour = DWARFFlavour::X86_32_Generic;
82 } else if (Subtarget->isTargetCygMing()) {
83 // Unsupported by now, just quick fallback
84 Flavour = DWARFFlavour::X86_32_Generic;
86 Flavour = DWARFFlavour::X86_32_Generic;
90 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
93 /// getX86RegNum - This function maps LLVM register identifiers to their X86
94 /// specific numbering, which is used in various places encoding instructions.
95 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
97 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
98 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
99 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
100 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
101 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
103 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
105 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
107 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
110 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
112 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
114 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
116 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
118 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
120 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
122 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
124 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
127 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
128 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
129 return RegNo-X86::ST0;
131 case X86::XMM0: case X86::XMM8: case X86::MM0:
133 case X86::XMM1: case X86::XMM9: case X86::MM1:
135 case X86::XMM2: case X86::XMM10: case X86::MM2:
137 case X86::XMM3: case X86::XMM11: case X86::MM3:
139 case X86::XMM4: case X86::XMM12: case X86::MM4:
141 case X86::XMM5: case X86::XMM13: case X86::MM5:
143 case X86::XMM6: case X86::XMM14: case X86::MM6:
145 case X86::XMM7: case X86::XMM15: case X86::MM7:
149 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
150 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
155 const TargetRegisterClass *
156 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
157 const TargetRegisterClass *B,
158 unsigned SubIdx) const {
163 if (B == &X86::GR8RegClass) {
164 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
166 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
167 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
168 A == &X86::GR64_NOREXRegClass ||
169 A == &X86::GR64_NOSPRegClass ||
170 A == &X86::GR64_NOREX_NOSPRegClass)
171 return &X86::GR64_ABCDRegClass;
172 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
173 A == &X86::GR32_NOREXRegClass ||
174 A == &X86::GR32_NOSPRegClass)
175 return &X86::GR32_ABCDRegClass;
176 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
177 A == &X86::GR16_NOREXRegClass)
178 return &X86::GR16_ABCDRegClass;
179 } else if (B == &X86::GR8_NOREXRegClass) {
180 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
181 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
182 return &X86::GR64_NOREXRegClass;
183 else if (A == &X86::GR64_ABCDRegClass)
184 return &X86::GR64_ABCDRegClass;
185 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
186 A == &X86::GR32_NOSPRegClass)
187 return &X86::GR32_NOREXRegClass;
188 else if (A == &X86::GR32_ABCDRegClass)
189 return &X86::GR32_ABCDRegClass;
190 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
191 return &X86::GR16_NOREXRegClass;
192 else if (A == &X86::GR16_ABCDRegClass)
193 return &X86::GR16_ABCDRegClass;
194 } else if (B == &X86::FR32RegClass) {
200 if (B == &X86::GR8_ABCD_HRegClass) {
201 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
202 A == &X86::GR64_NOREXRegClass ||
203 A == &X86::GR64_NOSPRegClass ||
204 A == &X86::GR64_NOREX_NOSPRegClass)
205 return &X86::GR64_ABCDRegClass;
206 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
207 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
208 return &X86::GR32_ABCDRegClass;
209 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
210 A == &X86::GR16_NOREXRegClass)
211 return &X86::GR16_ABCDRegClass;
212 } else if (B == &X86::FR64RegClass) {
218 if (B == &X86::GR16RegClass) {
219 if (A->getSize() == 4 || A->getSize() == 8)
221 } else if (B == &X86::GR16_ABCDRegClass) {
222 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
223 A == &X86::GR64_NOREXRegClass ||
224 A == &X86::GR64_NOSPRegClass ||
225 A == &X86::GR64_NOREX_NOSPRegClass)
226 return &X86::GR64_ABCDRegClass;
227 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
228 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
229 return &X86::GR32_ABCDRegClass;
230 } else if (B == &X86::GR16_NOREXRegClass) {
231 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
232 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
233 return &X86::GR64_NOREXRegClass;
234 else if (A == &X86::GR64_ABCDRegClass)
235 return &X86::GR64_ABCDRegClass;
236 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
237 A == &X86::GR32_NOSPRegClass)
238 return &X86::GR32_NOREXRegClass;
239 else if (A == &X86::GR32_ABCDRegClass)
240 return &X86::GR64_ABCDRegClass;
241 } else if (B == &X86::VR128RegClass) {
247 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
248 if (A->getSize() == 8)
250 } else if (B == &X86::GR32_ABCDRegClass) {
251 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
252 A == &X86::GR64_NOREXRegClass ||
253 A == &X86::GR64_NOSPRegClass ||
254 A == &X86::GR64_NOREX_NOSPRegClass)
255 return &X86::GR64_ABCDRegClass;
256 } else if (B == &X86::GR32_NOREXRegClass) {
257 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
258 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
259 return &X86::GR64_NOREXRegClass;
260 else if (A == &X86::GR64_ABCDRegClass)
261 return &X86::GR64_ABCDRegClass;
268 const TargetRegisterClass *
269 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
271 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
272 case 0: // Normal GPRs.
273 if (TM.getSubtarget<X86Subtarget>().is64Bit())
274 return &X86::GR64RegClass;
275 return &X86::GR32RegClass;
276 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
277 if (TM.getSubtarget<X86Subtarget>().is64Bit())
278 return &X86::GR64_NOSPRegClass;
279 return &X86::GR32_NOSPRegClass;
283 const TargetRegisterClass *
284 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
285 if (RC == &X86::CCRRegClass) {
287 return &X86::GR64RegClass;
289 return &X86::GR32RegClass;
295 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
296 bool callsEHReturn = false;
299 const MachineFrameInfo *MFI = MF->getFrameInfo();
300 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
301 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
304 static const unsigned CalleeSavedRegs32Bit[] = {
305 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
308 static const unsigned CalleeSavedRegs32EHRet[] = {
309 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
312 static const unsigned CalleeSavedRegs64Bit[] = {
313 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
316 static const unsigned CalleeSavedRegs64EHRet[] = {
317 X86::RAX, X86::RDX, X86::RBX, X86::R12,
318 X86::R13, X86::R14, X86::R15, X86::RBP, 0
321 static const unsigned CalleeSavedRegsWin64[] = {
322 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
323 X86::R12, X86::R13, X86::R14, X86::R15,
324 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
325 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
326 X86::XMM14, X86::XMM15, 0
331 return CalleeSavedRegsWin64;
333 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
335 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
339 const TargetRegisterClass* const*
340 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
341 bool callsEHReturn = false;
344 const MachineFrameInfo *MFI = MF->getFrameInfo();
345 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
346 callsEHReturn = (MMI ? MMI->callsEHReturn() : false);
349 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
350 &X86::GR32RegClass, &X86::GR32RegClass,
351 &X86::GR32RegClass, &X86::GR32RegClass, 0
353 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
354 &X86::GR32RegClass, &X86::GR32RegClass,
355 &X86::GR32RegClass, &X86::GR32RegClass,
356 &X86::GR32RegClass, &X86::GR32RegClass, 0
358 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
359 &X86::GR64RegClass, &X86::GR64RegClass,
360 &X86::GR64RegClass, &X86::GR64RegClass,
361 &X86::GR64RegClass, &X86::GR64RegClass, 0
363 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
364 &X86::GR64RegClass, &X86::GR64RegClass,
365 &X86::GR64RegClass, &X86::GR64RegClass,
366 &X86::GR64RegClass, &X86::GR64RegClass,
367 &X86::GR64RegClass, &X86::GR64RegClass, 0
369 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
370 &X86::GR64RegClass, &X86::GR64RegClass,
371 &X86::GR64RegClass, &X86::GR64RegClass,
372 &X86::GR64RegClass, &X86::GR64RegClass,
373 &X86::GR64RegClass, &X86::GR64RegClass,
374 &X86::VR128RegClass, &X86::VR128RegClass,
375 &X86::VR128RegClass, &X86::VR128RegClass,
376 &X86::VR128RegClass, &X86::VR128RegClass,
377 &X86::VR128RegClass, &X86::VR128RegClass,
378 &X86::VR128RegClass, &X86::VR128RegClass, 0
383 return CalleeSavedRegClassesWin64;
385 return (callsEHReturn ?
386 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
388 return (callsEHReturn ?
389 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
393 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
394 BitVector Reserved(getNumRegs());
395 // Set the stack-pointer register and its aliases as reserved.
396 Reserved.set(X86::RSP);
397 Reserved.set(X86::ESP);
398 Reserved.set(X86::SP);
399 Reserved.set(X86::SPL);
401 // Set the instruction pointer register and its aliases as reserved.
402 Reserved.set(X86::RIP);
403 Reserved.set(X86::EIP);
404 Reserved.set(X86::IP);
406 // Set the frame-pointer register and its aliases as reserved if needed.
408 Reserved.set(X86::RBP);
409 Reserved.set(X86::EBP);
410 Reserved.set(X86::BP);
411 Reserved.set(X86::BPL);
414 // Mark the x87 stack registers as reserved, since they don't behave normally
415 // with respect to liveness. We don't fully model the effects of x87 stack
416 // pushes and pops after stackification.
417 Reserved.set(X86::ST0);
418 Reserved.set(X86::ST1);
419 Reserved.set(X86::ST2);
420 Reserved.set(X86::ST3);
421 Reserved.set(X86::ST4);
422 Reserved.set(X86::ST5);
423 Reserved.set(X86::ST6);
424 Reserved.set(X86::ST7);
428 //===----------------------------------------------------------------------===//
429 // Stack Frame Processing methods
430 //===----------------------------------------------------------------------===//
432 /// hasFP - Return true if the specified function should have a dedicated frame
433 /// pointer register. This is true if the function has variable sized allocas
434 /// or if frame pointer elimination is disabled.
435 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
436 const MachineFrameInfo *MFI = MF.getFrameInfo();
437 const MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
439 return (NoFramePointerElim ||
440 needsStackRealignment(MF) ||
441 MFI->hasVarSizedObjects() ||
442 MFI->isFrameAddressTaken() ||
443 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
444 (MMI && MMI->callsUnwindInit()));
447 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
448 const MachineFrameInfo *MFI = MF.getFrameInfo();
449 return (RealignStack &&
450 !MFI->hasVarSizedObjects());
453 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
454 const MachineFrameInfo *MFI = MF.getFrameInfo();
455 const Function *F = MF.getFunction();
456 bool requiresRealignment =
457 RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
458 F->hasFnAttr(Attribute::StackAlignment));
460 // FIXME: Currently we don't support stack realignment for functions with
461 // variable-sized allocas.
462 // FIXME: Temporary disable the error - it seems to be too conservative.
463 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
465 "Stack realignment in presense of dynamic allocas is not supported");
467 return (requiresRealignment && !MFI->hasVarSizedObjects());
470 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
471 return !MF.getFrameInfo()->hasVarSizedObjects();
474 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
475 int &FrameIdx) const {
476 if (Reg == FramePtr && hasFP(MF)) {
477 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
484 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
485 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
486 const MachineFrameInfo *MFI = MF.getFrameInfo();
487 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
488 uint64_t StackSize = MFI->getStackSize();
490 if (needsStackRealignment(MF)) {
492 // Skip the saved EBP.
495 unsigned Align = MFI->getObjectAlignment(FI);
496 assert((-(Offset + StackSize)) % Align == 0);
498 return Offset + StackSize;
500 // FIXME: Support tail calls
503 return Offset + StackSize;
505 // Skip the saved EBP.
508 // Skip the RETADDR move area
509 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
510 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
511 if (TailCallReturnAddrDelta < 0)
512 Offset -= TailCallReturnAddrDelta;
518 void X86RegisterInfo::
519 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
520 MachineBasicBlock::iterator I) const {
521 if (!hasReservedCallFrame(MF)) {
522 // If the stack pointer can be changed after prologue, turn the
523 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
524 // adjcallstackdown instruction into 'add ESP, <amt>'
525 // TODO: consider using push / pop instead of sub + store / add
526 MachineInstr *Old = I;
527 uint64_t Amount = Old->getOperand(0).getImm();
529 // We need to keep the stack aligned properly. To do this, we round the
530 // amount of space needed for the outgoing arguments up to the next
531 // alignment boundary.
532 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
534 MachineInstr *New = 0;
535 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
536 New = BuildMI(MF, Old->getDebugLoc(),
537 TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri),
542 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
544 // Factor out the amount the callee already popped.
545 uint64_t CalleeAmt = Old->getOperand(1).getImm();
549 unsigned Opc = (Amount < 128) ?
550 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
551 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri);
552 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
559 // The EFLAGS implicit def is dead.
560 New->getOperand(3).setIsDead();
562 // Replace the pseudo instruction with a new instruction.
566 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
567 // If we are performing frame pointer elimination and if the callee pops
568 // something off the stack pointer, add it back. We do this until we have
569 // more advanced stack pointer tracking ability.
570 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
571 unsigned Opc = (CalleeAmt < 128) ?
572 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
573 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri);
574 MachineInstr *Old = I;
576 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
581 // The EFLAGS implicit def is dead.
582 New->getOperand(3).setIsDead();
591 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
592 int SPAdj, int *Value,
593 RegScavenger *RS) const{
594 assert(SPAdj == 0 && "Unexpected");
597 MachineInstr &MI = *II;
598 MachineFunction &MF = *MI.getParent()->getParent();
600 while (!MI.getOperand(i).isFI()) {
602 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
605 int FrameIndex = MI.getOperand(i).getIndex();
608 if (needsStackRealignment(MF))
609 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
611 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
613 // This must be part of a four operand memory reference. Replace the
614 // FrameIndex with base register with EBP. Add an offset to the offset.
615 MI.getOperand(i).ChangeToRegister(BasePtr, false);
617 // Now add the frame object offset to the offset from EBP.
618 if (MI.getOperand(i+3).isImm()) {
619 // Offset is a 32-bit integer.
620 int Offset = getFrameIndexOffset(MF, FrameIndex) +
621 (int)(MI.getOperand(i + 3).getImm());
623 MI.getOperand(i + 3).ChangeToImmediate(Offset);
625 // Offset is symbolic. This is extremely rare.
626 uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) +
627 (uint64_t)MI.getOperand(i+3).getOffset();
628 MI.getOperand(i+3).setOffset(Offset);
634 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
635 RegScavenger *RS) const {
636 MachineFrameInfo *MFI = MF.getFrameInfo();
638 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
639 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
641 if (TailCallReturnAddrDelta < 0) {
642 // create RETURNADDR area
651 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
652 (-1U*SlotSize)+TailCallReturnAddrDelta,
657 assert((TailCallReturnAddrDelta <= 0) &&
658 "The Delta should always be zero or negative");
659 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
661 // Create a frame entry for the EBP register that must be saved.
662 int FrameIdx = MFI->CreateFixedObject(SlotSize,
664 TFI.getOffsetOfLocalArea() +
665 TailCallReturnAddrDelta,
667 assert(FrameIdx == MFI->getObjectIndexBegin() &&
668 "Slot for EBP register must be last in order to be found!");
673 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
674 /// stack pointer by a constant value.
676 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
677 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
678 const TargetInstrInfo &TII) {
679 bool isSub = NumBytes < 0;
680 uint64_t Offset = isSub ? -NumBytes : NumBytes;
683 (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) :
684 (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri))
686 (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) :
687 (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri));
688 uint64_t Chunk = (1LL << 31) - 1;
689 DebugLoc DL = MBB.findDebugLoc(MBBI);
692 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
694 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
697 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
702 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
704 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
705 unsigned StackPtr, uint64_t *NumBytes = NULL) {
706 if (MBBI == MBB.begin()) return;
708 MachineBasicBlock::iterator PI = prior(MBBI);
709 unsigned Opc = PI->getOpcode();
710 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
711 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
712 PI->getOperand(0).getReg() == StackPtr) {
714 *NumBytes += PI->getOperand(2).getImm();
716 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
717 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
718 PI->getOperand(0).getReg() == StackPtr) {
720 *NumBytes -= PI->getOperand(2).getImm();
725 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
727 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
728 MachineBasicBlock::iterator &MBBI,
729 unsigned StackPtr, uint64_t *NumBytes = NULL) {
730 // FIXME: THIS ISN'T RUN!!!
733 if (MBBI == MBB.end()) return;
735 MachineBasicBlock::iterator NI = llvm::next(MBBI);
736 if (NI == MBB.end()) return;
738 unsigned Opc = NI->getOpcode();
739 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
740 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
741 NI->getOperand(0).getReg() == StackPtr) {
743 *NumBytes -= NI->getOperand(2).getImm();
746 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
747 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
748 NI->getOperand(0).getReg() == StackPtr) {
750 *NumBytes += NI->getOperand(2).getImm();
756 /// mergeSPUpdates - Checks the instruction before/after the passed
757 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
758 /// stack adjustment is returned as a positive value for ADD and a negative for
760 static int mergeSPUpdates(MachineBasicBlock &MBB,
761 MachineBasicBlock::iterator &MBBI,
763 bool doMergeWithPrevious) {
764 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
765 (!doMergeWithPrevious && MBBI == MBB.end()))
768 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
769 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
770 unsigned Opc = PI->getOpcode();
773 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
774 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
775 PI->getOperand(0).getReg() == StackPtr){
776 Offset += PI->getOperand(2).getImm();
778 if (!doMergeWithPrevious) MBBI = NI;
779 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
780 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
781 PI->getOperand(0).getReg() == StackPtr) {
782 Offset -= PI->getOperand(2).getImm();
784 if (!doMergeWithPrevious) MBBI = NI;
790 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
792 unsigned FramePtr) const {
793 MachineFrameInfo *MFI = MF.getFrameInfo();
794 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
797 // Add callee saved registers to move list.
798 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
799 if (CSI.empty()) return;
801 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
802 const TargetData *TD = MF.getTarget().getTargetData();
803 bool HasFP = hasFP(MF);
805 // Calculate amount of bytes used for return address storing.
807 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
808 TargetFrameInfo::StackGrowsUp ?
809 TD->getPointerSize() : -TD->getPointerSize());
811 // FIXME: This is dirty hack. The code itself is pretty mess right now.
812 // It should be rewritten from scratch and generalized sometimes.
814 // Determine maximum offset (minumum due to stack growth).
815 int64_t MaxOffset = 0;
816 for (std::vector<CalleeSavedInfo>::const_iterator
817 I = CSI.begin(), E = CSI.end(); I != E; ++I)
818 MaxOffset = std::min(MaxOffset,
819 MFI->getObjectOffset(I->getFrameIdx()));
821 // Calculate offsets.
822 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
823 for (std::vector<CalleeSavedInfo>::const_iterator
824 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
825 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
826 unsigned Reg = I->getReg();
827 Offset = MaxOffset - Offset + saveAreaOffset;
829 // Don't output a new machine move if we're re-saving the frame
830 // pointer. This happens when the PrologEpilogInserter has inserted an extra
831 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
832 // generates one when frame pointers are used. If we generate a "machine
833 // move" for this extra "PUSH", the linker will lose track of the fact that
834 // the frame pointer should have the value of the first "PUSH" when it's
837 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
838 // another bug. I.e., one where we generate a prolog like this:
846 // The immediate re-push of EBP is unnecessary. At the least, it's an
847 // optimization bug. EBP can be used as a scratch register in certain
848 // cases, but probably not when we have a frame pointer.
849 if (HasFP && FramePtr == Reg)
852 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
853 MachineLocation CSSrc(Reg);
854 Moves.push_back(MachineMove(LabelId, CSDst, CSSrc));
858 /// emitPrologue - Push callee-saved registers onto the stack, which
859 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
860 /// space for local variables. Also emit labels used by the exception handler to
861 /// generate the exception handling frames.
862 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
863 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
864 MachineBasicBlock::iterator MBBI = MBB.begin();
865 MachineFrameInfo *MFI = MF.getFrameInfo();
866 const Function *Fn = MF.getFunction();
867 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
868 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
869 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
870 bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
871 !Fn->doesNotThrow() || UnwindTablesMandatory;
872 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
873 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
874 bool HasFP = hasFP(MF);
877 // Add RETADDR move area to callee saved frame size.
878 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
879 if (TailCallReturnAddrDelta < 0)
880 X86FI->setCalleeSavedFrameSize(
881 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
883 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
884 // function, and use up to 128 bytes of stack space, don't have a frame
885 // pointer, calls, or dynamic alloca then we do not need to adjust the
886 // stack pointer (we fit in the Red Zone).
887 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
888 !needsStackRealignment(MF) &&
889 !MFI->hasVarSizedObjects() && // No dynamic alloca.
890 !MFI->hasCalls() && // No calls.
891 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
892 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
893 if (HasFP) MinSize += SlotSize;
894 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
895 MFI->setStackSize(StackSize);
896 } else if (Subtarget->isTargetWin64()) {
897 // We need to always allocate 32 bytes as register spill area.
898 // FIXME: We might reuse these 32 bytes for leaf functions.
900 MFI->setStackSize(StackSize);
903 // Insert stack pointer adjustment for later moving of return addr. Only
904 // applies to tail call optimized functions where the callee argument stack
905 // size is bigger than the callers.
906 if (TailCallReturnAddrDelta < 0) {
908 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri),
911 .addImm(-TailCallReturnAddrDelta);
912 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
915 // Mapping for machine moves:
917 // DST: VirtualFP AND
918 // SRC: VirtualFP => DW_CFA_def_cfa_offset
919 // ELSE => DW_CFA_def_cfa
921 // SRC: VirtualFP AND
922 // DST: Register => DW_CFA_def_cfa_register
925 // OFFSET < 0 => DW_CFA_offset_extended_sf
926 // REG < 64 => DW_CFA_offset + Reg
927 // ELSE => DW_CFA_offset_extended
929 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
930 const TargetData *TD = MF.getTarget().getTargetData();
931 uint64_t NumBytes = 0;
933 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
934 TargetFrameInfo::StackGrowsUp ?
935 TD->getPointerSize() : -TD->getPointerSize());
938 // Calculate required stack adjustment.
939 uint64_t FrameSize = StackSize - SlotSize;
940 if (needsStackRealignment(MF))
941 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
943 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
945 // Get the offset of the stack slot for the EBP register, which is
946 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
947 // Update the frame offset adjustment.
948 MFI->setOffsetAdjustment(-NumBytes);
950 // Save EBP/RBP into the appropriate stack slot.
951 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
952 .addReg(FramePtr, RegState::Kill);
954 if (needsFrameMoves) {
955 // Mark the place where EBP/RBP was saved.
956 unsigned FrameLabelId = MMI->NextLabelID();
957 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
959 // Define the current CFA rule to use the provided offset.
961 MachineLocation SPDst(MachineLocation::VirtualFP);
962 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
963 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
965 // FIXME: Verify & implement for FP
966 MachineLocation SPDst(StackPtr);
967 MachineLocation SPSrc(StackPtr, stackGrowth);
968 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
971 // Change the rule for the FramePtr to be an "offset" rule.
972 MachineLocation FPDst(MachineLocation::VirtualFP,
974 MachineLocation FPSrc(FramePtr);
975 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
978 // Update EBP with the new base value...
979 BuildMI(MBB, MBBI, DL,
980 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
983 if (needsFrameMoves) {
984 // Mark effective beginning of when frame pointer becomes valid.
985 unsigned FrameLabelId = MMI->NextLabelID();
986 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
988 // Define the current CFA to use the EBP/RBP register.
989 MachineLocation FPDst(FramePtr);
990 MachineLocation FPSrc(MachineLocation::VirtualFP);
991 Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
994 // Mark the FramePtr as live-in in every block except the entry.
995 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
997 I->addLiveIn(FramePtr);
1000 if (needsStackRealignment(MF)) {
1002 BuildMI(MBB, MBBI, DL,
1003 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1004 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1006 // The EFLAGS implicit def is dead.
1007 MI->getOperand(3).setIsDead();
1010 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1013 // Skip the callee-saved push instructions.
1014 bool PushedRegs = false;
1015 int StackOffset = 2 * stackGrowth;
1017 while (MBBI != MBB.end() &&
1018 (MBBI->getOpcode() == X86::PUSH32r ||
1019 MBBI->getOpcode() == X86::PUSH64r)) {
1023 if (!HasFP && needsFrameMoves) {
1024 // Mark callee-saved push instruction.
1025 unsigned LabelId = MMI->NextLabelID();
1026 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1028 // Define the current CFA rule to use the provided offset.
1029 unsigned Ptr = StackSize ?
1030 MachineLocation::VirtualFP : StackPtr;
1031 MachineLocation SPDst(Ptr);
1032 MachineLocation SPSrc(Ptr, StackOffset);
1033 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1034 StackOffset += stackGrowth;
1038 DL = MBB.findDebugLoc(MBBI);
1040 // Adjust stack pointer: ESP -= numbytes.
1041 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1042 // Check, whether EAX is livein for this function.
1043 bool isEAXAlive = false;
1044 for (MachineRegisterInfo::livein_iterator
1045 II = MF.getRegInfo().livein_begin(),
1046 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1047 unsigned Reg = II->first;
1048 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1049 Reg == X86::AH || Reg == X86::AL);
1052 // Function prologue calls _alloca to probe the stack when allocating more
1053 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1054 // to ensure that the guard pages used by the OS virtual memory manager are
1055 // allocated in correct sequence.
1057 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1059 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1060 .addExternalSymbol("_alloca")
1061 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1064 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1065 .addReg(X86::EAX, RegState::Kill);
1067 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1068 // allocated bytes for EAX.
1069 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1070 .addImm(NumBytes - 4);
1071 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1072 .addExternalSymbol("_alloca")
1073 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1076 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1078 StackPtr, false, NumBytes - 4);
1079 MBB.insert(MBBI, MI);
1081 } else if (NumBytes) {
1082 // If there is an SUB32ri of ESP immediately before this instruction, merge
1083 // the two. This can be the case when tail call elimination is enabled and
1084 // the callee has more arguments then the caller.
1085 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1087 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1088 // instruction, merge the two instructions.
1089 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1092 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1095 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1096 // Mark end of stack pointer adjustment.
1097 unsigned LabelId = MMI->NextLabelID();
1098 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(LabelId);
1100 if (!HasFP && NumBytes) {
1101 // Define the current CFA rule to use the provided offset.
1103 MachineLocation SPDst(MachineLocation::VirtualFP);
1104 MachineLocation SPSrc(MachineLocation::VirtualFP,
1105 -StackSize + stackGrowth);
1106 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1108 // FIXME: Verify & implement for FP
1109 MachineLocation SPDst(StackPtr);
1110 MachineLocation SPSrc(StackPtr, stackGrowth);
1111 Moves.push_back(MachineMove(LabelId, SPDst, SPSrc));
1115 // Emit DWARF info specifying the offsets of the callee-saved registers.
1117 emitCalleeSavedFrameMoves(MF, LabelId, HasFP ? FramePtr : StackPtr);
1121 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1122 MachineBasicBlock &MBB) const {
1123 const MachineFrameInfo *MFI = MF.getFrameInfo();
1124 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1125 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1126 unsigned RetOpcode = MBBI->getOpcode();
1127 DebugLoc DL = MBBI->getDebugLoc();
1129 switch (RetOpcode) {
1131 llvm_unreachable("Can only insert epilog into returning blocks");
1134 case X86::TCRETURNdi:
1135 case X86::TCRETURNri:
1136 case X86::TCRETURNri64:
1137 case X86::TCRETURNdi64:
1138 case X86::EH_RETURN:
1139 case X86::EH_RETURN64:
1143 break; // These are ok
1146 // Get the number of bytes to allocate from the FrameInfo.
1147 uint64_t StackSize = MFI->getStackSize();
1148 uint64_t MaxAlign = MFI->getMaxAlignment();
1149 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1150 uint64_t NumBytes = 0;
1153 // Calculate required stack adjustment.
1154 uint64_t FrameSize = StackSize - SlotSize;
1155 if (needsStackRealignment(MF))
1156 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1158 NumBytes = FrameSize - CSSize;
1161 BuildMI(MBB, MBBI, DL,
1162 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1164 NumBytes = StackSize - CSSize;
1167 // Skip the callee-saved pop instructions.
1168 MachineBasicBlock::iterator LastCSPop = MBBI;
1169 while (MBBI != MBB.begin()) {
1170 MachineBasicBlock::iterator PI = prior(MBBI);
1171 unsigned Opc = PI->getOpcode();
1173 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1174 !PI->getDesc().isTerminator())
1180 DL = MBBI->getDebugLoc();
1182 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1183 // instruction, merge the two instructions.
1184 if (NumBytes || MFI->hasVarSizedObjects())
1185 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1187 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1188 // slot before popping them off! Same applies for the case, when stack was
1190 if (needsStackRealignment(MF)) {
1191 // We cannot use LEA here, because stack pointer was realigned. We need to
1192 // deallocate local frame back.
1194 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1195 MBBI = prior(LastCSPop);
1198 BuildMI(MBB, MBBI, DL,
1199 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1200 StackPtr).addReg(FramePtr);
1201 } else if (MFI->hasVarSizedObjects()) {
1203 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1205 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1206 FramePtr, false, -CSSize);
1207 MBB.insert(MBBI, MI);
1209 BuildMI(MBB, MBBI, DL,
1210 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1213 } else if (NumBytes) {
1214 // Adjust stack pointer back: ESP += numbytes.
1215 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1218 // We're returning from function via eh_return.
1219 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1220 MBBI = prior(MBB.end());
1221 MachineOperand &DestAddr = MBBI->getOperand(0);
1222 assert(DestAddr.isReg() && "Offset should be in register!");
1223 BuildMI(MBB, MBBI, DL,
1224 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1225 StackPtr).addReg(DestAddr.getReg());
1226 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1227 RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) {
1228 // Tail call return: adjust the stack pointer and jump to callee.
1229 MBBI = prior(MBB.end());
1230 MachineOperand &JumpTarget = MBBI->getOperand(0);
1231 MachineOperand &StackAdjust = MBBI->getOperand(1);
1232 assert(StackAdjust.isImm() && "Expecting immediate value.");
1234 // Adjust stack pointer.
1235 int StackAdj = StackAdjust.getImm();
1236 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1238 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1240 // Incoporate the retaddr area.
1241 Offset = StackAdj-MaxTCDelta;
1242 assert(Offset >= 0 && "Offset should never be negative");
1245 // Check for possible merge with preceeding ADD instruction.
1246 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1247 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1250 // Jump to label or value in register.
1251 if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64) {
1252 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)).
1253 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1254 JumpTarget.getTargetFlags());
1255 } else if (RetOpcode == X86::TCRETURNri64) {
1256 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1258 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1261 MachineInstr *NewMI = prior(MBBI);
1262 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1263 NewMI->addOperand(MBBI->getOperand(i));
1265 // Delete the pseudo instruction TCRETURN.
1267 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1268 (X86FI->getTCReturnAddrDelta() < 0)) {
1269 // Add the return addr area delta back since we are not tail calling.
1270 int delta = -1*X86FI->getTCReturnAddrDelta();
1271 MBBI = prior(MBB.end());
1273 // Check for possible merge with preceeding ADD instruction.
1274 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1275 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1279 unsigned X86RegisterInfo::getRARegister() const {
1280 return Is64Bit ? X86::RIP // Should have dwarf #16.
1281 : X86::EIP; // Should have dwarf #8.
1284 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1285 return hasFP(MF) ? FramePtr : StackPtr;
1289 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1290 // Calculate amount of bytes used for return address storing
1291 int stackGrowth = (Is64Bit ? -8 : -4);
1293 // Initial state of the frame pointer is esp+4.
1294 MachineLocation Dst(MachineLocation::VirtualFP);
1295 MachineLocation Src(StackPtr, stackGrowth);
1296 Moves.push_back(MachineMove(0, Dst, Src));
1298 // Add return address to move list
1299 MachineLocation CSDst(StackPtr, stackGrowth);
1300 MachineLocation CSSrc(getRARegister());
1301 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1304 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1305 llvm_unreachable("What is the exception register");
1309 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1310 llvm_unreachable("What is the exception handler register");
1315 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1316 switch (VT.getSimpleVT().SimpleTy) {
1317 default: return Reg;
1322 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1324 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1326 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1328 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1334 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1336 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1338 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1340 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1342 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1344 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1346 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1348 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1350 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1352 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1354 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1356 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1358 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1360 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1362 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1364 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1370 default: return Reg;
1371 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1373 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1375 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1377 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1379 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1381 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1383 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1385 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1387 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1389 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1391 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1393 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1395 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1397 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1399 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1401 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1406 default: return Reg;
1407 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1409 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1411 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1413 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1415 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1417 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1419 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1421 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1423 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1425 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1427 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1429 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1431 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1433 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1435 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1437 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1442 default: return Reg;
1443 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1445 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1447 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1449 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1451 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1453 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1455 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1457 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1459 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1461 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1463 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1465 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1467 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1469 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1471 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1473 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1482 #include "X86GenRegisterInfo.inc"