1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "llvm/ADT/SmallString.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
22 #include "llvm/CodeGen/StackMaps.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/GlobalValue.h"
25 #include "llvm/IR/Mangler.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCCodeEmitter.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstBuilder.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/Support/TargetRegistry.h"
39 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
40 class X86MCInstLower {
42 const MachineFunction &MF;
43 const TargetMachine &TM;
45 X86AsmPrinter &AsmPrinter;
47 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
49 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
51 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
52 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
55 MachineModuleInfoMachO &getMachOMMI() const;
56 Mangler *getMang() const {
57 return AsmPrinter.Mang;
61 } // end anonymous namespace
63 // Emit a minimal sequence of nops spanning NumBytes bytes.
64 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
65 const MCSubtargetInfo &STI);
68 X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
69 : TM(TM), Count(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
71 X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
74 X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &MF) {
75 CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(*TM.getInstrInfo(),
76 *TM.getRegisterInfo(),
77 *TM.getSubtargetImpl(),
81 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
82 const MCSubtargetInfo &STI) {
84 SmallString<256> Code;
85 SmallVector<MCFixup, 4> Fixups;
86 raw_svector_ostream VecOS(Code);
87 CodeEmitter->EncodeInstruction(Inst, VecOS, Fixups, STI);
89 CurrentShadowSize += Code.size();
90 if (CurrentShadowSize >= RequiredShadowSize)
91 Count = false; // The shadow is big enough. Stop counting.
95 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
96 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
97 if (Count && CurrentShadowSize < RequiredShadowSize)
98 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
99 TM.getSubtarget<X86Subtarget>().is64Bit(), STI);
103 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
104 OutStreamer.EmitInstruction(Inst, getSubtargetInfo());
105 SMShadowTracker.count(Inst, getSubtargetInfo());
107 } // end llvm namespace
109 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
110 X86AsmPrinter &asmprinter)
111 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()),
112 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
114 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
115 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
119 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
120 /// operand to an MCSymbol.
121 MCSymbol *X86MCInstLower::
122 GetSymbolFromOperand(const MachineOperand &MO) const {
123 const DataLayout *DL = TM.getDataLayout();
124 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
126 SmallString<128> Name;
129 switch (MO.getTargetFlags()) {
130 case X86II::MO_DLLIMPORT:
131 // Handle dllimport linkage.
134 case X86II::MO_DARWIN_STUB:
137 case X86II::MO_DARWIN_NONLAZY:
138 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
139 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
140 Suffix = "$non_lazy_ptr";
145 Name += DL->getPrivateGlobalPrefix();
147 unsigned PrefixLen = Name.size();
150 const GlobalValue *GV = MO.getGlobal();
151 AsmPrinter.getNameWithPrefix(Name, GV);
152 } else if (MO.isSymbol()) {
153 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
154 } else if (MO.isMBB()) {
155 Name += MO.getMBB()->getSymbol()->getName();
157 unsigned OrigLen = Name.size() - PrefixLen;
160 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name);
162 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
164 // If the target flags on the operand changes the name of the symbol, do that
165 // before we return the symbol.
166 switch (MO.getTargetFlags()) {
168 case X86II::MO_DARWIN_NONLAZY:
169 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
170 MachineModuleInfoImpl::StubValueTy &StubSym =
171 getMachOMMI().getGVStubEntry(Sym);
172 if (!StubSym.getPointer()) {
173 assert(MO.isGlobal() && "Extern symbol not handled yet");
175 MachineModuleInfoImpl::
176 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
177 !MO.getGlobal()->hasInternalLinkage());
181 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
182 MachineModuleInfoImpl::StubValueTy &StubSym =
183 getMachOMMI().getHiddenGVStubEntry(Sym);
184 if (!StubSym.getPointer()) {
185 assert(MO.isGlobal() && "Extern symbol not handled yet");
187 MachineModuleInfoImpl::
188 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
189 !MO.getGlobal()->hasInternalLinkage());
193 case X86II::MO_DARWIN_STUB: {
194 MachineModuleInfoImpl::StubValueTy &StubSym =
195 getMachOMMI().getFnStubEntry(Sym);
196 if (StubSym.getPointer())
201 MachineModuleInfoImpl::
202 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
203 !MO.getGlobal()->hasInternalLinkage());
206 MachineModuleInfoImpl::
207 StubValueTy(Ctx.GetOrCreateSymbol(OrigName), false);
216 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
217 MCSymbol *Sym) const {
218 // FIXME: We would like an efficient form for this, so we don't have to do a
219 // lot of extra uniquing.
220 const MCExpr *Expr = nullptr;
221 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
223 switch (MO.getTargetFlags()) {
224 default: llvm_unreachable("Unknown target flag on GV operand");
225 case X86II::MO_NO_FLAG: // No flag.
226 // These affect the name of the symbol, not any suffix.
227 case X86II::MO_DARWIN_NONLAZY:
228 case X86II::MO_DLLIMPORT:
229 case X86II::MO_DARWIN_STUB:
232 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
233 case X86II::MO_TLVP_PIC_BASE:
234 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
235 // Subtract the pic base.
236 Expr = MCBinaryExpr::CreateSub(Expr,
237 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
241 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
242 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
243 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
244 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
245 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
246 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
247 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
248 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
249 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
250 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
251 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
252 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
253 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
254 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
255 case X86II::MO_PIC_BASE_OFFSET:
256 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
257 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
258 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
259 // Subtract the pic base.
260 Expr = MCBinaryExpr::CreateSub(Expr,
261 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
263 if (MO.isJTI() && MAI.hasSetDirective()) {
264 // If .set directive is supported, use it to reduce the number of
265 // relocations the assembler will generate for differences between
266 // local labels. This is only safe when the symbols are in the same
267 // section so we are restricting it to jumptable references.
268 MCSymbol *Label = Ctx.CreateTempSymbol();
269 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
270 Expr = MCSymbolRefExpr::Create(Label, Ctx);
276 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
278 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
279 Expr = MCBinaryExpr::CreateAdd(Expr,
280 MCConstantExpr::Create(MO.getOffset(), Ctx),
282 return MCOperand::CreateExpr(Expr);
286 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
287 /// a short fixed-register form.
288 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
289 unsigned ImmOp = Inst.getNumOperands() - 1;
290 assert(Inst.getOperand(0).isReg() &&
291 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
292 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
293 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
294 Inst.getNumOperands() == 2) && "Unexpected instruction!");
296 // Check whether the destination register can be fixed.
297 unsigned Reg = Inst.getOperand(0).getReg();
298 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
301 // If so, rewrite the instruction.
302 MCOperand Saved = Inst.getOperand(ImmOp);
304 Inst.setOpcode(Opcode);
305 Inst.addOperand(Saved);
308 /// \brief If a movsx instruction has a shorter encoding for the used register
309 /// simplify the instruction to use it instead.
310 static void SimplifyMOVSX(MCInst &Inst) {
311 unsigned NewOpcode = 0;
312 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
313 switch (Inst.getOpcode()) {
315 llvm_unreachable("Unexpected instruction!");
316 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
317 if (Op0 == X86::AX && Op1 == X86::AL)
318 NewOpcode = X86::CBW;
320 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
321 if (Op0 == X86::EAX && Op1 == X86::AX)
322 NewOpcode = X86::CWDE;
324 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
325 if (Op0 == X86::RAX && Op1 == X86::EAX)
326 NewOpcode = X86::CDQE;
330 if (NewOpcode != 0) {
332 Inst.setOpcode(NewOpcode);
336 /// \brief Simplify things like MOV32rm to MOV32o32a.
337 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
339 // Don't make these simplifications in 64-bit mode; other assemblers don't
340 // perform them because they make the code larger.
341 if (Printer.getSubtarget().is64Bit())
344 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
345 unsigned AddrBase = IsStore;
346 unsigned RegOp = IsStore ? 0 : 5;
347 unsigned AddrOp = AddrBase + 3;
348 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
349 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
350 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
351 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
352 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
353 (Inst.getOperand(AddrOp).isExpr() ||
354 Inst.getOperand(AddrOp).isImm()) &&
355 "Unexpected instruction!");
357 // Check whether the destination register can be fixed.
358 unsigned Reg = Inst.getOperand(RegOp).getReg();
359 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
362 // Check whether this is an absolute address.
363 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
365 bool Absolute = true;
366 if (Inst.getOperand(AddrOp).isExpr()) {
367 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
368 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
369 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
374 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
375 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
376 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
379 // If so, rewrite the instruction.
380 MCOperand Saved = Inst.getOperand(AddrOp);
381 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
383 Inst.setOpcode(Opcode);
384 Inst.addOperand(Saved);
385 Inst.addOperand(Seg);
388 static unsigned getRetOpcode(const X86Subtarget &Subtarget)
390 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
393 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
394 OutMI.setOpcode(MI->getOpcode());
396 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
397 const MachineOperand &MO = MI->getOperand(i);
400 switch (MO.getType()) {
403 llvm_unreachable("unknown operand type");
404 case MachineOperand::MO_Register:
405 // Ignore all implicit register operands.
406 if (MO.isImplicit()) continue;
407 MCOp = MCOperand::CreateReg(MO.getReg());
409 case MachineOperand::MO_Immediate:
410 MCOp = MCOperand::CreateImm(MO.getImm());
412 case MachineOperand::MO_MachineBasicBlock:
413 case MachineOperand::MO_GlobalAddress:
414 case MachineOperand::MO_ExternalSymbol:
415 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
417 case MachineOperand::MO_JumpTableIndex:
418 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
420 case MachineOperand::MO_ConstantPoolIndex:
421 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
423 case MachineOperand::MO_BlockAddress:
424 MCOp = LowerSymbolOperand(MO,
425 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
427 case MachineOperand::MO_RegisterMask:
428 // Ignore call clobbers.
432 OutMI.addOperand(MCOp);
435 // Handle a few special cases to eliminate operand modifiers.
437 switch (OutMI.getOpcode()) {
442 // LEA should have a segment register, but it must be empty.
443 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
444 "Unexpected # of LEA operands");
445 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
446 "LEA has segment specified!");
450 OutMI.setOpcode(X86::MOV32ri);
453 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
454 // if one of the registers is extended, but other isn't.
456 case X86::VMOVAPDYrr:
458 case X86::VMOVAPSYrr:
460 case X86::VMOVDQAYrr:
462 case X86::VMOVDQUYrr:
464 case X86::VMOVUPDYrr:
466 case X86::VMOVUPSYrr: {
467 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
468 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
470 switch (OutMI.getOpcode()) {
471 default: llvm_unreachable("Invalid opcode");
472 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
473 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
474 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
475 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
476 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
477 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
478 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
479 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
480 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
481 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
482 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
483 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
485 OutMI.setOpcode(NewOpc);
490 case X86::VMOVSSrr: {
491 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
492 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
494 switch (OutMI.getOpcode()) {
495 default: llvm_unreachable("Invalid opcode");
496 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
497 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
499 OutMI.setOpcode(NewOpc);
504 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
505 // inputs modeled as normal uses instead of implicit uses. As such, truncate
506 // off all but the first operand (the callee). FIXME: Change isel.
507 case X86::TAILJMPr64:
509 case X86::CALL64pcrel32: {
510 unsigned Opcode = OutMI.getOpcode();
511 MCOperand Saved = OutMI.getOperand(0);
513 OutMI.setOpcode(Opcode);
514 OutMI.addOperand(Saved);
519 case X86::EH_RETURN64: {
521 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
525 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
528 case X86::TAILJMPd64: {
530 switch (OutMI.getOpcode()) {
531 default: llvm_unreachable("Invalid opcode");
532 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
534 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
537 MCOperand Saved = OutMI.getOperand(0);
539 OutMI.setOpcode(Opcode);
540 OutMI.addOperand(Saved);
544 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
545 // this with an ugly goto in case the resultant OR uses EAX and needs the
547 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
548 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
549 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
550 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
551 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
552 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
553 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
554 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
555 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
557 // The assembler backend wants to see branches in their small form and relax
558 // them to their large form. The JIT can only handle the large form because
559 // it does not do relaxation. For now, translate the large form to the
561 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
562 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
563 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
564 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
565 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
566 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
567 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
568 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
569 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
570 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
571 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
572 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
573 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
574 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
575 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
576 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
577 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
579 // Atomic load and store require a separate pseudo-inst because Acquire
580 // implies mayStore and Release implies mayLoad; fix these to regular MOV
582 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
583 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
584 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
585 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
586 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
587 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
588 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
589 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
591 // We don't currently select the correct instruction form for instructions
592 // which have a short %eax, etc. form. Handle this by custom lowering, for
595 // Note, we are currently not handling the following instructions:
596 // MOV64ao8, MOV64o8a
597 // XCHG16ar, XCHG32ar, XCHG64ar
598 case X86::MOV8mr_NOREX:
599 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
600 case X86::MOV8rm_NOREX:
601 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
602 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
603 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
604 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
605 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
607 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
608 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
609 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
610 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
611 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
612 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
613 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
614 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
615 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
616 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
617 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
618 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
619 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
620 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
621 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
622 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
623 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
624 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
625 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
626 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
627 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
628 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
629 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
630 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
631 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
632 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
633 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
634 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
635 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
636 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
637 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
638 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
639 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
640 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
641 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
642 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
644 // Try to shrink some forms of movsx.
645 case X86::MOVSX16rr8:
646 case X86::MOVSX32rr16:
647 case X86::MOVSX64rr32:
648 SimplifyMOVSX(OutMI);
653 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
654 const MachineInstr &MI) {
656 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
657 MI.getOpcode() == X86::TLS_base_addr64;
659 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
661 MCContext &context = OutStreamer.getContext();
664 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
666 MCSymbolRefExpr::VariantKind SRVK;
667 switch (MI.getOpcode()) {
668 case X86::TLS_addr32:
669 case X86::TLS_addr64:
670 SRVK = MCSymbolRefExpr::VK_TLSGD;
672 case X86::TLS_base_addr32:
673 SRVK = MCSymbolRefExpr::VK_TLSLDM;
675 case X86::TLS_base_addr64:
676 SRVK = MCSymbolRefExpr::VK_TLSLD;
679 llvm_unreachable("unexpected opcode");
682 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
683 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
687 LEA.setOpcode(X86::LEA64r);
688 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
689 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
690 LEA.addOperand(MCOperand::CreateImm(1)); // scale
691 LEA.addOperand(MCOperand::CreateReg(0)); // index
692 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
693 LEA.addOperand(MCOperand::CreateReg(0)); // seg
694 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
695 LEA.setOpcode(X86::LEA32r);
696 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
697 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
698 LEA.addOperand(MCOperand::CreateImm(1)); // scale
699 LEA.addOperand(MCOperand::CreateReg(0)); // index
700 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
701 LEA.addOperand(MCOperand::CreateReg(0)); // seg
703 LEA.setOpcode(X86::LEA32r);
704 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
705 LEA.addOperand(MCOperand::CreateReg(0)); // base
706 LEA.addOperand(MCOperand::CreateImm(1)); // scale
707 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
708 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
709 LEA.addOperand(MCOperand::CreateReg(0)); // seg
711 EmitAndCountInstruction(LEA);
714 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
715 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
716 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
719 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
720 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
721 const MCSymbolRefExpr *tlsRef =
722 MCSymbolRefExpr::Create(tlsGetAddr,
723 MCSymbolRefExpr::VK_PLT,
726 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
731 /// \brief Emit the optimal amount of multi-byte nops on X86.
732 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
733 // This works only for 64bit. For 32bit we have to do additional checking if
734 // the CPU supports multi-byte nops.
735 assert(Is64Bit && "EmitNops only supports X86-64");
737 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
738 Opc = IndexReg = Displacement = SegmentReg = 0;
739 BaseReg = X86::RAX; ScaleVal = 1;
741 case 0: llvm_unreachable("Zero nops?"); break;
742 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
743 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
744 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
745 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
746 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
747 IndexReg = X86::RAX; break;
748 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
749 IndexReg = X86::RAX; break;
750 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
751 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
752 IndexReg = X86::RAX; break;
753 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
754 IndexReg = X86::RAX; break;
755 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
756 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
759 unsigned NumPrefixes = std::min(NumBytes, 5U);
760 NumBytes -= NumPrefixes;
761 for (unsigned i = 0; i != NumPrefixes; ++i)
762 OS.EmitBytes("\x66");
765 default: llvm_unreachable("Unexpected opcode"); break;
767 OS.EmitInstruction(MCInstBuilder(Opc), STI);
770 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
774 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
775 .addImm(ScaleVal).addReg(IndexReg)
776 .addImm(Displacement).addReg(SegmentReg), STI);
779 } // while (NumBytes)
782 // Lower a stackmap of the form:
783 // <id>, <shadowBytes>, ...
784 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
785 SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
786 SM.recordStackMap(MI);
787 unsigned NumShadowBytes = MI.getOperand(1).getImm();
788 SMShadowTracker.reset(NumShadowBytes);
791 // Lower a patchpoint of the form:
792 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
793 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI) {
794 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
796 SMShadowTracker.emitShadowPadding(OutStreamer, getSubtargetInfo());
798 SM.recordPatchPoint(MI);
800 PatchPointOpers opers(&MI);
801 unsigned ScratchIdx = opers.getNextScratchIdx();
802 unsigned EncodedBytes = 0;
803 int64_t CallTarget = opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
805 // Emit MOV to materialize the target address and the CALL to target.
806 // This is encoded with 12-13 bytes, depending on which register is used.
807 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
808 if (X86II::isX86_64ExtendedReg(ScratchReg))
812 EmitAndCountInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
813 .addImm(CallTarget));
814 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
817 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
818 assert(NumBytes >= EncodedBytes &&
819 "Patchpoint can't request size less than the length of a call.");
821 EmitNops(OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
825 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
826 X86MCInstLower MCInstLowering(*MF, *this);
827 const X86RegisterInfo *RI =
828 static_cast<const X86RegisterInfo *>(TM.getRegisterInfo());
830 switch (MI->getOpcode()) {
831 case TargetOpcode::DBG_VALUE:
832 llvm_unreachable("Should be handled target independently");
834 // Emit nothing here but a comment if we can.
835 case X86::Int_MemBarrier:
836 OutStreamer.emitRawComment("MEMBARRIER");
841 case X86::EH_RETURN64: {
842 // Lower these as normal, but add some comments.
843 unsigned Reg = MI->getOperand(0).getReg();
844 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
845 X86ATTInstPrinter::getRegisterName(Reg));
850 case X86::TAILJMPd64:
851 // Lower these as normal, but add some comments.
852 OutStreamer.AddComment("TAILCALL");
855 case X86::TLS_addr32:
856 case X86::TLS_addr64:
857 case X86::TLS_base_addr32:
858 case X86::TLS_base_addr64:
859 return LowerTlsAddr(MCInstLowering, *MI);
861 case X86::MOVPC32r: {
862 // This is a pseudo op for a two instruction sequence with a label, which
869 MCSymbol *PICBase = MF->getPICBaseSymbol();
870 // FIXME: We would like an efficient form for this, so we don't have to do a
871 // lot of extra uniquing.
872 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
873 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
876 OutStreamer.EmitLabel(PICBase);
879 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
880 .addReg(MI->getOperand(0).getReg()));
885 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
886 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
889 // Okay, we have something like:
890 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
892 // For this, we want to print something like:
893 // MYGLOBAL + (. - PICBASE)
894 // However, we can't generate a ".", so just emit a new label here and refer
896 MCSymbol *DotSym = OutContext.CreateTempSymbol();
897 OutStreamer.EmitLabel(DotSym);
899 // Now that we have emitted the label, lower the complex operand expression.
900 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
902 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
903 const MCExpr *PICBase =
904 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
905 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
907 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
908 DotExpr, OutContext);
910 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
911 .addReg(MI->getOperand(0).getReg())
912 .addReg(MI->getOperand(1).getReg())
917 case TargetOpcode::STACKMAP:
918 return LowerSTACKMAP(*MI);
920 case TargetOpcode::PATCHPOINT:
921 return LowerPATCHPOINT(*MI);
923 case X86::MORESTACK_RET:
924 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
927 case X86::MORESTACK_RET_RESTORE_R10:
928 // Return, then restore R10.
929 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
930 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
935 case X86::SEH_PushReg:
936 OutStreamer.EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
939 case X86::SEH_SaveReg:
940 OutStreamer.EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
941 MI->getOperand(1).getImm());
944 case X86::SEH_SaveXMM:
945 OutStreamer.EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
946 MI->getOperand(1).getImm());
949 case X86::SEH_StackAlloc:
950 OutStreamer.EmitWinCFIAllocStack(MI->getOperand(0).getImm());
953 case X86::SEH_SetFrame:
954 OutStreamer.EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
955 MI->getOperand(1).getImm());
958 case X86::SEH_PushFrame:
959 OutStreamer.EmitWinCFIPushFrame(MI->getOperand(0).getImm());
962 case X86::SEH_EndPrologue:
963 OutStreamer.EmitWinCFIEndProlog();
968 MCInstLowering.Lower(MI, TmpInst);
969 EmitAndCountInstruction(TmpInst);