1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "InstPrinter/X86ATTInstPrinter.h"
17 #include "X86COFFMachineModuleInfo.h"
18 #include "llvm/ADT/SmallString.h"
19 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
20 #include "llvm/IR/Type.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCInstBuilder.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Support/FormattedStream.h"
29 #include "llvm/Target/Mangler.h"
34 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
35 class X86MCInstLower {
38 const MachineFunction &MF;
39 const TargetMachine &TM;
41 X86AsmPrinter &AsmPrinter;
43 X86MCInstLower(Mangler *mang, const MachineFunction &MF,
44 X86AsmPrinter &asmprinter);
46 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
48 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
49 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
52 MachineModuleInfoMachO &getMachOMMI() const;
55 } // end anonymous namespace
57 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
58 X86AsmPrinter &asmprinter)
59 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
60 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
62 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
63 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
67 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
68 /// operand to an MCSymbol.
69 MCSymbol *X86MCInstLower::
70 GetSymbolFromOperand(const MachineOperand &MO) const {
71 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
73 SmallString<128> Name;
76 const GlobalValue *GV = MO.getGlobal();
77 bool isImplicitlyPrivate = false;
78 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
79 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
80 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
81 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
82 isImplicitlyPrivate = true;
84 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
85 } else if (MO.isSymbol()) {
86 Name += MAI.getGlobalPrefix();
87 Name += MO.getSymbolName();
88 } else if (MO.isMBB()) {
89 Name += MO.getMBB()->getSymbol()->getName();
92 // If the target flags on the operand changes the name of the symbol, do that
93 // before we return the symbol.
94 switch (MO.getTargetFlags()) {
96 case X86II::MO_DLLIMPORT: {
97 // Handle dllimport linkage.
98 const char *Prefix = "__imp_";
99 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
102 case X86II::MO_DARWIN_NONLAZY:
103 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
104 Name += "$non_lazy_ptr";
105 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
107 MachineModuleInfoImpl::StubValueTy &StubSym =
108 getMachOMMI().getGVStubEntry(Sym);
109 if (StubSym.getPointer() == 0) {
110 assert(MO.isGlobal() && "Extern symbol not handled yet");
112 MachineModuleInfoImpl::
113 StubValueTy(Mang->getSymbol(MO.getGlobal()),
114 !MO.getGlobal()->hasInternalLinkage());
118 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
119 Name += "$non_lazy_ptr";
120 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
121 MachineModuleInfoImpl::StubValueTy &StubSym =
122 getMachOMMI().getHiddenGVStubEntry(Sym);
123 if (StubSym.getPointer() == 0) {
124 assert(MO.isGlobal() && "Extern symbol not handled yet");
126 MachineModuleInfoImpl::
127 StubValueTy(Mang->getSymbol(MO.getGlobal()),
128 !MO.getGlobal()->hasInternalLinkage());
132 case X86II::MO_DARWIN_STUB: {
134 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
135 MachineModuleInfoImpl::StubValueTy &StubSym =
136 getMachOMMI().getFnStubEntry(Sym);
137 if (StubSym.getPointer())
142 MachineModuleInfoImpl::
143 StubValueTy(Mang->getSymbol(MO.getGlobal()),
144 !MO.getGlobal()->hasInternalLinkage());
146 Name.erase(Name.end()-5, Name.end());
148 MachineModuleInfoImpl::
149 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
155 return Ctx.GetOrCreateSymbol(Name.str());
158 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
159 MCSymbol *Sym) const {
160 // FIXME: We would like an efficient form for this, so we don't have to do a
161 // lot of extra uniquing.
162 const MCExpr *Expr = 0;
163 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
165 switch (MO.getTargetFlags()) {
166 default: llvm_unreachable("Unknown target flag on GV operand");
167 case X86II::MO_NO_FLAG: // No flag.
168 // These affect the name of the symbol, not any suffix.
169 case X86II::MO_DARWIN_NONLAZY:
170 case X86II::MO_DLLIMPORT:
171 case X86II::MO_DARWIN_STUB:
174 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
175 case X86II::MO_TLVP_PIC_BASE:
176 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
177 // Subtract the pic base.
178 Expr = MCBinaryExpr::CreateSub(Expr,
179 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
183 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
184 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
185 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
186 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
187 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
188 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
189 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
190 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
191 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
192 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
193 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
194 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
195 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
196 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
197 case X86II::MO_PIC_BASE_OFFSET:
198 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
199 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
200 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
201 // Subtract the pic base.
202 Expr = MCBinaryExpr::CreateSub(Expr,
203 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
205 if (MO.isJTI() && MAI.hasSetDirective()) {
206 // If .set directive is supported, use it to reduce the number of
207 // relocations the assembler will generate for differences between
208 // local labels. This is only safe when the symbols are in the same
209 // section so we are restricting it to jumptable references.
210 MCSymbol *Label = Ctx.CreateTempSymbol();
211 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
212 Expr = MCSymbolRefExpr::Create(Label, Ctx);
218 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
220 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
221 Expr = MCBinaryExpr::CreateAdd(Expr,
222 MCConstantExpr::Create(MO.getOffset(), Ctx),
224 return MCOperand::CreateExpr(Expr);
229 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
230 // Convert registers in the addr mode according to subreg32.
231 unsigned Reg = MI->getOperand(OpNo).getReg();
233 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
236 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
237 // Convert registers in the addr mode according to subreg64.
238 for (unsigned i = 0; i != 4; ++i) {
239 if (!MI->getOperand(OpNo+i).isReg()) continue;
241 unsigned Reg = MI->getOperand(OpNo+i).getReg();
242 // LEAs can use RIP-relative addressing, and RIP has no sub/super register.
243 if (Reg == 0 || Reg == X86::RIP) continue;
245 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
249 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
250 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
251 OutMI.setOpcode(NewOpc);
252 lower_subreg32(&OutMI, 0);
254 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
255 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
256 OutMI.setOpcode(NewOpc);
257 OutMI.addOperand(OutMI.getOperand(0));
258 OutMI.addOperand(OutMI.getOperand(0));
261 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
262 /// a short fixed-register form.
263 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
264 unsigned ImmOp = Inst.getNumOperands() - 1;
265 assert(Inst.getOperand(0).isReg() &&
266 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
267 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
268 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
269 Inst.getNumOperands() == 2) && "Unexpected instruction!");
271 // Check whether the destination register can be fixed.
272 unsigned Reg = Inst.getOperand(0).getReg();
273 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
276 // If so, rewrite the instruction.
277 MCOperand Saved = Inst.getOperand(ImmOp);
279 Inst.setOpcode(Opcode);
280 Inst.addOperand(Saved);
283 /// \brief Simplify things like MOV32rm to MOV32o32a.
284 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
286 // Don't make these simplifications in 64-bit mode; other assemblers don't
287 // perform them because they make the code larger.
288 if (Printer.getSubtarget().is64Bit())
291 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
292 unsigned AddrBase = IsStore;
293 unsigned RegOp = IsStore ? 0 : 5;
294 unsigned AddrOp = AddrBase + 3;
295 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
296 Inst.getOperand(AddrBase + 0).isReg() && // base
297 Inst.getOperand(AddrBase + 1).isImm() && // scale
298 Inst.getOperand(AddrBase + 2).isReg() && // index register
299 (Inst.getOperand(AddrOp).isExpr() || // address
300 Inst.getOperand(AddrOp).isImm())&&
301 Inst.getOperand(AddrBase + 4).isReg() && // segment
302 "Unexpected instruction!");
304 // Check whether the destination register can be fixed.
305 unsigned Reg = Inst.getOperand(RegOp).getReg();
306 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
309 // Check whether this is an absolute address.
310 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
312 bool Absolute = true;
313 if (Inst.getOperand(AddrOp).isExpr()) {
314 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
315 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
316 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
321 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
322 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
323 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
324 Inst.getOperand(AddrBase + 1).getImm() != 1))
327 // If so, rewrite the instruction.
328 MCOperand Saved = Inst.getOperand(AddrOp);
330 Inst.setOpcode(Opcode);
331 Inst.addOperand(Saved);
334 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
335 OutMI.setOpcode(MI->getOpcode());
337 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
338 const MachineOperand &MO = MI->getOperand(i);
341 switch (MO.getType()) {
344 llvm_unreachable("unknown operand type");
345 case MachineOperand::MO_Register:
346 // Ignore all implicit register operands.
347 if (MO.isImplicit()) continue;
348 MCOp = MCOperand::CreateReg(MO.getReg());
350 case MachineOperand::MO_Immediate:
351 MCOp = MCOperand::CreateImm(MO.getImm());
353 case MachineOperand::MO_MachineBasicBlock:
354 case MachineOperand::MO_GlobalAddress:
355 case MachineOperand::MO_ExternalSymbol:
356 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
358 case MachineOperand::MO_JumpTableIndex:
359 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
361 case MachineOperand::MO_ConstantPoolIndex:
362 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
364 case MachineOperand::MO_BlockAddress:
365 MCOp = LowerSymbolOperand(MO,
366 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
368 case MachineOperand::MO_RegisterMask:
369 // Ignore call clobbers.
373 OutMI.addOperand(MCOp);
376 // Handle a few special cases to eliminate operand modifiers.
378 switch (OutMI.getOpcode()) {
379 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
380 lower_lea64_32mem(&OutMI, 1);
385 // LEA should have a segment register, but it must be empty.
386 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
387 "Unexpected # of LEA operands");
388 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
389 "LEA has segment specified!");
391 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
392 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
393 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
394 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
395 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
396 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
397 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
398 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
399 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
402 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
403 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
406 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
407 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
410 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
411 // if one of the registers is extended, but other isn't.
413 case X86::VMOVAPDYrr:
415 case X86::VMOVAPSYrr:
417 case X86::VMOVDQAYrr:
419 case X86::VMOVDQUYrr:
423 case X86::VMOVUPDYrr:
425 case X86::VMOVUPSYrr: {
426 if (X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
427 !X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()))
431 switch (OutMI.getOpcode()) {
432 default: llvm_unreachable("Invalid opcode");
433 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
434 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
435 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
436 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
437 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
438 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
439 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
440 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
441 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
442 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
443 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
444 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
445 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
446 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
448 OutMI.setOpcode(NewOpc);
452 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
453 // inputs modeled as normal uses instead of implicit uses. As such, truncate
454 // off all but the first operand (the callee). FIXME: Change isel.
455 case X86::TAILJMPr64:
457 case X86::CALL64pcrel32: {
458 unsigned Opcode = OutMI.getOpcode();
459 MCOperand Saved = OutMI.getOperand(0);
461 OutMI.setOpcode(Opcode);
462 OutMI.addOperand(Saved);
467 case X86::EH_RETURN64: {
469 OutMI.setOpcode(X86::RET);
473 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
476 case X86::TAILJMPd64: {
478 switch (OutMI.getOpcode()) {
479 default: llvm_unreachable("Invalid opcode");
480 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
482 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
485 MCOperand Saved = OutMI.getOperand(0);
487 OutMI.setOpcode(Opcode);
488 OutMI.addOperand(Saved);
492 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
493 // this with an ugly goto in case the resultant OR uses EAX and needs the
495 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
496 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
497 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
498 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
499 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
500 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
501 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
502 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
503 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
505 // The assembler backend wants to see branches in their small form and relax
506 // them to their large form. The JIT can only handle the large form because
507 // it does not do relaxation. For now, translate the large form to the
509 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
510 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
511 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
512 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
513 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
514 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
515 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
516 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
517 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
518 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
519 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
520 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
521 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
522 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
523 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
524 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
525 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
527 // Atomic load and store require a separate pseudo-inst because Acquire
528 // implies mayStore and Release implies mayLoad; fix these to regular MOV
530 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
531 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
532 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
533 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
534 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
535 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
536 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
537 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
539 // We don't currently select the correct instruction form for instructions
540 // which have a short %eax, etc. form. Handle this by custom lowering, for
543 // Note, we are currently not handling the following instructions:
544 // MOV64ao8, MOV64o8a
545 // XCHG16ar, XCHG32ar, XCHG64ar
546 case X86::MOV8mr_NOREX:
547 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
548 case X86::MOV8rm_NOREX:
549 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
550 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
551 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
552 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
553 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
555 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
556 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
557 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
558 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
559 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
560 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
561 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
562 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
563 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
564 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
565 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
566 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
567 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
568 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
569 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
570 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
571 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
572 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
573 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
574 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
575 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
576 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
577 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
578 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
579 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
580 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
581 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
582 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
583 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
584 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
585 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
586 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
587 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
588 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
589 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
590 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
592 case X86::MORESTACK_RET:
593 OutMI.setOpcode(X86::RET);
596 case X86::MORESTACK_RET_RESTORE_R10:
597 OutMI.setOpcode(X86::MOV64rr);
598 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
599 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
601 AsmPrinter.OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
606 static void LowerTlsAddr(MCStreamer &OutStreamer,
607 X86MCInstLower &MCInstLowering,
608 const MachineInstr &MI) {
610 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
611 MI.getOpcode() == X86::TLS_base_addr64;
613 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
615 MCContext &context = OutStreamer.getContext();
618 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
620 MCSymbolRefExpr::VariantKind SRVK;
621 switch (MI.getOpcode()) {
622 case X86::TLS_addr32:
623 case X86::TLS_addr64:
624 SRVK = MCSymbolRefExpr::VK_TLSGD;
626 case X86::TLS_base_addr32:
627 SRVK = MCSymbolRefExpr::VK_TLSLDM;
629 case X86::TLS_base_addr64:
630 SRVK = MCSymbolRefExpr::VK_TLSLD;
633 llvm_unreachable("unexpected opcode");
636 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
637 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
641 LEA.setOpcode(X86::LEA64r);
642 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
643 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
644 LEA.addOperand(MCOperand::CreateImm(1)); // scale
645 LEA.addOperand(MCOperand::CreateReg(0)); // index
646 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
647 LEA.addOperand(MCOperand::CreateReg(0)); // seg
648 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
649 LEA.setOpcode(X86::LEA32r);
650 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
651 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
652 LEA.addOperand(MCOperand::CreateImm(1)); // scale
653 LEA.addOperand(MCOperand::CreateReg(0)); // index
654 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
655 LEA.addOperand(MCOperand::CreateReg(0)); // seg
657 LEA.setOpcode(X86::LEA32r);
658 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
659 LEA.addOperand(MCOperand::CreateReg(0)); // base
660 LEA.addOperand(MCOperand::CreateImm(1)); // scale
661 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
662 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
663 LEA.addOperand(MCOperand::CreateReg(0)); // seg
665 OutStreamer.EmitInstruction(LEA);
668 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
669 OutStreamer.EmitInstruction(MCInstBuilder(X86::DATA16_PREFIX));
670 OutStreamer.EmitInstruction(MCInstBuilder(X86::REX64_PREFIX));
673 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
674 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
675 const MCSymbolRefExpr *tlsRef =
676 MCSymbolRefExpr::Create(tlsGetAddr,
677 MCSymbolRefExpr::VK_PLT,
680 OutStreamer.EmitInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
685 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
686 X86MCInstLower MCInstLowering(Mang, *MF, *this);
687 switch (MI->getOpcode()) {
688 case TargetOpcode::DBG_VALUE:
689 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
691 raw_string_ostream OS(TmpStr);
692 PrintDebugValueComment(MI, OS);
693 OutStreamer.EmitRawText(StringRef(OS.str()));
697 // Emit nothing here but a comment if we can.
698 case X86::Int_MemBarrier:
699 if (OutStreamer.hasRawTextSupport())
700 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
705 case X86::EH_RETURN64: {
706 // Lower these as normal, but add some comments.
707 unsigned Reg = MI->getOperand(0).getReg();
708 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
709 X86ATTInstPrinter::getRegisterName(Reg));
714 case X86::TAILJMPd64:
715 // Lower these as normal, but add some comments.
716 OutStreamer.AddComment("TAILCALL");
719 case X86::TLS_addr32:
720 case X86::TLS_addr64:
721 case X86::TLS_base_addr32:
722 case X86::TLS_base_addr64:
723 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
725 case X86::MOVPC32r: {
726 // This is a pseudo op for a two instruction sequence with a label, which
733 MCSymbol *PICBase = MF->getPICBaseSymbol();
734 // FIXME: We would like an efficient form for this, so we don't have to do a
735 // lot of extra uniquing.
736 OutStreamer.EmitInstruction(MCInstBuilder(X86::CALLpcrel32)
737 .addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
740 OutStreamer.EmitLabel(PICBase);
743 OutStreamer.EmitInstruction(MCInstBuilder(X86::POP32r)
744 .addReg(MI->getOperand(0).getReg()));
749 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
750 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
753 // Okay, we have something like:
754 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
756 // For this, we want to print something like:
757 // MYGLOBAL + (. - PICBASE)
758 // However, we can't generate a ".", so just emit a new label here and refer
760 MCSymbol *DotSym = OutContext.CreateTempSymbol();
761 OutStreamer.EmitLabel(DotSym);
763 // Now that we have emitted the label, lower the complex operand expression.
764 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
766 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
767 const MCExpr *PICBase =
768 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
769 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
771 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
772 DotExpr, OutContext);
774 OutStreamer.EmitInstruction(MCInstBuilder(X86::ADD32ri)
775 .addReg(MI->getOperand(0).getReg())
776 .addReg(MI->getOperand(1).getReg())
783 MCInstLowering.Lower(MI, TmpInst);
784 OutStreamer.EmitInstruction(TmpInst);