1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
26 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Mangler.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixup.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/TargetRegistry.h"
44 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
45 class X86MCInstLower {
47 const MachineFunction &MF;
48 const TargetMachine &TM;
50 X86AsmPrinter &AsmPrinter;
52 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
54 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
55 const MachineOperand &MO) const;
56 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
58 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
59 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
62 MachineModuleInfoMachO &getMachOMMI() const;
63 Mangler *getMang() const {
64 return AsmPrinter.Mang;
68 } // end anonymous namespace
70 // Emit a minimal sequence of nops spanning NumBytes bytes.
71 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
72 const MCSubtargetInfo &STI);
75 X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
76 : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
78 X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
81 X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
83 CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
84 *MF->getSubtarget().getInstrInfo(),
85 *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
88 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
89 const MCSubtargetInfo &STI) {
91 SmallString<256> Code;
92 SmallVector<MCFixup, 4> Fixups;
93 raw_svector_ostream VecOS(Code);
94 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
96 CurrentShadowSize += Code.size();
97 if (CurrentShadowSize >= RequiredShadowSize)
98 InShadow = false; // The shadow is big enough. Stop counting.
102 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
103 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
104 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
106 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
107 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
111 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
112 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
113 SMShadowTracker.count(Inst, getSubtargetInfo());
115 } // end llvm namespace
117 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
118 X86AsmPrinter &asmprinter)
119 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
120 AsmPrinter(asmprinter) {}
122 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
123 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
127 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
128 /// operand to an MCSymbol.
129 MCSymbol *X86MCInstLower::
130 GetSymbolFromOperand(const MachineOperand &MO) const {
131 const DataLayout *DL = TM.getDataLayout();
132 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
134 MCSymbol *Sym = nullptr;
135 SmallString<128> Name;
138 switch (MO.getTargetFlags()) {
139 case X86II::MO_DLLIMPORT:
140 // Handle dllimport linkage.
143 case X86II::MO_DARWIN_STUB:
146 case X86II::MO_DARWIN_NONLAZY:
147 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
148 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
149 Suffix = "$non_lazy_ptr";
154 Name += DL->getPrivateGlobalPrefix();
156 unsigned PrefixLen = Name.size();
159 const GlobalValue *GV = MO.getGlobal();
160 AsmPrinter.getNameWithPrefix(Name, GV);
161 } else if (MO.isSymbol()) {
162 if (MO.getTargetFlags() == X86II::MO_NOPREFIX)
163 Name += MO.getSymbolName();
165 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
166 } else if (MO.isMBB()) {
167 assert(Suffix.empty());
168 Sym = MO.getMBB()->getSymbol();
170 unsigned OrigLen = Name.size() - PrefixLen;
174 Sym = Ctx.getOrCreateSymbol(Name);
176 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
178 // If the target flags on the operand changes the name of the symbol, do that
179 // before we return the symbol.
180 switch (MO.getTargetFlags()) {
182 case X86II::MO_DARWIN_NONLAZY:
183 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
184 MachineModuleInfoImpl::StubValueTy &StubSym =
185 getMachOMMI().getGVStubEntry(Sym);
186 if (!StubSym.getPointer()) {
187 assert(MO.isGlobal() && "Extern symbol not handled yet");
189 MachineModuleInfoImpl::
190 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
191 !MO.getGlobal()->hasInternalLinkage());
195 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
196 MachineModuleInfoImpl::StubValueTy &StubSym =
197 getMachOMMI().getHiddenGVStubEntry(Sym);
198 if (!StubSym.getPointer()) {
199 assert(MO.isGlobal() && "Extern symbol not handled yet");
201 MachineModuleInfoImpl::
202 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
203 !MO.getGlobal()->hasInternalLinkage());
207 case X86II::MO_DARWIN_STUB: {
208 MachineModuleInfoImpl::StubValueTy &StubSym =
209 getMachOMMI().getFnStubEntry(Sym);
210 if (StubSym.getPointer())
215 MachineModuleInfoImpl::
216 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
217 !MO.getGlobal()->hasInternalLinkage());
220 MachineModuleInfoImpl::
221 StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
230 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
231 MCSymbol *Sym) const {
232 // FIXME: We would like an efficient form for this, so we don't have to do a
233 // lot of extra uniquing.
234 const MCExpr *Expr = nullptr;
235 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
237 switch (MO.getTargetFlags()) {
238 default: llvm_unreachable("Unknown target flag on GV operand");
239 case X86II::MO_NO_FLAG: // No flag.
240 // These affect the name of the symbol, not any suffix.
241 case X86II::MO_DARWIN_NONLAZY:
242 case X86II::MO_DLLIMPORT:
243 case X86II::MO_DARWIN_STUB:
244 case X86II::MO_NOPREFIX:
247 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
248 case X86II::MO_TLVP_PIC_BASE:
249 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
250 // Subtract the pic base.
251 Expr = MCBinaryExpr::createSub(Expr,
252 MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
256 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
257 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
258 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
259 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
260 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
261 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
262 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
263 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
264 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
265 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
266 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
267 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
268 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
269 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
270 case X86II::MO_PIC_BASE_OFFSET:
271 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
272 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
273 Expr = MCSymbolRefExpr::create(Sym, Ctx);
274 // Subtract the pic base.
275 Expr = MCBinaryExpr::createSub(Expr,
276 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
279 assert(MAI.doesSetDirectiveSuppressesReloc());
280 // If .set directive is supported, use it to reduce the number of
281 // relocations the assembler will generate for differences between
282 // local labels. This is only safe when the symbols are in the same
283 // section so we are restricting it to jumptable references.
284 MCSymbol *Label = Ctx.createTempSymbol();
285 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
286 Expr = MCSymbolRefExpr::create(Label, Ctx);
292 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
294 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
295 Expr = MCBinaryExpr::createAdd(Expr,
296 MCConstantExpr::create(MO.getOffset(), Ctx),
298 return MCOperand::createExpr(Expr);
302 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
303 /// a short fixed-register form.
304 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
305 unsigned ImmOp = Inst.getNumOperands() - 1;
306 assert(Inst.getOperand(0).isReg() &&
307 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
308 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
309 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
310 Inst.getNumOperands() == 2) && "Unexpected instruction!");
312 // Check whether the destination register can be fixed.
313 unsigned Reg = Inst.getOperand(0).getReg();
314 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
317 // If so, rewrite the instruction.
318 MCOperand Saved = Inst.getOperand(ImmOp);
320 Inst.setOpcode(Opcode);
321 Inst.addOperand(Saved);
324 /// \brief If a movsx instruction has a shorter encoding for the used register
325 /// simplify the instruction to use it instead.
326 static void SimplifyMOVSX(MCInst &Inst) {
327 unsigned NewOpcode = 0;
328 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
329 switch (Inst.getOpcode()) {
331 llvm_unreachable("Unexpected instruction!");
332 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
333 if (Op0 == X86::AX && Op1 == X86::AL)
334 NewOpcode = X86::CBW;
336 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
337 if (Op0 == X86::EAX && Op1 == X86::AX)
338 NewOpcode = X86::CWDE;
340 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
341 if (Op0 == X86::RAX && Op1 == X86::EAX)
342 NewOpcode = X86::CDQE;
346 if (NewOpcode != 0) {
348 Inst.setOpcode(NewOpcode);
352 /// \brief Simplify things like MOV32rm to MOV32o32a.
353 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
355 // Don't make these simplifications in 64-bit mode; other assemblers don't
356 // perform them because they make the code larger.
357 if (Printer.getSubtarget().is64Bit())
360 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
361 unsigned AddrBase = IsStore;
362 unsigned RegOp = IsStore ? 0 : 5;
363 unsigned AddrOp = AddrBase + 3;
364 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
365 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
366 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
367 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
368 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
369 (Inst.getOperand(AddrOp).isExpr() ||
370 Inst.getOperand(AddrOp).isImm()) &&
371 "Unexpected instruction!");
373 // Check whether the destination register can be fixed.
374 unsigned Reg = Inst.getOperand(RegOp).getReg();
375 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
378 // Check whether this is an absolute address.
379 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
381 bool Absolute = true;
382 if (Inst.getOperand(AddrOp).isExpr()) {
383 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
384 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
385 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
390 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
391 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
392 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
395 // If so, rewrite the instruction.
396 MCOperand Saved = Inst.getOperand(AddrOp);
397 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
399 Inst.setOpcode(Opcode);
400 Inst.addOperand(Saved);
401 Inst.addOperand(Seg);
404 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
405 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
409 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
410 const MachineOperand &MO) const {
411 switch (MO.getType()) {
414 llvm_unreachable("unknown operand type");
415 case MachineOperand::MO_Register:
416 // Ignore all implicit register operands.
419 return MCOperand::createReg(MO.getReg());
420 case MachineOperand::MO_Immediate:
421 return MCOperand::createImm(MO.getImm());
422 case MachineOperand::MO_MachineBasicBlock:
423 case MachineOperand::MO_GlobalAddress:
424 case MachineOperand::MO_ExternalSymbol:
425 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
426 case MachineOperand::MO_JumpTableIndex:
427 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
428 case MachineOperand::MO_ConstantPoolIndex:
429 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
430 case MachineOperand::MO_BlockAddress:
431 return LowerSymbolOperand(
432 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
433 case MachineOperand::MO_RegisterMask:
434 // Ignore call clobbers.
439 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
440 OutMI.setOpcode(MI->getOpcode());
442 for (const MachineOperand &MO : MI->operands())
443 if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
444 OutMI.addOperand(MaybeMCOp.getValue());
446 // Handle a few special cases to eliminate operand modifiers.
448 switch (OutMI.getOpcode()) {
453 // LEA should have a segment register, but it must be empty.
454 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
455 "Unexpected # of LEA operands");
456 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
457 "LEA has segment specified!");
461 OutMI.setOpcode(X86::MOV32ri);
464 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
465 // if one of the registers is extended, but other isn't.
467 case X86::VMOVAPDYrr:
469 case X86::VMOVAPSYrr:
471 case X86::VMOVDQAYrr:
473 case X86::VMOVDQUYrr:
475 case X86::VMOVUPDYrr:
477 case X86::VMOVUPSYrr: {
478 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
479 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
481 switch (OutMI.getOpcode()) {
482 default: llvm_unreachable("Invalid opcode");
483 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
484 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
485 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
486 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
487 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
488 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
489 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
490 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
491 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
492 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
493 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
494 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
496 OutMI.setOpcode(NewOpc);
501 case X86::VMOVSSrr: {
502 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
503 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
505 switch (OutMI.getOpcode()) {
506 default: llvm_unreachable("Invalid opcode");
507 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
508 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
510 OutMI.setOpcode(NewOpc);
515 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
516 // inputs modeled as normal uses instead of implicit uses. As such, truncate
517 // off all but the first operand (the callee). FIXME: Change isel.
518 case X86::TAILJMPr64:
519 case X86::TAILJMPr64_REX:
521 case X86::CALL64pcrel32: {
522 unsigned Opcode = OutMI.getOpcode();
523 MCOperand Saved = OutMI.getOperand(0);
525 OutMI.setOpcode(Opcode);
526 OutMI.addOperand(Saved);
531 case X86::EH_RETURN64: {
533 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
537 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
540 case X86::TAILJMPd64: {
542 switch (OutMI.getOpcode()) {
543 default: llvm_unreachable("Invalid opcode");
544 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
546 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
549 MCOperand Saved = OutMI.getOperand(0);
551 OutMI.setOpcode(Opcode);
552 OutMI.addOperand(Saved);
560 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
561 if (!AsmPrinter.getSubtarget().is64Bit()) {
563 switch (OutMI.getOpcode()) {
564 default: llvm_unreachable("Invalid opcode");
565 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
566 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
567 case X86::INC16r: Opcode = X86::INC16r_alt; break;
568 case X86::INC32r: Opcode = X86::INC32r_alt; break;
570 OutMI.setOpcode(Opcode);
574 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
575 // this with an ugly goto in case the resultant OR uses EAX and needs the
577 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
578 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
579 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
580 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
581 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
582 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
583 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
584 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
585 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
587 // Atomic load and store require a separate pseudo-inst because Acquire
588 // implies mayStore and Release implies mayLoad; fix these to regular MOV
590 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
591 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
592 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
593 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
594 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
595 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
596 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
597 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
598 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
599 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
600 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
601 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
602 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
603 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
604 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
605 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
606 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
607 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
608 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
609 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
610 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
611 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
612 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
613 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
614 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
615 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
616 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
617 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
618 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
619 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
620 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
621 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
623 // We don't currently select the correct instruction form for instructions
624 // which have a short %eax, etc. form. Handle this by custom lowering, for
627 // Note, we are currently not handling the following instructions:
628 // MOV64ao8, MOV64o8a
629 // XCHG16ar, XCHG32ar, XCHG64ar
630 case X86::MOV8mr_NOREX:
631 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
632 case X86::MOV8rm_NOREX:
633 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
634 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
635 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
636 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
637 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
639 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
640 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
641 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
642 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
643 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
644 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
645 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
646 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
647 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
648 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
649 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
650 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
651 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
652 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
653 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
654 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
655 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
656 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
657 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
658 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
659 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
660 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
661 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
662 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
663 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
664 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
665 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
666 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
667 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
668 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
669 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
670 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
671 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
672 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
673 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
674 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
676 // Try to shrink some forms of movsx.
677 case X86::MOVSX16rr8:
678 case X86::MOVSX32rr16:
679 case X86::MOVSX64rr32:
680 SimplifyMOVSX(OutMI);
685 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
686 const MachineInstr &MI) {
688 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
689 MI.getOpcode() == X86::TLS_base_addr64;
691 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
693 MCContext &context = OutStreamer->getContext();
696 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
698 MCSymbolRefExpr::VariantKind SRVK;
699 switch (MI.getOpcode()) {
700 case X86::TLS_addr32:
701 case X86::TLS_addr64:
702 SRVK = MCSymbolRefExpr::VK_TLSGD;
704 case X86::TLS_base_addr32:
705 SRVK = MCSymbolRefExpr::VK_TLSLDM;
707 case X86::TLS_base_addr64:
708 SRVK = MCSymbolRefExpr::VK_TLSLD;
711 llvm_unreachable("unexpected opcode");
714 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
715 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
719 LEA.setOpcode(X86::LEA64r);
720 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
721 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
722 LEA.addOperand(MCOperand::createImm(1)); // scale
723 LEA.addOperand(MCOperand::createReg(0)); // index
724 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
725 LEA.addOperand(MCOperand::createReg(0)); // seg
726 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
727 LEA.setOpcode(X86::LEA32r);
728 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
729 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
730 LEA.addOperand(MCOperand::createImm(1)); // scale
731 LEA.addOperand(MCOperand::createReg(0)); // index
732 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
733 LEA.addOperand(MCOperand::createReg(0)); // seg
735 LEA.setOpcode(X86::LEA32r);
736 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
737 LEA.addOperand(MCOperand::createReg(0)); // base
738 LEA.addOperand(MCOperand::createImm(1)); // scale
739 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
740 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
741 LEA.addOperand(MCOperand::createReg(0)); // seg
743 EmitAndCountInstruction(LEA);
746 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
747 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
748 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
751 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
752 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
753 const MCSymbolRefExpr *tlsRef =
754 MCSymbolRefExpr::create(tlsGetAddr,
755 MCSymbolRefExpr::VK_PLT,
758 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
763 /// \brief Emit the optimal amount of multi-byte nops on X86.
764 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
765 // This works only for 64bit. For 32bit we have to do additional checking if
766 // the CPU supports multi-byte nops.
767 assert(Is64Bit && "EmitNops only supports X86-64");
769 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
770 Opc = IndexReg = Displacement = SegmentReg = 0;
771 BaseReg = X86::RAX; ScaleVal = 1;
773 case 0: llvm_unreachable("Zero nops?"); break;
774 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
775 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
776 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
777 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
778 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
779 IndexReg = X86::RAX; break;
780 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
781 IndexReg = X86::RAX; break;
782 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
783 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
784 IndexReg = X86::RAX; break;
785 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
786 IndexReg = X86::RAX; break;
787 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
788 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
791 unsigned NumPrefixes = std::min(NumBytes, 5U);
792 NumBytes -= NumPrefixes;
793 for (unsigned i = 0; i != NumPrefixes; ++i)
794 OS.EmitBytes("\x66");
797 default: llvm_unreachable("Unexpected opcode"); break;
799 OS.EmitInstruction(MCInstBuilder(Opc), STI);
802 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
806 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
807 .addImm(ScaleVal).addReg(IndexReg)
808 .addImm(Displacement).addReg(SegmentReg), STI);
811 } // while (NumBytes)
814 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
815 X86MCInstLower &MCIL) {
816 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
818 StatepointOpers SOpers(&MI);
819 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
820 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
823 // Lower call target and choose correct opcode
824 const MachineOperand &CallTarget = SOpers.getCallTarget();
825 MCOperand CallTargetMCOp;
827 switch (CallTarget.getType()) {
828 case MachineOperand::MO_GlobalAddress:
829 case MachineOperand::MO_ExternalSymbol:
830 CallTargetMCOp = MCIL.LowerSymbolOperand(
831 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
832 CallOpcode = X86::CALL64pcrel32;
833 // Currently, we only support relative addressing with statepoints.
834 // Otherwise, we'll need a scratch register to hold the target
835 // address. You'll fail asserts during load & relocation if this
836 // symbol is to far away. (TODO: support non-relative addressing)
838 case MachineOperand::MO_Immediate:
839 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
840 CallOpcode = X86::CALL64pcrel32;
841 // Currently, we only support relative addressing with statepoints.
842 // Otherwise, we'll need a scratch register to hold the target
843 // immediate. You'll fail asserts during load & relocation if this
844 // address is to far away. (TODO: support non-relative addressing)
846 case MachineOperand::MO_Register:
847 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
848 CallOpcode = X86::CALL64r;
851 llvm_unreachable("Unsupported operand type in statepoint call target");
857 CallInst.setOpcode(CallOpcode);
858 CallInst.addOperand(CallTargetMCOp);
859 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
862 // Record our statepoint node in the same section used by STACKMAP
864 SM.recordStatepoint(MI);
868 // Lower a stackmap of the form:
869 // <id>, <shadowBytes>, ...
870 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
871 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
872 SM.recordStackMap(MI);
873 unsigned NumShadowBytes = MI.getOperand(1).getImm();
874 SMShadowTracker.reset(NumShadowBytes);
877 // Lower a patchpoint of the form:
878 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
879 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
880 X86MCInstLower &MCIL) {
881 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
883 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
885 SM.recordPatchPoint(MI);
887 PatchPointOpers opers(&MI);
888 unsigned ScratchIdx = opers.getNextScratchIdx();
889 unsigned EncodedBytes = 0;
890 const MachineOperand &CalleeMO =
891 opers.getMetaOper(PatchPointOpers::TargetPos);
893 // Check for null target. If target is non-null (i.e. is non-zero or is
894 // symbolic) then emit a call.
895 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
896 MCOperand CalleeMCOp;
897 switch (CalleeMO.getType()) {
899 /// FIXME: Add a verifier check for bad callee types.
900 llvm_unreachable("Unrecognized callee operand type.");
901 case MachineOperand::MO_Immediate:
902 if (CalleeMO.getImm())
903 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
905 case MachineOperand::MO_ExternalSymbol:
906 case MachineOperand::MO_GlobalAddress:
908 MCIL.LowerSymbolOperand(CalleeMO,
909 MCIL.GetSymbolFromOperand(CalleeMO));
913 // Emit MOV to materialize the target address and the CALL to target.
914 // This is encoded with 12-13 bytes, depending on which register is used.
915 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
916 if (X86II::isX86_64ExtendedReg(ScratchReg))
921 EmitAndCountInstruction(
922 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
923 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
927 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
928 assert(NumBytes >= EncodedBytes &&
929 "Patchpoint can't request size less than the length of a call.");
931 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
935 // Returns instruction preceding MBBI in MachineFunction.
936 // If MBBI is the first instruction of the first basic block, returns null.
937 static MachineBasicBlock::const_iterator
938 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
939 const MachineBasicBlock *MBB = MBBI->getParent();
940 while (MBBI == MBB->begin()) {
941 if (MBB == MBB->getParent()->begin())
943 MBB = MBB->getPrevNode();
949 static const Constant *getConstantFromPool(const MachineInstr &MI,
950 const MachineOperand &Op) {
954 ArrayRef<MachineConstantPoolEntry> Constants =
955 MI.getParent()->getParent()->getConstantPool()->getConstants();
956 const MachineConstantPoolEntry &ConstantEntry =
957 Constants[Op.getIndex()];
959 // Bail if this is a machine constant pool entry, we won't be able to dig out
961 if (ConstantEntry.isMachineConstantPoolEntry())
964 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
965 assert((!C || ConstantEntry.getType() == C->getType()) &&
966 "Expected a constant of the same type!");
970 static std::string getShuffleComment(const MachineOperand &DstOp,
971 const MachineOperand &SrcOp,
972 ArrayRef<int> Mask) {
975 // Compute the name for a register. This is really goofy because we have
976 // multiple instruction printers that could (in theory) use different
977 // names. Fortunately most people use the ATT style (outside of Windows)
978 // and they actually agree on register naming here. Ultimately, this is
979 // a comment, and so its OK if it isn't perfect.
980 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
981 return X86ATTInstPrinter::getRegisterName(RegNum);
984 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
985 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
987 raw_string_ostream CS(Comment);
988 CS << DstName << " = ";
989 bool NeedComma = false;
992 // Wrap up any prior entry...
993 if (M == SM_SentinelZero && InSrc) {
1002 // Print this shuffle...
1003 if (M == SM_SentinelZero) {
1008 CS << SrcName << "[";
1010 if (M == SM_SentinelUndef)
1023 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1024 X86MCInstLower MCInstLowering(*MF, *this);
1025 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1027 switch (MI->getOpcode()) {
1028 case TargetOpcode::DBG_VALUE:
1029 llvm_unreachable("Should be handled target independently");
1031 // Emit nothing here but a comment if we can.
1032 case X86::Int_MemBarrier:
1033 OutStreamer->emitRawComment("MEMBARRIER");
1037 case X86::EH_RETURN:
1038 case X86::EH_RETURN64: {
1039 // Lower these as normal, but add some comments.
1040 unsigned Reg = MI->getOperand(0).getReg();
1041 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1042 X86ATTInstPrinter::getRegisterName(Reg));
1048 case X86::TAILJMPr64:
1049 case X86::TAILJMPm64:
1050 case X86::TAILJMPd64:
1051 case X86::TAILJMPr64_REX:
1052 case X86::TAILJMPm64_REX:
1053 case X86::TAILJMPd64_REX:
1054 // Lower these as normal, but add some comments.
1055 OutStreamer->AddComment("TAILCALL");
1058 case X86::TLS_addr32:
1059 case X86::TLS_addr64:
1060 case X86::TLS_base_addr32:
1061 case X86::TLS_base_addr64:
1062 return LowerTlsAddr(MCInstLowering, *MI);
1064 case X86::MOVPC32r: {
1065 // This is a pseudo op for a two instruction sequence with a label, which
1072 MCSymbol *PICBase = MF->getPICBaseSymbol();
1073 // FIXME: We would like an efficient form for this, so we don't have to do a
1074 // lot of extra uniquing.
1075 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1076 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1079 OutStreamer->EmitLabel(PICBase);
1082 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1083 .addReg(MI->getOperand(0).getReg()));
1087 case X86::ADD32ri: {
1088 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1089 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1092 // Okay, we have something like:
1093 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1095 // For this, we want to print something like:
1096 // MYGLOBAL + (. - PICBASE)
1097 // However, we can't generate a ".", so just emit a new label here and refer
1099 MCSymbol *DotSym = OutContext.createTempSymbol();
1100 OutStreamer->EmitLabel(DotSym);
1102 // Now that we have emitted the label, lower the complex operand expression.
1103 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1105 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1106 const MCExpr *PICBase =
1107 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1108 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1110 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
1111 DotExpr, OutContext);
1113 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1114 .addReg(MI->getOperand(0).getReg())
1115 .addReg(MI->getOperand(1).getReg())
1119 case TargetOpcode::STATEPOINT:
1120 return LowerSTATEPOINT(*MI, MCInstLowering);
1122 case TargetOpcode::STACKMAP:
1123 return LowerSTACKMAP(*MI);
1125 case TargetOpcode::PATCHPOINT:
1126 return LowerPATCHPOINT(*MI, MCInstLowering);
1128 case X86::MORESTACK_RET:
1129 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1132 case X86::MORESTACK_RET_RESTORE_R10:
1133 // Return, then restore R10.
1134 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1135 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1140 case X86::SEH_PushReg:
1141 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1144 case X86::SEH_SaveReg:
1145 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1146 MI->getOperand(1).getImm());
1149 case X86::SEH_SaveXMM:
1150 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1151 MI->getOperand(1).getImm());
1154 case X86::SEH_StackAlloc:
1155 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1158 case X86::SEH_SetFrame:
1159 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1160 MI->getOperand(1).getImm());
1163 case X86::SEH_PushFrame:
1164 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1167 case X86::SEH_EndPrologue:
1168 OutStreamer->EmitWinCFIEndProlog();
1171 case X86::SEH_Epilogue: {
1172 MachineBasicBlock::const_iterator MBBI(MI);
1173 // Check if preceded by a call and emit nop if so.
1174 for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1175 // Conservatively assume that pseudo instructions don't emit code and keep
1176 // looking for a call. We may emit an unnecessary nop in some cases.
1177 if (!MBBI->isPseudo()) {
1179 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1186 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1187 // a constant shuffle mask. We won't be able to do this at the MC layer
1188 // because the mask isn't an immediate.
1190 case X86::VPSHUFBrm:
1191 case X86::VPSHUFBYrm: {
1192 if (!OutStreamer->isVerboseAsm())
1194 assert(MI->getNumOperands() > 5 &&
1195 "We should always have at least 5 operands!");
1196 const MachineOperand &DstOp = MI->getOperand(0);
1197 const MachineOperand &SrcOp = MI->getOperand(1);
1198 const MachineOperand &MaskOp = MI->getOperand(5);
1200 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1201 SmallVector<int, 16> Mask;
1202 DecodePSHUFBMask(C, Mask);
1204 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1208 case X86::VPERMILPSrm:
1209 case X86::VPERMILPDrm:
1210 case X86::VPERMILPSYrm:
1211 case X86::VPERMILPDYrm: {
1212 if (!OutStreamer->isVerboseAsm())
1214 assert(MI->getNumOperands() > 5 &&
1215 "We should always have at least 5 operands!");
1216 const MachineOperand &DstOp = MI->getOperand(0);
1217 const MachineOperand &SrcOp = MI->getOperand(1);
1218 const MachineOperand &MaskOp = MI->getOperand(5);
1220 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1221 SmallVector<int, 16> Mask;
1222 DecodeVPERMILPMask(C, Mask);
1224 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1229 // For loads from a constant pool to a vector register, print the constant
1232 case X86::VMOVAPDrm:
1233 case X86::VMOVAPDYrm:
1235 case X86::VMOVUPDrm:
1236 case X86::VMOVUPDYrm:
1238 case X86::VMOVAPSrm:
1239 case X86::VMOVAPSYrm:
1241 case X86::VMOVUPSrm:
1242 case X86::VMOVUPSYrm:
1244 case X86::VMOVDQArm:
1245 case X86::VMOVDQAYrm:
1247 case X86::VMOVDQUrm:
1248 case X86::VMOVDQUYrm:
1249 if (!OutStreamer->isVerboseAsm())
1251 if (MI->getNumOperands() > 4)
1252 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1253 std::string Comment;
1254 raw_string_ostream CS(Comment);
1255 const MachineOperand &DstOp = MI->getOperand(0);
1256 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1257 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1259 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1262 if (CDS->getElementType()->isIntegerTy())
1263 CS << CDS->getElementAsInteger(i);
1264 else if (CDS->getElementType()->isFloatTy())
1265 CS << CDS->getElementAsFloat(i);
1266 else if (CDS->getElementType()->isDoubleTy())
1267 CS << CDS->getElementAsDouble(i);
1272 OutStreamer->AddComment(CS.str());
1273 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1275 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1278 Constant *COp = CV->getOperand(i);
1279 if (isa<UndefValue>(COp)) {
1281 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1282 CS << CI->getZExtValue();
1283 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1284 SmallString<32> Str;
1285 CF->getValueAPF().toString(Str);
1292 OutStreamer->AddComment(CS.str());
1299 MCInstLowering.Lower(MI, TmpInst);
1301 // Stackmap shadows cannot include branch targets, so we can count the bytes
1302 // in a call towards the shadow, but must ensure that the no thread returns
1303 // in to the stackmap shadow. The only way to achieve this is if the call
1304 // is at the end of the shadow.
1306 // Count then size of the call towards the shadow
1307 SMShadowTracker.count(TmpInst, getSubtargetInfo());
1308 // Then flush the shadow so that we fill with nops before the call, not
1310 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1311 // Then emit the call
1312 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1316 EmitAndCountInstruction(TmpInst);