1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86COFFMachineModuleInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "llvm/Type.h"
19 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Target/Mangler.h"
27 #include "llvm/Support/FormattedStream.h"
28 #include "llvm/ADT/SmallString.h"
33 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
34 class X86MCInstLower {
37 const MachineFunction &MF;
38 const TargetMachine &TM;
40 X86AsmPrinter &AsmPrinter;
42 X86MCInstLower(Mangler *mang, const MachineFunction &MF,
43 X86AsmPrinter &asmprinter);
45 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
47 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
48 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
51 MachineModuleInfoMachO &getMachOMMI() const;
54 } // end anonymous namespace
56 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
57 X86AsmPrinter &asmprinter)
58 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
59 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
61 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
62 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
66 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
67 /// operand to an MCSymbol.
68 MCSymbol *X86MCInstLower::
69 GetSymbolFromOperand(const MachineOperand &MO) const {
70 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
72 SmallString<128> Name;
75 const GlobalValue *GV = MO.getGlobal();
76 bool isImplicitlyPrivate = false;
77 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
78 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
79 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
80 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
81 isImplicitlyPrivate = true;
83 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
84 } else if (MO.isSymbol()) {
85 Name += MAI.getGlobalPrefix();
86 Name += MO.getSymbolName();
87 } else if (MO.isMBB()) {
88 Name += MO.getMBB()->getSymbol()->getName();
91 // If the target flags on the operand changes the name of the symbol, do that
92 // before we return the symbol.
93 switch (MO.getTargetFlags()) {
95 case X86II::MO_DLLIMPORT: {
96 // Handle dllimport linkage.
97 const char *Prefix = "__imp_";
98 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
101 case X86II::MO_DARWIN_NONLAZY:
102 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
103 Name += "$non_lazy_ptr";
104 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
106 MachineModuleInfoImpl::StubValueTy &StubSym =
107 getMachOMMI().getGVStubEntry(Sym);
108 if (StubSym.getPointer() == 0) {
109 assert(MO.isGlobal() && "Extern symbol not handled yet");
111 MachineModuleInfoImpl::
112 StubValueTy(Mang->getSymbol(MO.getGlobal()),
113 !MO.getGlobal()->hasInternalLinkage());
117 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
118 Name += "$non_lazy_ptr";
119 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
120 MachineModuleInfoImpl::StubValueTy &StubSym =
121 getMachOMMI().getHiddenGVStubEntry(Sym);
122 if (StubSym.getPointer() == 0) {
123 assert(MO.isGlobal() && "Extern symbol not handled yet");
125 MachineModuleInfoImpl::
126 StubValueTy(Mang->getSymbol(MO.getGlobal()),
127 !MO.getGlobal()->hasInternalLinkage());
131 case X86II::MO_DARWIN_STUB: {
133 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
134 MachineModuleInfoImpl::StubValueTy &StubSym =
135 getMachOMMI().getFnStubEntry(Sym);
136 if (StubSym.getPointer())
141 MachineModuleInfoImpl::
142 StubValueTy(Mang->getSymbol(MO.getGlobal()),
143 !MO.getGlobal()->hasInternalLinkage());
145 Name.erase(Name.end()-5, Name.end());
147 MachineModuleInfoImpl::
148 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
154 return Ctx.GetOrCreateSymbol(Name.str());
157 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
158 MCSymbol *Sym) const {
159 // FIXME: We would like an efficient form for this, so we don't have to do a
160 // lot of extra uniquing.
161 const MCExpr *Expr = 0;
162 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
164 switch (MO.getTargetFlags()) {
165 default: llvm_unreachable("Unknown target flag on GV operand");
166 case X86II::MO_NO_FLAG: // No flag.
167 // These affect the name of the symbol, not any suffix.
168 case X86II::MO_DARWIN_NONLAZY:
169 case X86II::MO_DLLIMPORT:
170 case X86II::MO_DARWIN_STUB:
173 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
174 case X86II::MO_TLVP_PIC_BASE:
175 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
176 // Subtract the pic base.
177 Expr = MCBinaryExpr::CreateSub(Expr,
178 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
182 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
183 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
184 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
185 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
186 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
187 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
188 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
189 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
190 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
191 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
192 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
193 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
194 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
195 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
196 case X86II::MO_PIC_BASE_OFFSET:
197 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
198 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
199 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
200 // Subtract the pic base.
201 Expr = MCBinaryExpr::CreateSub(Expr,
202 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
204 if (MO.isJTI() && MAI.hasSetDirective()) {
205 // If .set directive is supported, use it to reduce the number of
206 // relocations the assembler will generate for differences between
207 // local labels. This is only safe when the symbols are in the same
208 // section so we are restricting it to jumptable references.
209 MCSymbol *Label = Ctx.CreateTempSymbol();
210 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
211 Expr = MCSymbolRefExpr::Create(Label, Ctx);
217 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
219 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
220 Expr = MCBinaryExpr::CreateAdd(Expr,
221 MCConstantExpr::Create(MO.getOffset(), Ctx),
223 return MCOperand::CreateExpr(Expr);
228 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
229 // Convert registers in the addr mode according to subreg32.
230 unsigned Reg = MI->getOperand(OpNo).getReg();
232 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
235 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
236 // Convert registers in the addr mode according to subreg64.
237 for (unsigned i = 0; i != 4; ++i) {
238 if (!MI->getOperand(OpNo+i).isReg()) continue;
240 unsigned Reg = MI->getOperand(OpNo+i).getReg();
241 if (Reg == 0) continue;
243 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
247 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
248 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
249 OutMI.setOpcode(NewOpc);
250 lower_subreg32(&OutMI, 0);
252 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
253 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
254 OutMI.setOpcode(NewOpc);
255 OutMI.addOperand(OutMI.getOperand(0));
256 OutMI.addOperand(OutMI.getOperand(0));
259 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
260 /// a short fixed-register form.
261 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
262 unsigned ImmOp = Inst.getNumOperands() - 1;
263 assert(Inst.getOperand(0).isReg() &&
264 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
265 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
266 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
267 Inst.getNumOperands() == 2) && "Unexpected instruction!");
269 // Check whether the destination register can be fixed.
270 unsigned Reg = Inst.getOperand(0).getReg();
271 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
274 // If so, rewrite the instruction.
275 MCOperand Saved = Inst.getOperand(ImmOp);
277 Inst.setOpcode(Opcode);
278 Inst.addOperand(Saved);
281 /// \brief Simplify things like MOV32rm to MOV32o32a.
282 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
284 // Don't make these simplifications in 64-bit mode; other assemblers don't
285 // perform them because they make the code larger.
286 if (Printer.getSubtarget().is64Bit())
289 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
290 unsigned AddrBase = IsStore;
291 unsigned RegOp = IsStore ? 0 : 5;
292 unsigned AddrOp = AddrBase + 3;
293 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
294 Inst.getOperand(AddrBase + 0).isReg() && // base
295 Inst.getOperand(AddrBase + 1).isImm() && // scale
296 Inst.getOperand(AddrBase + 2).isReg() && // index register
297 (Inst.getOperand(AddrOp).isExpr() || // address
298 Inst.getOperand(AddrOp).isImm())&&
299 Inst.getOperand(AddrBase + 4).isReg() && // segment
300 "Unexpected instruction!");
302 // Check whether the destination register can be fixed.
303 unsigned Reg = Inst.getOperand(RegOp).getReg();
304 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
307 // Check whether this is an absolute address.
308 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
310 bool Absolute = true;
311 if (Inst.getOperand(AddrOp).isExpr()) {
312 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
313 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
314 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
319 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
320 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
321 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
322 Inst.getOperand(AddrBase + 1).getImm() != 1))
325 // If so, rewrite the instruction.
326 MCOperand Saved = Inst.getOperand(AddrOp);
328 Inst.setOpcode(Opcode);
329 Inst.addOperand(Saved);
332 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
333 OutMI.setOpcode(MI->getOpcode());
335 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
336 const MachineOperand &MO = MI->getOperand(i);
339 switch (MO.getType()) {
342 llvm_unreachable("unknown operand type");
343 case MachineOperand::MO_Register:
344 // Ignore all implicit register operands.
345 if (MO.isImplicit()) continue;
346 MCOp = MCOperand::CreateReg(MO.getReg());
348 case MachineOperand::MO_Immediate:
349 MCOp = MCOperand::CreateImm(MO.getImm());
351 case MachineOperand::MO_MachineBasicBlock:
352 case MachineOperand::MO_GlobalAddress:
353 case MachineOperand::MO_ExternalSymbol:
354 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
356 case MachineOperand::MO_JumpTableIndex:
357 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
359 case MachineOperand::MO_ConstantPoolIndex:
360 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
362 case MachineOperand::MO_BlockAddress:
363 MCOp = LowerSymbolOperand(MO,
364 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
366 case MachineOperand::MO_RegisterMask:
367 // Ignore call clobbers.
371 OutMI.addOperand(MCOp);
374 // Handle a few special cases to eliminate operand modifiers.
376 switch (OutMI.getOpcode()) {
377 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
378 lower_lea64_32mem(&OutMI, 1);
383 // LEA should have a segment register, but it must be empty.
384 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
385 "Unexpected # of LEA operands");
386 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
387 "LEA has segment specified!");
389 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
390 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
391 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
392 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
393 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
394 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
395 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
396 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
397 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
400 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
401 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
404 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
405 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
408 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
409 // inputs modeled as normal uses instead of implicit uses. As such, truncate
410 // off all but the first operand (the callee). FIXME: Change isel.
411 case X86::TAILJMPr64:
413 case X86::CALL64pcrel32: {
414 unsigned Opcode = OutMI.getOpcode();
415 MCOperand Saved = OutMI.getOperand(0);
417 OutMI.setOpcode(Opcode);
418 OutMI.addOperand(Saved);
423 case X86::EH_RETURN64: {
425 OutMI.setOpcode(X86::RET);
429 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
432 case X86::TAILJMPd64: {
434 switch (OutMI.getOpcode()) {
435 default: llvm_unreachable("Invalid opcode");
436 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
438 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
441 MCOperand Saved = OutMI.getOperand(0);
443 OutMI.setOpcode(Opcode);
444 OutMI.addOperand(Saved);
448 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
449 // this with an ugly goto in case the resultant OR uses EAX and needs the
451 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
452 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
453 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
454 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
455 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
456 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
457 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
458 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
459 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
461 // The assembler backend wants to see branches in their small form and relax
462 // them to their large form. The JIT can only handle the large form because
463 // it does not do relaxation. For now, translate the large form to the
465 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
466 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
467 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
468 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
469 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
470 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
471 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
472 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
473 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
474 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
475 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
476 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
477 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
478 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
479 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
480 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
481 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
483 // Atomic load and store require a separate pseudo-inst because Acquire
484 // implies mayStore and Release implies mayLoad; fix these to regular MOV
486 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
487 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
488 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
489 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
490 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
491 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
492 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
493 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
495 // We don't currently select the correct instruction form for instructions
496 // which have a short %eax, etc. form. Handle this by custom lowering, for
499 // Note, we are currently not handling the following instructions:
500 // MOV64ao8, MOV64o8a
501 // XCHG16ar, XCHG32ar, XCHG64ar
502 case X86::MOV8mr_NOREX:
503 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
504 case X86::MOV8rm_NOREX:
505 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
506 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
507 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
508 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
509 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
511 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
512 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
513 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
514 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
515 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
516 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
517 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
518 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
519 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
520 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
521 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
522 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
523 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
524 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
525 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
526 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
527 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
528 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
529 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
530 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
531 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
532 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
533 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
534 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
535 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
536 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
537 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
538 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
539 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
540 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
541 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
542 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
543 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
544 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
545 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
546 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
548 case X86::MORESTACK_RET:
549 OutMI.setOpcode(X86::RET);
552 case X86::MORESTACK_RET_RESTORE_R10: {
555 OutMI.setOpcode(X86::MOV64rr);
556 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
557 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
559 retInst.setOpcode(X86::RET);
560 AsmPrinter.OutStreamer.EmitInstruction(retInst);
566 static void LowerTlsAddr(MCStreamer &OutStreamer,
567 X86MCInstLower &MCInstLowering,
568 const MachineInstr &MI) {
570 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
571 MI.getOpcode() == X86::TLS_base_addr64;
573 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
575 MCContext &context = OutStreamer.getContext();
579 prefix.setOpcode(X86::DATA16_PREFIX);
580 OutStreamer.EmitInstruction(prefix);
583 MCSymbolRefExpr::VariantKind SRVK;
584 switch (MI.getOpcode()) {
585 case X86::TLS_addr32:
586 case X86::TLS_addr64:
587 SRVK = MCSymbolRefExpr::VK_TLSGD;
589 case X86::TLS_base_addr32:
590 SRVK = MCSymbolRefExpr::VK_TLSLDM;
592 case X86::TLS_base_addr64:
593 SRVK = MCSymbolRefExpr::VK_TLSLD;
596 llvm_unreachable("unexpected opcode");
599 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
600 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
604 LEA.setOpcode(X86::LEA64r);
605 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
606 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
607 LEA.addOperand(MCOperand::CreateImm(1)); // scale
608 LEA.addOperand(MCOperand::CreateReg(0)); // index
609 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
610 LEA.addOperand(MCOperand::CreateReg(0)); // seg
611 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
612 LEA.setOpcode(X86::LEA32r);
613 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
614 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
615 LEA.addOperand(MCOperand::CreateImm(1)); // scale
616 LEA.addOperand(MCOperand::CreateReg(0)); // index
617 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
618 LEA.addOperand(MCOperand::CreateReg(0)); // seg
620 LEA.setOpcode(X86::LEA32r);
621 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
622 LEA.addOperand(MCOperand::CreateReg(0)); // base
623 LEA.addOperand(MCOperand::CreateImm(1)); // scale
624 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
625 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
626 LEA.addOperand(MCOperand::CreateReg(0)); // seg
628 OutStreamer.EmitInstruction(LEA);
632 prefix.setOpcode(X86::DATA16_PREFIX);
633 OutStreamer.EmitInstruction(prefix);
634 prefix.setOpcode(X86::DATA16_PREFIX);
635 OutStreamer.EmitInstruction(prefix);
636 prefix.setOpcode(X86::REX64_PREFIX);
637 OutStreamer.EmitInstruction(prefix);
642 call.setOpcode(X86::CALL64pcrel32);
644 call.setOpcode(X86::CALLpcrel32);
645 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
646 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
647 const MCSymbolRefExpr *tlsRef =
648 MCSymbolRefExpr::Create(tlsGetAddr,
649 MCSymbolRefExpr::VK_PLT,
652 call.addOperand(MCOperand::CreateExpr(tlsRef));
653 OutStreamer.EmitInstruction(call);
656 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
657 X86MCInstLower MCInstLowering(Mang, *MF, *this);
658 switch (MI->getOpcode()) {
659 case TargetOpcode::DBG_VALUE:
660 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
662 raw_string_ostream OS(TmpStr);
663 PrintDebugValueComment(MI, OS);
664 OutStreamer.EmitRawText(StringRef(OS.str()));
668 // Emit nothing here but a comment if we can.
669 case X86::Int_MemBarrier:
670 if (OutStreamer.hasRawTextSupport())
671 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
676 case X86::EH_RETURN64: {
677 // Lower these as normal, but add some comments.
678 unsigned Reg = MI->getOperand(0).getReg();
679 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
680 X86ATTInstPrinter::getRegisterName(Reg));
685 case X86::TAILJMPd64:
686 // Lower these as normal, but add some comments.
687 OutStreamer.AddComment("TAILCALL");
690 case X86::TLS_addr32:
691 case X86::TLS_addr64:
692 case X86::TLS_base_addr32:
693 case X86::TLS_base_addr64:
694 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
696 case X86::MOVPC32r: {
698 // This is a pseudo op for a two instruction sequence with a label, which
705 MCSymbol *PICBase = MF->getPICBaseSymbol();
706 TmpInst.setOpcode(X86::CALLpcrel32);
707 // FIXME: We would like an efficient form for this, so we don't have to do a
708 // lot of extra uniquing.
709 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
711 OutStreamer.EmitInstruction(TmpInst);
714 OutStreamer.EmitLabel(PICBase);
717 TmpInst.setOpcode(X86::POP32r);
718 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
719 OutStreamer.EmitInstruction(TmpInst);
724 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
725 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
728 // Okay, we have something like:
729 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
731 // For this, we want to print something like:
732 // MYGLOBAL + (. - PICBASE)
733 // However, we can't generate a ".", so just emit a new label here and refer
735 MCSymbol *DotSym = OutContext.CreateTempSymbol();
736 OutStreamer.EmitLabel(DotSym);
738 // Now that we have emitted the label, lower the complex operand expression.
739 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
741 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
742 const MCExpr *PICBase =
743 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
744 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
746 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
747 DotExpr, OutContext);
750 TmpInst.setOpcode(X86::ADD32ri);
751 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
752 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
753 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
754 OutStreamer.EmitInstruction(TmpInst);
760 MCInstLowering.Lower(MI, TmpInst);
761 OutStreamer.EmitInstruction(TmpInst);