1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
26 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Mangler.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixup.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/TargetRegistry.h"
44 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
45 class X86MCInstLower {
47 const MachineFunction &MF;
48 const TargetMachine &TM;
50 X86AsmPrinter &AsmPrinter;
52 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
54 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
55 const MachineOperand &MO) const;
56 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
58 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
59 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
62 MachineModuleInfoMachO &getMachOMMI() const;
63 Mangler *getMang() const {
64 return AsmPrinter.Mang;
68 } // end anonymous namespace
70 // Emit a minimal sequence of nops spanning NumBytes bytes.
71 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
72 const MCSubtargetInfo &STI);
75 X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
76 : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
78 X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
81 X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
83 CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
84 *MF->getSubtarget().getInstrInfo(),
85 *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
88 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
89 const MCSubtargetInfo &STI) {
91 SmallString<256> Code;
92 SmallVector<MCFixup, 4> Fixups;
93 raw_svector_ostream VecOS(Code);
94 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
95 CurrentShadowSize += Code.size();
96 if (CurrentShadowSize >= RequiredShadowSize)
97 InShadow = false; // The shadow is big enough. Stop counting.
101 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
102 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
103 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
105 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
106 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
110 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
111 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
112 SMShadowTracker.count(Inst, getSubtargetInfo());
114 } // end llvm namespace
116 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
117 X86AsmPrinter &asmprinter)
118 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
119 AsmPrinter(asmprinter) {}
121 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
122 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
126 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
127 /// operand to an MCSymbol.
128 MCSymbol *X86MCInstLower::
129 GetSymbolFromOperand(const MachineOperand &MO) const {
130 const DataLayout &DL = MF.getDataLayout();
131 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
133 MCSymbol *Sym = nullptr;
134 SmallString<128> Name;
137 switch (MO.getTargetFlags()) {
138 case X86II::MO_DLLIMPORT:
139 // Handle dllimport linkage.
142 case X86II::MO_DARWIN_STUB:
145 case X86II::MO_DARWIN_NONLAZY:
146 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
147 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
148 Suffix = "$non_lazy_ptr";
153 Name += DL.getPrivateGlobalPrefix();
155 unsigned PrefixLen = Name.size();
158 const GlobalValue *GV = MO.getGlobal();
159 AsmPrinter.getNameWithPrefix(Name, GV);
160 } else if (MO.isSymbol()) {
161 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
162 } else if (MO.isMBB()) {
163 assert(Suffix.empty());
164 Sym = MO.getMBB()->getSymbol();
166 unsigned OrigLen = Name.size() - PrefixLen;
170 Sym = Ctx.getOrCreateSymbol(Name);
172 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
174 // If the target flags on the operand changes the name of the symbol, do that
175 // before we return the symbol.
176 switch (MO.getTargetFlags()) {
178 case X86II::MO_DARWIN_NONLAZY:
179 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
180 MachineModuleInfoImpl::StubValueTy &StubSym =
181 getMachOMMI().getGVStubEntry(Sym);
182 if (!StubSym.getPointer()) {
183 assert(MO.isGlobal() && "Extern symbol not handled yet");
185 MachineModuleInfoImpl::
186 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
187 !MO.getGlobal()->hasInternalLinkage());
191 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
192 MachineModuleInfoImpl::StubValueTy &StubSym =
193 getMachOMMI().getHiddenGVStubEntry(Sym);
194 if (!StubSym.getPointer()) {
195 assert(MO.isGlobal() && "Extern symbol not handled yet");
197 MachineModuleInfoImpl::
198 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
199 !MO.getGlobal()->hasInternalLinkage());
203 case X86II::MO_DARWIN_STUB: {
204 MachineModuleInfoImpl::StubValueTy &StubSym =
205 getMachOMMI().getFnStubEntry(Sym);
206 if (StubSym.getPointer())
211 MachineModuleInfoImpl::
212 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
213 !MO.getGlobal()->hasInternalLinkage());
216 MachineModuleInfoImpl::
217 StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
226 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
227 MCSymbol *Sym) const {
228 // FIXME: We would like an efficient form for this, so we don't have to do a
229 // lot of extra uniquing.
230 const MCExpr *Expr = nullptr;
231 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
233 switch (MO.getTargetFlags()) {
234 default: llvm_unreachable("Unknown target flag on GV operand");
235 case X86II::MO_NO_FLAG: // No flag.
236 // These affect the name of the symbol, not any suffix.
237 case X86II::MO_DARWIN_NONLAZY:
238 case X86II::MO_DLLIMPORT:
239 case X86II::MO_DARWIN_STUB:
242 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
243 case X86II::MO_TLVP_PIC_BASE:
244 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
245 // Subtract the pic base.
246 Expr = MCBinaryExpr::createSub(Expr,
247 MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
251 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
252 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
253 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
254 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
255 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
256 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
257 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
258 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
259 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
260 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
261 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
262 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
263 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
264 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
265 case X86II::MO_PIC_BASE_OFFSET:
266 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
267 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
268 Expr = MCSymbolRefExpr::create(Sym, Ctx);
269 // Subtract the pic base.
270 Expr = MCBinaryExpr::createSub(Expr,
271 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
274 assert(MAI.doesSetDirectiveSuppressesReloc());
275 // If .set directive is supported, use it to reduce the number of
276 // relocations the assembler will generate for differences between
277 // local labels. This is only safe when the symbols are in the same
278 // section so we are restricting it to jumptable references.
279 MCSymbol *Label = Ctx.createTempSymbol();
280 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
281 Expr = MCSymbolRefExpr::create(Label, Ctx);
287 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
289 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
290 Expr = MCBinaryExpr::createAdd(Expr,
291 MCConstantExpr::create(MO.getOffset(), Ctx),
293 return MCOperand::createExpr(Expr);
297 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
298 /// a short fixed-register form.
299 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
300 unsigned ImmOp = Inst.getNumOperands() - 1;
301 assert(Inst.getOperand(0).isReg() &&
302 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
303 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
304 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
305 Inst.getNumOperands() == 2) && "Unexpected instruction!");
307 // Check whether the destination register can be fixed.
308 unsigned Reg = Inst.getOperand(0).getReg();
309 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
312 // If so, rewrite the instruction.
313 MCOperand Saved = Inst.getOperand(ImmOp);
315 Inst.setOpcode(Opcode);
316 Inst.addOperand(Saved);
319 /// \brief If a movsx instruction has a shorter encoding for the used register
320 /// simplify the instruction to use it instead.
321 static void SimplifyMOVSX(MCInst &Inst) {
322 unsigned NewOpcode = 0;
323 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
324 switch (Inst.getOpcode()) {
326 llvm_unreachable("Unexpected instruction!");
327 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
328 if (Op0 == X86::AX && Op1 == X86::AL)
329 NewOpcode = X86::CBW;
331 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
332 if (Op0 == X86::EAX && Op1 == X86::AX)
333 NewOpcode = X86::CWDE;
335 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
336 if (Op0 == X86::RAX && Op1 == X86::EAX)
337 NewOpcode = X86::CDQE;
341 if (NewOpcode != 0) {
343 Inst.setOpcode(NewOpcode);
347 /// \brief Simplify things like MOV32rm to MOV32o32a.
348 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
350 // Don't make these simplifications in 64-bit mode; other assemblers don't
351 // perform them because they make the code larger.
352 if (Printer.getSubtarget().is64Bit())
355 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
356 unsigned AddrBase = IsStore;
357 unsigned RegOp = IsStore ? 0 : 5;
358 unsigned AddrOp = AddrBase + 3;
359 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
360 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
361 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
362 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
363 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
364 (Inst.getOperand(AddrOp).isExpr() ||
365 Inst.getOperand(AddrOp).isImm()) &&
366 "Unexpected instruction!");
368 // Check whether the destination register can be fixed.
369 unsigned Reg = Inst.getOperand(RegOp).getReg();
370 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
373 // Check whether this is an absolute address.
374 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
376 bool Absolute = true;
377 if (Inst.getOperand(AddrOp).isExpr()) {
378 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
379 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
380 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
385 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
386 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
387 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
390 // If so, rewrite the instruction.
391 MCOperand Saved = Inst.getOperand(AddrOp);
392 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
394 Inst.setOpcode(Opcode);
395 Inst.addOperand(Saved);
396 Inst.addOperand(Seg);
399 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
400 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
404 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
405 const MachineOperand &MO) const {
406 switch (MO.getType()) {
409 llvm_unreachable("unknown operand type");
410 case MachineOperand::MO_Register:
411 // Ignore all implicit register operands.
414 return MCOperand::createReg(MO.getReg());
415 case MachineOperand::MO_Immediate:
416 return MCOperand::createImm(MO.getImm());
417 case MachineOperand::MO_MachineBasicBlock:
418 case MachineOperand::MO_GlobalAddress:
419 case MachineOperand::MO_ExternalSymbol:
420 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
421 case MachineOperand::MO_MCSymbol:
422 return LowerSymbolOperand(MO, MO.getMCSymbol());
423 case MachineOperand::MO_JumpTableIndex:
424 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
425 case MachineOperand::MO_ConstantPoolIndex:
426 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
427 case MachineOperand::MO_BlockAddress:
428 return LowerSymbolOperand(
429 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
430 case MachineOperand::MO_RegisterMask:
431 // Ignore call clobbers.
436 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
437 OutMI.setOpcode(MI->getOpcode());
439 for (const MachineOperand &MO : MI->operands())
440 if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
441 OutMI.addOperand(MaybeMCOp.getValue());
443 // Handle a few special cases to eliminate operand modifiers.
445 switch (OutMI.getOpcode()) {
450 // LEA should have a segment register, but it must be empty.
451 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
452 "Unexpected # of LEA operands");
453 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
454 "LEA has segment specified!");
458 OutMI.setOpcode(X86::MOV32ri);
461 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
462 // if one of the registers is extended, but other isn't.
464 case X86::VMOVAPDYrr:
466 case X86::VMOVAPSYrr:
468 case X86::VMOVDQAYrr:
470 case X86::VMOVDQUYrr:
472 case X86::VMOVUPDYrr:
474 case X86::VMOVUPSYrr: {
475 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
476 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
478 switch (OutMI.getOpcode()) {
479 default: llvm_unreachable("Invalid opcode");
480 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
481 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
482 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
483 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
484 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
485 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
486 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
487 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
488 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
489 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
490 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
491 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
493 OutMI.setOpcode(NewOpc);
498 case X86::VMOVSSrr: {
499 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
500 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
502 switch (OutMI.getOpcode()) {
503 default: llvm_unreachable("Invalid opcode");
504 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
505 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
507 OutMI.setOpcode(NewOpc);
512 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
513 // inputs modeled as normal uses instead of implicit uses. As such, truncate
514 // off all but the first operand (the callee). FIXME: Change isel.
515 case X86::TAILJMPr64:
516 case X86::TAILJMPr64_REX:
518 case X86::CALL64pcrel32: {
519 unsigned Opcode = OutMI.getOpcode();
520 MCOperand Saved = OutMI.getOperand(0);
522 OutMI.setOpcode(Opcode);
523 OutMI.addOperand(Saved);
528 case X86::EH_RETURN64: {
530 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
535 case X86::CATCHRET64: {
537 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
541 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
544 case X86::TAILJMPd64: {
546 switch (OutMI.getOpcode()) {
547 default: llvm_unreachable("Invalid opcode");
548 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
550 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
553 MCOperand Saved = OutMI.getOperand(0);
555 OutMI.setOpcode(Opcode);
556 OutMI.addOperand(Saved);
564 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
565 if (!AsmPrinter.getSubtarget().is64Bit()) {
567 switch (OutMI.getOpcode()) {
568 default: llvm_unreachable("Invalid opcode");
569 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
570 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
571 case X86::INC16r: Opcode = X86::INC16r_alt; break;
572 case X86::INC32r: Opcode = X86::INC32r_alt; break;
574 OutMI.setOpcode(Opcode);
578 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
579 // this with an ugly goto in case the resultant OR uses EAX and needs the
581 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
582 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
583 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
584 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
585 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
586 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
587 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
588 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
589 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
591 // Atomic load and store require a separate pseudo-inst because Acquire
592 // implies mayStore and Release implies mayLoad; fix these to regular MOV
594 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
595 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
596 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
597 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
598 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
599 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
600 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
601 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
602 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
603 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
604 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
605 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
606 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
607 case X86::RELEASE_ADD8mr: OutMI.setOpcode(X86::ADD8mr); goto ReSimplify;
608 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
609 case X86::RELEASE_ADD32mr: OutMI.setOpcode(X86::ADD32mr); goto ReSimplify;
610 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
611 case X86::RELEASE_ADD64mr: OutMI.setOpcode(X86::ADD64mr); goto ReSimplify;
612 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
613 case X86::RELEASE_AND8mr: OutMI.setOpcode(X86::AND8mr); goto ReSimplify;
614 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
615 case X86::RELEASE_AND32mr: OutMI.setOpcode(X86::AND32mr); goto ReSimplify;
616 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
617 case X86::RELEASE_AND64mr: OutMI.setOpcode(X86::AND64mr); goto ReSimplify;
618 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
619 case X86::RELEASE_OR8mr: OutMI.setOpcode(X86::OR8mr); goto ReSimplify;
620 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
621 case X86::RELEASE_OR32mr: OutMI.setOpcode(X86::OR32mr); goto ReSimplify;
622 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
623 case X86::RELEASE_OR64mr: OutMI.setOpcode(X86::OR64mr); goto ReSimplify;
624 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
625 case X86::RELEASE_XOR8mr: OutMI.setOpcode(X86::XOR8mr); goto ReSimplify;
626 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
627 case X86::RELEASE_XOR32mr: OutMI.setOpcode(X86::XOR32mr); goto ReSimplify;
628 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
629 case X86::RELEASE_XOR64mr: OutMI.setOpcode(X86::XOR64mr); goto ReSimplify;
630 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
631 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
632 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
633 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
634 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
635 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
636 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
637 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
639 // We don't currently select the correct instruction form for instructions
640 // which have a short %eax, etc. form. Handle this by custom lowering, for
643 // Note, we are currently not handling the following instructions:
644 // MOV64ao8, MOV64o8a
645 // XCHG16ar, XCHG32ar, XCHG64ar
646 case X86::MOV8mr_NOREX:
647 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
648 case X86::MOV8rm_NOREX:
649 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
650 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
651 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
652 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
653 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
655 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
656 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
657 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
658 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
659 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
660 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
661 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
662 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
663 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
664 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
665 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
666 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
667 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
668 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
669 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
670 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
671 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
672 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
673 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
674 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
675 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
676 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
677 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
678 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
679 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
680 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
681 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
682 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
683 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
684 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
685 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
686 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
687 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
688 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
689 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
690 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
692 // Try to shrink some forms of movsx.
693 case X86::MOVSX16rr8:
694 case X86::MOVSX32rr16:
695 case X86::MOVSX64rr32:
696 SimplifyMOVSX(OutMI);
701 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
702 const MachineInstr &MI) {
704 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
705 MI.getOpcode() == X86::TLS_base_addr64;
707 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
709 MCContext &context = OutStreamer->getContext();
712 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
714 MCSymbolRefExpr::VariantKind SRVK;
715 switch (MI.getOpcode()) {
716 case X86::TLS_addr32:
717 case X86::TLS_addr64:
718 SRVK = MCSymbolRefExpr::VK_TLSGD;
720 case X86::TLS_base_addr32:
721 SRVK = MCSymbolRefExpr::VK_TLSLDM;
723 case X86::TLS_base_addr64:
724 SRVK = MCSymbolRefExpr::VK_TLSLD;
727 llvm_unreachable("unexpected opcode");
730 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
731 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
735 LEA.setOpcode(X86::LEA64r);
736 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
737 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
738 LEA.addOperand(MCOperand::createImm(1)); // scale
739 LEA.addOperand(MCOperand::createReg(0)); // index
740 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
741 LEA.addOperand(MCOperand::createReg(0)); // seg
742 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
743 LEA.setOpcode(X86::LEA32r);
744 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
745 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
746 LEA.addOperand(MCOperand::createImm(1)); // scale
747 LEA.addOperand(MCOperand::createReg(0)); // index
748 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
749 LEA.addOperand(MCOperand::createReg(0)); // seg
751 LEA.setOpcode(X86::LEA32r);
752 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
753 LEA.addOperand(MCOperand::createReg(0)); // base
754 LEA.addOperand(MCOperand::createImm(1)); // scale
755 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
756 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
757 LEA.addOperand(MCOperand::createReg(0)); // seg
759 EmitAndCountInstruction(LEA);
762 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
763 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
764 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
767 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
768 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
769 const MCSymbolRefExpr *tlsRef =
770 MCSymbolRefExpr::create(tlsGetAddr,
771 MCSymbolRefExpr::VK_PLT,
774 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
779 /// \brief Emit the optimal amount of multi-byte nops on X86.
780 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
781 // This works only for 64bit. For 32bit we have to do additional checking if
782 // the CPU supports multi-byte nops.
783 assert(Is64Bit && "EmitNops only supports X86-64");
785 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
786 Opc = IndexReg = Displacement = SegmentReg = 0;
787 BaseReg = X86::RAX; ScaleVal = 1;
789 case 0: llvm_unreachable("Zero nops?"); break;
790 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
791 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
792 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
793 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
794 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
795 IndexReg = X86::RAX; break;
796 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
797 IndexReg = X86::RAX; break;
798 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
799 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
800 IndexReg = X86::RAX; break;
801 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
802 IndexReg = X86::RAX; break;
803 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
804 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
807 unsigned NumPrefixes = std::min(NumBytes, 5U);
808 NumBytes -= NumPrefixes;
809 for (unsigned i = 0; i != NumPrefixes; ++i)
810 OS.EmitBytes("\x66");
813 default: llvm_unreachable("Unexpected opcode"); break;
815 OS.EmitInstruction(MCInstBuilder(Opc), STI);
818 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
822 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
823 .addImm(ScaleVal).addReg(IndexReg)
824 .addImm(Displacement).addReg(SegmentReg), STI);
827 } // while (NumBytes)
830 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
831 X86MCInstLower &MCIL) {
832 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
834 StatepointOpers SOpers(&MI);
835 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
836 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
839 // Lower call target and choose correct opcode
840 const MachineOperand &CallTarget = SOpers.getCallTarget();
841 MCOperand CallTargetMCOp;
843 switch (CallTarget.getType()) {
844 case MachineOperand::MO_GlobalAddress:
845 case MachineOperand::MO_ExternalSymbol:
846 CallTargetMCOp = MCIL.LowerSymbolOperand(
847 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
848 CallOpcode = X86::CALL64pcrel32;
849 // Currently, we only support relative addressing with statepoints.
850 // Otherwise, we'll need a scratch register to hold the target
851 // address. You'll fail asserts during load & relocation if this
852 // symbol is to far away. (TODO: support non-relative addressing)
854 case MachineOperand::MO_Immediate:
855 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
856 CallOpcode = X86::CALL64pcrel32;
857 // Currently, we only support relative addressing with statepoints.
858 // Otherwise, we'll need a scratch register to hold the target
859 // immediate. You'll fail asserts during load & relocation if this
860 // address is to far away. (TODO: support non-relative addressing)
862 case MachineOperand::MO_Register:
863 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
864 CallOpcode = X86::CALL64r;
867 llvm_unreachable("Unsupported operand type in statepoint call target");
873 CallInst.setOpcode(CallOpcode);
874 CallInst.addOperand(CallTargetMCOp);
875 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
878 // Record our statepoint node in the same section used by STACKMAP
880 SM.recordStatepoint(MI);
883 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI,
884 X86MCInstLower &MCIL) {
885 // FAULTING_LOAD_OP <def>, <handler label>, <load opcode>, <load operands>
887 unsigned LoadDefRegister = MI.getOperand(0).getReg();
888 MCSymbol *HandlerLabel = MI.getOperand(1).getMCSymbol();
889 unsigned LoadOpcode = MI.getOperand(2).getImm();
890 unsigned LoadOperandsBeginIdx = 3;
892 FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel);
895 LoadMI.setOpcode(LoadOpcode);
897 if (LoadDefRegister != X86::NoRegister)
898 LoadMI.addOperand(MCOperand::createReg(LoadDefRegister));
900 for (auto I = MI.operands_begin() + LoadOperandsBeginIdx,
901 E = MI.operands_end();
903 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I))
904 LoadMI.addOperand(MaybeOperand.getValue());
906 OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo());
909 // Lower a stackmap of the form:
910 // <id>, <shadowBytes>, ...
911 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
912 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
913 SM.recordStackMap(MI);
914 unsigned NumShadowBytes = MI.getOperand(1).getImm();
915 SMShadowTracker.reset(NumShadowBytes);
918 // Lower a patchpoint of the form:
919 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
920 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
921 X86MCInstLower &MCIL) {
922 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
924 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
926 SM.recordPatchPoint(MI);
928 PatchPointOpers opers(&MI);
929 unsigned ScratchIdx = opers.getNextScratchIdx();
930 unsigned EncodedBytes = 0;
931 const MachineOperand &CalleeMO =
932 opers.getMetaOper(PatchPointOpers::TargetPos);
934 // Check for null target. If target is non-null (i.e. is non-zero or is
935 // symbolic) then emit a call.
936 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
937 MCOperand CalleeMCOp;
938 switch (CalleeMO.getType()) {
940 /// FIXME: Add a verifier check for bad callee types.
941 llvm_unreachable("Unrecognized callee operand type.");
942 case MachineOperand::MO_Immediate:
943 if (CalleeMO.getImm())
944 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
946 case MachineOperand::MO_ExternalSymbol:
947 case MachineOperand::MO_GlobalAddress:
949 MCIL.LowerSymbolOperand(CalleeMO,
950 MCIL.GetSymbolFromOperand(CalleeMO));
954 // Emit MOV to materialize the target address and the CALL to target.
955 // This is encoded with 12-13 bytes, depending on which register is used.
956 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
957 if (X86II::isX86_64ExtendedReg(ScratchReg))
962 EmitAndCountInstruction(
963 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
964 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
968 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
969 assert(NumBytes >= EncodedBytes &&
970 "Patchpoint can't request size less than the length of a call.");
972 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
976 // Returns instruction preceding MBBI in MachineFunction.
977 // If MBBI is the first instruction of the first basic block, returns null.
978 static MachineBasicBlock::const_iterator
979 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
980 const MachineBasicBlock *MBB = MBBI->getParent();
981 while (MBBI == MBB->begin()) {
982 if (MBB == MBB->getParent()->begin())
984 MBB = MBB->getPrevNode();
990 static const Constant *getConstantFromPool(const MachineInstr &MI,
991 const MachineOperand &Op) {
995 ArrayRef<MachineConstantPoolEntry> Constants =
996 MI.getParent()->getParent()->getConstantPool()->getConstants();
997 const MachineConstantPoolEntry &ConstantEntry =
998 Constants[Op.getIndex()];
1000 // Bail if this is a machine constant pool entry, we won't be able to dig out
1002 if (ConstantEntry.isMachineConstantPoolEntry())
1005 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
1006 assert((!C || ConstantEntry.getType() == C->getType()) &&
1007 "Expected a constant of the same type!");
1011 static std::string getShuffleComment(const MachineOperand &DstOp,
1012 const MachineOperand &SrcOp,
1013 ArrayRef<int> Mask) {
1014 std::string Comment;
1016 // Compute the name for a register. This is really goofy because we have
1017 // multiple instruction printers that could (in theory) use different
1018 // names. Fortunately most people use the ATT style (outside of Windows)
1019 // and they actually agree on register naming here. Ultimately, this is
1020 // a comment, and so its OK if it isn't perfect.
1021 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1022 return X86ATTInstPrinter::getRegisterName(RegNum);
1025 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1026 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
1028 raw_string_ostream CS(Comment);
1029 CS << DstName << " = ";
1030 bool NeedComma = false;
1032 for (int M : Mask) {
1033 // Wrap up any prior entry...
1034 if (M == SM_SentinelZero && InSrc) {
1043 // Print this shuffle...
1044 if (M == SM_SentinelZero) {
1049 CS << SrcName << "[";
1051 if (M == SM_SentinelUndef)
1064 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1065 X86MCInstLower MCInstLowering(*MF, *this);
1066 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1068 switch (MI->getOpcode()) {
1069 case TargetOpcode::DBG_VALUE:
1070 llvm_unreachable("Should be handled target independently");
1072 // Emit nothing here but a comment if we can.
1073 case X86::Int_MemBarrier:
1074 OutStreamer->emitRawComment("MEMBARRIER");
1078 case X86::EH_RETURN:
1079 case X86::EH_RETURN64: {
1080 // Lower these as normal, but add some comments.
1081 unsigned Reg = MI->getOperand(0).getReg();
1082 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1083 X86ATTInstPrinter::getRegisterName(Reg));
1089 case X86::TAILJMPr64:
1090 case X86::TAILJMPm64:
1091 case X86::TAILJMPd64:
1092 case X86::TAILJMPr64_REX:
1093 case X86::TAILJMPm64_REX:
1094 case X86::TAILJMPd64_REX:
1095 // Lower these as normal, but add some comments.
1096 OutStreamer->AddComment("TAILCALL");
1099 case X86::TLS_addr32:
1100 case X86::TLS_addr64:
1101 case X86::TLS_base_addr32:
1102 case X86::TLS_base_addr64:
1103 return LowerTlsAddr(MCInstLowering, *MI);
1105 case X86::MOVPC32r: {
1106 // This is a pseudo op for a two instruction sequence with a label, which
1113 MCSymbol *PICBase = MF->getPICBaseSymbol();
1114 // FIXME: We would like an efficient form for this, so we don't have to do a
1115 // lot of extra uniquing.
1116 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1117 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1120 OutStreamer->EmitLabel(PICBase);
1123 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1124 .addReg(MI->getOperand(0).getReg()));
1128 case X86::ADD32ri: {
1129 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1130 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1133 // Okay, we have something like:
1134 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1136 // For this, we want to print something like:
1137 // MYGLOBAL + (. - PICBASE)
1138 // However, we can't generate a ".", so just emit a new label here and refer
1140 MCSymbol *DotSym = OutContext.createTempSymbol();
1141 OutStreamer->EmitLabel(DotSym);
1143 // Now that we have emitted the label, lower the complex operand expression.
1144 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1146 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1147 const MCExpr *PICBase =
1148 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1149 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1151 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
1152 DotExpr, OutContext);
1154 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1155 .addReg(MI->getOperand(0).getReg())
1156 .addReg(MI->getOperand(1).getReg())
1160 case TargetOpcode::STATEPOINT:
1161 return LowerSTATEPOINT(*MI, MCInstLowering);
1163 case TargetOpcode::FAULTING_LOAD_OP:
1164 return LowerFAULTING_LOAD_OP(*MI, MCInstLowering);
1166 case TargetOpcode::STACKMAP:
1167 return LowerSTACKMAP(*MI);
1169 case TargetOpcode::PATCHPOINT:
1170 return LowerPATCHPOINT(*MI, MCInstLowering);
1172 case X86::MORESTACK_RET:
1173 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1176 case X86::MORESTACK_RET_RESTORE_R10:
1177 // Return, then restore R10.
1178 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1179 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1184 case X86::SEH_PushReg:
1185 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1188 case X86::SEH_SaveReg:
1189 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1190 MI->getOperand(1).getImm());
1193 case X86::SEH_SaveXMM:
1194 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1195 MI->getOperand(1).getImm());
1198 case X86::SEH_StackAlloc:
1199 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1202 case X86::SEH_SetFrame:
1203 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1204 MI->getOperand(1).getImm());
1207 case X86::SEH_PushFrame:
1208 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1211 case X86::SEH_EndPrologue:
1212 OutStreamer->EmitWinCFIEndProlog();
1215 case X86::SEH_Epilogue: {
1216 MachineBasicBlock::const_iterator MBBI(MI);
1217 // Check if preceded by a call and emit nop if so.
1218 for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1219 // Conservatively assume that pseudo instructions don't emit code and keep
1220 // looking for a call. We may emit an unnecessary nop in some cases.
1221 if (!MBBI->isPseudo()) {
1223 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1230 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1231 // a constant shuffle mask. We won't be able to do this at the MC layer
1232 // because the mask isn't an immediate.
1234 case X86::VPSHUFBrm:
1235 case X86::VPSHUFBYrm: {
1236 if (!OutStreamer->isVerboseAsm())
1238 assert(MI->getNumOperands() > 5 &&
1239 "We should always have at least 5 operands!");
1240 const MachineOperand &DstOp = MI->getOperand(0);
1241 const MachineOperand &SrcOp = MI->getOperand(1);
1242 const MachineOperand &MaskOp = MI->getOperand(5);
1244 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1245 SmallVector<int, 16> Mask;
1246 DecodePSHUFBMask(C, Mask);
1248 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1252 case X86::VPERMILPSrm:
1253 case X86::VPERMILPDrm:
1254 case X86::VPERMILPSYrm:
1255 case X86::VPERMILPDYrm: {
1256 if (!OutStreamer->isVerboseAsm())
1258 assert(MI->getNumOperands() > 5 &&
1259 "We should always have at least 5 operands!");
1260 const MachineOperand &DstOp = MI->getOperand(0);
1261 const MachineOperand &SrcOp = MI->getOperand(1);
1262 const MachineOperand &MaskOp = MI->getOperand(5);
1264 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1265 SmallVector<int, 16> Mask;
1266 DecodeVPERMILPMask(C, Mask);
1268 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1273 #define MOV_CASE(Prefix, Suffix) \
1274 case X86::Prefix##MOVAPD##Suffix##rm: \
1275 case X86::Prefix##MOVAPS##Suffix##rm: \
1276 case X86::Prefix##MOVUPD##Suffix##rm: \
1277 case X86::Prefix##MOVUPS##Suffix##rm: \
1278 case X86::Prefix##MOVDQA##Suffix##rm: \
1279 case X86::Prefix##MOVDQU##Suffix##rm:
1281 #define MOV_AVX512_CASE(Suffix) \
1282 case X86::VMOVDQA64##Suffix##rm: \
1283 case X86::VMOVDQA32##Suffix##rm: \
1284 case X86::VMOVDQU64##Suffix##rm: \
1285 case X86::VMOVDQU32##Suffix##rm: \
1286 case X86::VMOVDQU16##Suffix##rm: \
1287 case X86::VMOVDQU8##Suffix##rm: \
1288 case X86::VMOVAPS##Suffix##rm: \
1289 case X86::VMOVAPD##Suffix##rm: \
1290 case X86::VMOVUPS##Suffix##rm: \
1291 case X86::VMOVUPD##Suffix##rm:
1293 #define CASE_ALL_MOV_RM() \
1294 MOV_CASE(, ) /* SSE */ \
1295 MOV_CASE(V, ) /* AVX-128 */ \
1296 MOV_CASE(V, Y) /* AVX-256 */ \
1297 MOV_AVX512_CASE(Z) \
1298 MOV_AVX512_CASE(Z256) \
1299 MOV_AVX512_CASE(Z128)
1301 // For loads from a constant pool to a vector register, print the constant
1304 if (!OutStreamer->isVerboseAsm())
1306 if (MI->getNumOperands() > 4)
1307 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1308 std::string Comment;
1309 raw_string_ostream CS(Comment);
1310 const MachineOperand &DstOp = MI->getOperand(0);
1311 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1312 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1314 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1317 if (CDS->getElementType()->isIntegerTy())
1318 CS << CDS->getElementAsInteger(i);
1319 else if (CDS->getElementType()->isFloatTy())
1320 CS << CDS->getElementAsFloat(i);
1321 else if (CDS->getElementType()->isDoubleTy())
1322 CS << CDS->getElementAsDouble(i);
1327 OutStreamer->AddComment(CS.str());
1328 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1330 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1333 Constant *COp = CV->getOperand(i);
1334 if (isa<UndefValue>(COp)) {
1336 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1337 CS << CI->getZExtValue();
1338 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1339 SmallString<32> Str;
1340 CF->getValueAPF().toString(Str);
1347 OutStreamer->AddComment(CS.str());
1354 MCInstLowering.Lower(MI, TmpInst);
1356 // Stackmap shadows cannot include branch targets, so we can count the bytes
1357 // in a call towards the shadow, but must ensure that the no thread returns
1358 // in to the stackmap shadow. The only way to achieve this is if the call
1359 // is at the end of the shadow.
1361 // Count then size of the call towards the shadow
1362 SMShadowTracker.count(TmpInst, getSubtargetInfo());
1363 // Then flush the shadow so that we fill with nops before the call, not
1365 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1366 // Then emit the call
1367 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1371 EmitAndCountInstruction(TmpInst);