1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/Optional.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
26 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/Mangler.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCCodeEmitter.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixup.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Support/TargetRegistry.h"
44 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
45 class X86MCInstLower {
47 const MachineFunction &MF;
48 const TargetMachine &TM;
50 X86AsmPrinter &AsmPrinter;
52 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
54 Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
55 const MachineOperand &MO) const;
56 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
58 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
59 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
62 MachineModuleInfoMachO &getMachOMMI() const;
63 Mangler *getMang() const {
64 return AsmPrinter.Mang;
68 } // end anonymous namespace
70 // Emit a minimal sequence of nops spanning NumBytes bytes.
71 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
72 const MCSubtargetInfo &STI);
75 X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
76 : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
78 X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
81 X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
83 CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
84 *MF->getSubtarget().getInstrInfo(),
85 *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
88 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
89 const MCSubtargetInfo &STI) {
91 SmallString<256> Code;
92 SmallVector<MCFixup, 4> Fixups;
93 raw_svector_ostream VecOS(Code);
94 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
96 CurrentShadowSize += Code.size();
97 if (CurrentShadowSize >= RequiredShadowSize)
98 InShadow = false; // The shadow is big enough. Stop counting.
102 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
103 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
104 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
106 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
107 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
111 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
112 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
113 SMShadowTracker.count(Inst, getSubtargetInfo());
115 } // end llvm namespace
117 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
118 X86AsmPrinter &asmprinter)
119 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
120 AsmPrinter(asmprinter) {}
122 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
123 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
127 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
128 /// operand to an MCSymbol.
129 MCSymbol *X86MCInstLower::
130 GetSymbolFromOperand(const MachineOperand &MO) const {
131 const DataLayout &DL = MF.getDataLayout();
132 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
134 MCSymbol *Sym = nullptr;
135 SmallString<128> Name;
138 switch (MO.getTargetFlags()) {
139 case X86II::MO_DLLIMPORT:
140 // Handle dllimport linkage.
143 case X86II::MO_DARWIN_STUB:
146 case X86II::MO_DARWIN_NONLAZY:
147 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
148 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
149 Suffix = "$non_lazy_ptr";
154 Name += DL.getPrivateGlobalPrefix();
156 unsigned PrefixLen = Name.size();
159 const GlobalValue *GV = MO.getGlobal();
160 AsmPrinter.getNameWithPrefix(Name, GV);
161 } else if (MO.isSymbol()) {
162 Mangler::getNameWithPrefix(Name, MO.getSymbolName(), DL);
163 } else if (MO.isMBB()) {
164 assert(Suffix.empty());
165 Sym = MO.getMBB()->getSymbol();
167 unsigned OrigLen = Name.size() - PrefixLen;
171 Sym = Ctx.getOrCreateSymbol(Name);
173 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
175 // If the target flags on the operand changes the name of the symbol, do that
176 // before we return the symbol.
177 switch (MO.getTargetFlags()) {
179 case X86II::MO_DARWIN_NONLAZY:
180 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
181 MachineModuleInfoImpl::StubValueTy &StubSym =
182 getMachOMMI().getGVStubEntry(Sym);
183 if (!StubSym.getPointer()) {
184 assert(MO.isGlobal() && "Extern symbol not handled yet");
186 MachineModuleInfoImpl::
187 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
188 !MO.getGlobal()->hasInternalLinkage());
192 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
193 MachineModuleInfoImpl::StubValueTy &StubSym =
194 getMachOMMI().getHiddenGVStubEntry(Sym);
195 if (!StubSym.getPointer()) {
196 assert(MO.isGlobal() && "Extern symbol not handled yet");
198 MachineModuleInfoImpl::
199 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
200 !MO.getGlobal()->hasInternalLinkage());
204 case X86II::MO_DARWIN_STUB: {
205 MachineModuleInfoImpl::StubValueTy &StubSym =
206 getMachOMMI().getFnStubEntry(Sym);
207 if (StubSym.getPointer())
212 MachineModuleInfoImpl::
213 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
214 !MO.getGlobal()->hasInternalLinkage());
217 MachineModuleInfoImpl::
218 StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
227 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
228 MCSymbol *Sym) const {
229 // FIXME: We would like an efficient form for this, so we don't have to do a
230 // lot of extra uniquing.
231 const MCExpr *Expr = nullptr;
232 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
234 switch (MO.getTargetFlags()) {
235 default: llvm_unreachable("Unknown target flag on GV operand");
236 case X86II::MO_NO_FLAG: // No flag.
237 // These affect the name of the symbol, not any suffix.
238 case X86II::MO_DARWIN_NONLAZY:
239 case X86II::MO_DLLIMPORT:
240 case X86II::MO_DARWIN_STUB:
243 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
244 case X86II::MO_TLVP_PIC_BASE:
245 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
246 // Subtract the pic base.
247 Expr = MCBinaryExpr::createSub(Expr,
248 MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
252 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
253 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
254 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
255 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
256 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
257 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
258 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
259 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
260 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
261 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
262 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
263 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
264 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
265 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
266 case X86II::MO_PIC_BASE_OFFSET:
267 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
268 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
269 Expr = MCSymbolRefExpr::create(Sym, Ctx);
270 // Subtract the pic base.
271 Expr = MCBinaryExpr::createSub(Expr,
272 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
275 assert(MAI.doesSetDirectiveSuppressesReloc());
276 // If .set directive is supported, use it to reduce the number of
277 // relocations the assembler will generate for differences between
278 // local labels. This is only safe when the symbols are in the same
279 // section so we are restricting it to jumptable references.
280 MCSymbol *Label = Ctx.createTempSymbol();
281 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
282 Expr = MCSymbolRefExpr::create(Label, Ctx);
288 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
290 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
291 Expr = MCBinaryExpr::createAdd(Expr,
292 MCConstantExpr::create(MO.getOffset(), Ctx),
294 return MCOperand::createExpr(Expr);
298 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
299 /// a short fixed-register form.
300 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
301 unsigned ImmOp = Inst.getNumOperands() - 1;
302 assert(Inst.getOperand(0).isReg() &&
303 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
304 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
305 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
306 Inst.getNumOperands() == 2) && "Unexpected instruction!");
308 // Check whether the destination register can be fixed.
309 unsigned Reg = Inst.getOperand(0).getReg();
310 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
313 // If so, rewrite the instruction.
314 MCOperand Saved = Inst.getOperand(ImmOp);
316 Inst.setOpcode(Opcode);
317 Inst.addOperand(Saved);
320 /// \brief If a movsx instruction has a shorter encoding for the used register
321 /// simplify the instruction to use it instead.
322 static void SimplifyMOVSX(MCInst &Inst) {
323 unsigned NewOpcode = 0;
324 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
325 switch (Inst.getOpcode()) {
327 llvm_unreachable("Unexpected instruction!");
328 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
329 if (Op0 == X86::AX && Op1 == X86::AL)
330 NewOpcode = X86::CBW;
332 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
333 if (Op0 == X86::EAX && Op1 == X86::AX)
334 NewOpcode = X86::CWDE;
336 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
337 if (Op0 == X86::RAX && Op1 == X86::EAX)
338 NewOpcode = X86::CDQE;
342 if (NewOpcode != 0) {
344 Inst.setOpcode(NewOpcode);
348 /// \brief Simplify things like MOV32rm to MOV32o32a.
349 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
351 // Don't make these simplifications in 64-bit mode; other assemblers don't
352 // perform them because they make the code larger.
353 if (Printer.getSubtarget().is64Bit())
356 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
357 unsigned AddrBase = IsStore;
358 unsigned RegOp = IsStore ? 0 : 5;
359 unsigned AddrOp = AddrBase + 3;
360 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
361 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
362 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
363 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
364 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
365 (Inst.getOperand(AddrOp).isExpr() ||
366 Inst.getOperand(AddrOp).isImm()) &&
367 "Unexpected instruction!");
369 // Check whether the destination register can be fixed.
370 unsigned Reg = Inst.getOperand(RegOp).getReg();
371 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
374 // Check whether this is an absolute address.
375 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
377 bool Absolute = true;
378 if (Inst.getOperand(AddrOp).isExpr()) {
379 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
380 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
381 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
386 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
387 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
388 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
391 // If so, rewrite the instruction.
392 MCOperand Saved = Inst.getOperand(AddrOp);
393 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
395 Inst.setOpcode(Opcode);
396 Inst.addOperand(Saved);
397 Inst.addOperand(Seg);
400 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
401 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
405 X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
406 const MachineOperand &MO) const {
407 switch (MO.getType()) {
410 llvm_unreachable("unknown operand type");
411 case MachineOperand::MO_Register:
412 // Ignore all implicit register operands.
415 return MCOperand::createReg(MO.getReg());
416 case MachineOperand::MO_Immediate:
417 return MCOperand::createImm(MO.getImm());
418 case MachineOperand::MO_MachineBasicBlock:
419 case MachineOperand::MO_GlobalAddress:
420 case MachineOperand::MO_ExternalSymbol:
421 return LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
422 case MachineOperand::MO_MCSymbol:
423 return LowerSymbolOperand(MO, MO.getMCSymbol());
424 case MachineOperand::MO_JumpTableIndex:
425 return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
426 case MachineOperand::MO_ConstantPoolIndex:
427 return LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
428 case MachineOperand::MO_BlockAddress:
429 return LowerSymbolOperand(
430 MO, AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
431 case MachineOperand::MO_RegisterMask:
432 // Ignore call clobbers.
437 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
438 OutMI.setOpcode(MI->getOpcode());
440 for (const MachineOperand &MO : MI->operands())
441 if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
442 OutMI.addOperand(MaybeMCOp.getValue());
444 // Handle a few special cases to eliminate operand modifiers.
446 switch (OutMI.getOpcode()) {
451 // LEA should have a segment register, but it must be empty.
452 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
453 "Unexpected # of LEA operands");
454 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
455 "LEA has segment specified!");
459 OutMI.setOpcode(X86::MOV32ri);
462 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
463 // if one of the registers is extended, but other isn't.
465 case X86::VMOVAPDYrr:
467 case X86::VMOVAPSYrr:
469 case X86::VMOVDQAYrr:
471 case X86::VMOVDQUYrr:
473 case X86::VMOVUPDYrr:
475 case X86::VMOVUPSYrr: {
476 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
477 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
479 switch (OutMI.getOpcode()) {
480 default: llvm_unreachable("Invalid opcode");
481 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
482 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
483 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
484 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
485 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
486 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
487 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
488 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
489 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
490 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
491 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
492 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
494 OutMI.setOpcode(NewOpc);
499 case X86::VMOVSSrr: {
500 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
501 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
503 switch (OutMI.getOpcode()) {
504 default: llvm_unreachable("Invalid opcode");
505 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
506 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
508 OutMI.setOpcode(NewOpc);
513 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
514 // inputs modeled as normal uses instead of implicit uses. As such, truncate
515 // off all but the first operand (the callee). FIXME: Change isel.
516 case X86::TAILJMPr64:
517 case X86::TAILJMPr64_REX:
519 case X86::CALL64pcrel32: {
520 unsigned Opcode = OutMI.getOpcode();
521 MCOperand Saved = OutMI.getOperand(0);
523 OutMI.setOpcode(Opcode);
524 OutMI.addOperand(Saved);
529 case X86::EH_RETURN64: {
531 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
535 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
538 case X86::TAILJMPd64: {
540 switch (OutMI.getOpcode()) {
541 default: llvm_unreachable("Invalid opcode");
542 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
544 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
547 MCOperand Saved = OutMI.getOperand(0);
549 OutMI.setOpcode(Opcode);
550 OutMI.addOperand(Saved);
558 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
559 if (!AsmPrinter.getSubtarget().is64Bit()) {
561 switch (OutMI.getOpcode()) {
562 default: llvm_unreachable("Invalid opcode");
563 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
564 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
565 case X86::INC16r: Opcode = X86::INC16r_alt; break;
566 case X86::INC32r: Opcode = X86::INC32r_alt; break;
568 OutMI.setOpcode(Opcode);
572 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
573 // this with an ugly goto in case the resultant OR uses EAX and needs the
575 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
576 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
577 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
578 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
579 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
580 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
581 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
582 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
583 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
585 // Atomic load and store require a separate pseudo-inst because Acquire
586 // implies mayStore and Release implies mayLoad; fix these to regular MOV
588 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
589 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
590 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
591 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
592 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
593 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
594 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
595 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
596 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
597 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
598 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
599 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
600 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
601 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
602 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
603 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
604 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
605 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
606 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
607 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
608 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
609 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
610 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
611 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
612 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
613 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
614 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
615 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
616 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
617 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
618 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
619 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
621 // We don't currently select the correct instruction form for instructions
622 // which have a short %eax, etc. form. Handle this by custom lowering, for
625 // Note, we are currently not handling the following instructions:
626 // MOV64ao8, MOV64o8a
627 // XCHG16ar, XCHG32ar, XCHG64ar
628 case X86::MOV8mr_NOREX:
629 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
630 case X86::MOV8rm_NOREX:
631 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
632 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
633 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
634 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
635 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
637 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
638 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
639 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
640 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
641 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
642 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
643 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
644 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
645 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
646 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
647 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
648 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
649 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
650 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
651 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
652 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
653 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
654 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
655 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
656 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
657 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
658 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
659 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
660 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
661 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
662 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
663 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
664 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
665 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
666 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
667 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
668 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
669 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
670 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
671 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
672 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
674 // Try to shrink some forms of movsx.
675 case X86::MOVSX16rr8:
676 case X86::MOVSX32rr16:
677 case X86::MOVSX64rr32:
678 SimplifyMOVSX(OutMI);
683 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
684 const MachineInstr &MI) {
686 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
687 MI.getOpcode() == X86::TLS_base_addr64;
689 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
691 MCContext &context = OutStreamer->getContext();
694 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
696 MCSymbolRefExpr::VariantKind SRVK;
697 switch (MI.getOpcode()) {
698 case X86::TLS_addr32:
699 case X86::TLS_addr64:
700 SRVK = MCSymbolRefExpr::VK_TLSGD;
702 case X86::TLS_base_addr32:
703 SRVK = MCSymbolRefExpr::VK_TLSLDM;
705 case X86::TLS_base_addr64:
706 SRVK = MCSymbolRefExpr::VK_TLSLD;
709 llvm_unreachable("unexpected opcode");
712 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
713 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
717 LEA.setOpcode(X86::LEA64r);
718 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
719 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
720 LEA.addOperand(MCOperand::createImm(1)); // scale
721 LEA.addOperand(MCOperand::createReg(0)); // index
722 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
723 LEA.addOperand(MCOperand::createReg(0)); // seg
724 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
725 LEA.setOpcode(X86::LEA32r);
726 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
727 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
728 LEA.addOperand(MCOperand::createImm(1)); // scale
729 LEA.addOperand(MCOperand::createReg(0)); // index
730 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
731 LEA.addOperand(MCOperand::createReg(0)); // seg
733 LEA.setOpcode(X86::LEA32r);
734 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
735 LEA.addOperand(MCOperand::createReg(0)); // base
736 LEA.addOperand(MCOperand::createImm(1)); // scale
737 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
738 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
739 LEA.addOperand(MCOperand::createReg(0)); // seg
741 EmitAndCountInstruction(LEA);
744 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
745 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
746 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
749 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
750 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
751 const MCSymbolRefExpr *tlsRef =
752 MCSymbolRefExpr::create(tlsGetAddr,
753 MCSymbolRefExpr::VK_PLT,
756 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
761 /// \brief Emit the optimal amount of multi-byte nops on X86.
762 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
763 // This works only for 64bit. For 32bit we have to do additional checking if
764 // the CPU supports multi-byte nops.
765 assert(Is64Bit && "EmitNops only supports X86-64");
767 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
768 Opc = IndexReg = Displacement = SegmentReg = 0;
769 BaseReg = X86::RAX; ScaleVal = 1;
771 case 0: llvm_unreachable("Zero nops?"); break;
772 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
773 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
774 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
775 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
776 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
777 IndexReg = X86::RAX; break;
778 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
779 IndexReg = X86::RAX; break;
780 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
781 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
782 IndexReg = X86::RAX; break;
783 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
784 IndexReg = X86::RAX; break;
785 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
786 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
789 unsigned NumPrefixes = std::min(NumBytes, 5U);
790 NumBytes -= NumPrefixes;
791 for (unsigned i = 0; i != NumPrefixes; ++i)
792 OS.EmitBytes("\x66");
795 default: llvm_unreachable("Unexpected opcode"); break;
797 OS.EmitInstruction(MCInstBuilder(Opc), STI);
800 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
804 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
805 .addImm(ScaleVal).addReg(IndexReg)
806 .addImm(Displacement).addReg(SegmentReg), STI);
809 } // while (NumBytes)
812 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
813 X86MCInstLower &MCIL) {
814 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
816 StatepointOpers SOpers(&MI);
817 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
818 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
821 // Lower call target and choose correct opcode
822 const MachineOperand &CallTarget = SOpers.getCallTarget();
823 MCOperand CallTargetMCOp;
825 switch (CallTarget.getType()) {
826 case MachineOperand::MO_GlobalAddress:
827 case MachineOperand::MO_ExternalSymbol:
828 CallTargetMCOp = MCIL.LowerSymbolOperand(
829 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
830 CallOpcode = X86::CALL64pcrel32;
831 // Currently, we only support relative addressing with statepoints.
832 // Otherwise, we'll need a scratch register to hold the target
833 // address. You'll fail asserts during load & relocation if this
834 // symbol is to far away. (TODO: support non-relative addressing)
836 case MachineOperand::MO_Immediate:
837 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
838 CallOpcode = X86::CALL64pcrel32;
839 // Currently, we only support relative addressing with statepoints.
840 // Otherwise, we'll need a scratch register to hold the target
841 // immediate. You'll fail asserts during load & relocation if this
842 // address is to far away. (TODO: support non-relative addressing)
844 case MachineOperand::MO_Register:
845 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
846 CallOpcode = X86::CALL64r;
849 llvm_unreachable("Unsupported operand type in statepoint call target");
855 CallInst.setOpcode(CallOpcode);
856 CallInst.addOperand(CallTargetMCOp);
857 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
860 // Record our statepoint node in the same section used by STACKMAP
862 SM.recordStatepoint(MI);
865 void X86AsmPrinter::LowerFAULTING_LOAD_OP(const MachineInstr &MI,
866 X86MCInstLower &MCIL) {
867 // FAULTING_LOAD_OP <def>, <handler label>, <load opcode>, <load operands>
869 unsigned LoadDefRegister = MI.getOperand(0).getReg();
870 MCSymbol *HandlerLabel = MI.getOperand(1).getMCSymbol();
871 unsigned LoadOpcode = MI.getOperand(2).getImm();
872 unsigned LoadOperandsBeginIdx = 3;
874 FM.recordFaultingOp(FaultMaps::FaultingLoad, HandlerLabel);
877 LoadMI.setOpcode(LoadOpcode);
879 if (LoadDefRegister != X86::NoRegister)
880 LoadMI.addOperand(MCOperand::createReg(LoadDefRegister));
882 for (auto I = MI.operands_begin() + LoadOperandsBeginIdx,
883 E = MI.operands_end();
885 if (auto MaybeOperand = MCIL.LowerMachineOperand(&MI, *I))
886 LoadMI.addOperand(MaybeOperand.getValue());
888 OutStreamer->EmitInstruction(LoadMI, getSubtargetInfo());
891 // Lower a stackmap of the form:
892 // <id>, <shadowBytes>, ...
893 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
894 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
895 SM.recordStackMap(MI);
896 unsigned NumShadowBytes = MI.getOperand(1).getImm();
897 SMShadowTracker.reset(NumShadowBytes);
900 // Lower a patchpoint of the form:
901 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
902 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
903 X86MCInstLower &MCIL) {
904 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
906 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
908 SM.recordPatchPoint(MI);
910 PatchPointOpers opers(&MI);
911 unsigned ScratchIdx = opers.getNextScratchIdx();
912 unsigned EncodedBytes = 0;
913 const MachineOperand &CalleeMO =
914 opers.getMetaOper(PatchPointOpers::TargetPos);
916 // Check for null target. If target is non-null (i.e. is non-zero or is
917 // symbolic) then emit a call.
918 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
919 MCOperand CalleeMCOp;
920 switch (CalleeMO.getType()) {
922 /// FIXME: Add a verifier check for bad callee types.
923 llvm_unreachable("Unrecognized callee operand type.");
924 case MachineOperand::MO_Immediate:
925 if (CalleeMO.getImm())
926 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
928 case MachineOperand::MO_ExternalSymbol:
929 case MachineOperand::MO_GlobalAddress:
931 MCIL.LowerSymbolOperand(CalleeMO,
932 MCIL.GetSymbolFromOperand(CalleeMO));
936 // Emit MOV to materialize the target address and the CALL to target.
937 // This is encoded with 12-13 bytes, depending on which register is used.
938 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
939 if (X86II::isX86_64ExtendedReg(ScratchReg))
944 EmitAndCountInstruction(
945 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
946 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
950 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
951 assert(NumBytes >= EncodedBytes &&
952 "Patchpoint can't request size less than the length of a call.");
954 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
958 // Returns instruction preceding MBBI in MachineFunction.
959 // If MBBI is the first instruction of the first basic block, returns null.
960 static MachineBasicBlock::const_iterator
961 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
962 const MachineBasicBlock *MBB = MBBI->getParent();
963 while (MBBI == MBB->begin()) {
964 if (MBB == MBB->getParent()->begin())
966 MBB = MBB->getPrevNode();
972 static const Constant *getConstantFromPool(const MachineInstr &MI,
973 const MachineOperand &Op) {
977 ArrayRef<MachineConstantPoolEntry> Constants =
978 MI.getParent()->getParent()->getConstantPool()->getConstants();
979 const MachineConstantPoolEntry &ConstantEntry =
980 Constants[Op.getIndex()];
982 // Bail if this is a machine constant pool entry, we won't be able to dig out
984 if (ConstantEntry.isMachineConstantPoolEntry())
987 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
988 assert((!C || ConstantEntry.getType() == C->getType()) &&
989 "Expected a constant of the same type!");
993 static std::string getShuffleComment(const MachineOperand &DstOp,
994 const MachineOperand &SrcOp,
995 ArrayRef<int> Mask) {
998 // Compute the name for a register. This is really goofy because we have
999 // multiple instruction printers that could (in theory) use different
1000 // names. Fortunately most people use the ATT style (outside of Windows)
1001 // and they actually agree on register naming here. Ultimately, this is
1002 // a comment, and so its OK if it isn't perfect.
1003 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
1004 return X86ATTInstPrinter::getRegisterName(RegNum);
1007 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1008 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
1010 raw_string_ostream CS(Comment);
1011 CS << DstName << " = ";
1012 bool NeedComma = false;
1014 for (int M : Mask) {
1015 // Wrap up any prior entry...
1016 if (M == SM_SentinelZero && InSrc) {
1025 // Print this shuffle...
1026 if (M == SM_SentinelZero) {
1031 CS << SrcName << "[";
1033 if (M == SM_SentinelUndef)
1046 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1047 X86MCInstLower MCInstLowering(*MF, *this);
1048 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1050 switch (MI->getOpcode()) {
1051 case TargetOpcode::DBG_VALUE:
1052 llvm_unreachable("Should be handled target independently");
1054 // Emit nothing here but a comment if we can.
1055 case X86::Int_MemBarrier:
1056 OutStreamer->emitRawComment("MEMBARRIER");
1060 case X86::EH_RETURN:
1061 case X86::EH_RETURN64: {
1062 // Lower these as normal, but add some comments.
1063 unsigned Reg = MI->getOperand(0).getReg();
1064 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1065 X86ATTInstPrinter::getRegisterName(Reg));
1071 case X86::TAILJMPr64:
1072 case X86::TAILJMPm64:
1073 case X86::TAILJMPd64:
1074 case X86::TAILJMPr64_REX:
1075 case X86::TAILJMPm64_REX:
1076 case X86::TAILJMPd64_REX:
1077 // Lower these as normal, but add some comments.
1078 OutStreamer->AddComment("TAILCALL");
1081 case X86::TLS_addr32:
1082 case X86::TLS_addr64:
1083 case X86::TLS_base_addr32:
1084 case X86::TLS_base_addr64:
1085 return LowerTlsAddr(MCInstLowering, *MI);
1087 case X86::MOVPC32r: {
1088 // This is a pseudo op for a two instruction sequence with a label, which
1095 MCSymbol *PICBase = MF->getPICBaseSymbol();
1096 // FIXME: We would like an efficient form for this, so we don't have to do a
1097 // lot of extra uniquing.
1098 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1099 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1102 OutStreamer->EmitLabel(PICBase);
1105 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1106 .addReg(MI->getOperand(0).getReg()));
1110 case X86::ADD32ri: {
1111 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1112 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1115 // Okay, we have something like:
1116 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1118 // For this, we want to print something like:
1119 // MYGLOBAL + (. - PICBASE)
1120 // However, we can't generate a ".", so just emit a new label here and refer
1122 MCSymbol *DotSym = OutContext.createTempSymbol();
1123 OutStreamer->EmitLabel(DotSym);
1125 // Now that we have emitted the label, lower the complex operand expression.
1126 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1128 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1129 const MCExpr *PICBase =
1130 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1131 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1133 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
1134 DotExpr, OutContext);
1136 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1137 .addReg(MI->getOperand(0).getReg())
1138 .addReg(MI->getOperand(1).getReg())
1142 case TargetOpcode::STATEPOINT:
1143 return LowerSTATEPOINT(*MI, MCInstLowering);
1145 case TargetOpcode::FAULTING_LOAD_OP:
1146 return LowerFAULTING_LOAD_OP(*MI, MCInstLowering);
1148 case TargetOpcode::STACKMAP:
1149 return LowerSTACKMAP(*MI);
1151 case TargetOpcode::PATCHPOINT:
1152 return LowerPATCHPOINT(*MI, MCInstLowering);
1154 case X86::MORESTACK_RET:
1155 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1158 case X86::MORESTACK_RET_RESTORE_R10:
1159 // Return, then restore R10.
1160 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1161 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1166 case X86::SEH_PushReg:
1167 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1170 case X86::SEH_SaveReg:
1171 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1172 MI->getOperand(1).getImm());
1175 case X86::SEH_SaveXMM:
1176 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1177 MI->getOperand(1).getImm());
1180 case X86::SEH_StackAlloc:
1181 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1184 case X86::SEH_SetFrame:
1185 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1186 MI->getOperand(1).getImm());
1189 case X86::SEH_PushFrame:
1190 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1193 case X86::SEH_EndPrologue:
1194 OutStreamer->EmitWinCFIEndProlog();
1197 case X86::SEH_Epilogue: {
1198 MachineBasicBlock::const_iterator MBBI(MI);
1199 // Check if preceded by a call and emit nop if so.
1200 for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1201 // Conservatively assume that pseudo instructions don't emit code and keep
1202 // looking for a call. We may emit an unnecessary nop in some cases.
1203 if (!MBBI->isPseudo()) {
1205 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1212 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1213 // a constant shuffle mask. We won't be able to do this at the MC layer
1214 // because the mask isn't an immediate.
1216 case X86::VPSHUFBrm:
1217 case X86::VPSHUFBYrm: {
1218 if (!OutStreamer->isVerboseAsm())
1220 assert(MI->getNumOperands() > 5 &&
1221 "We should always have at least 5 operands!");
1222 const MachineOperand &DstOp = MI->getOperand(0);
1223 const MachineOperand &SrcOp = MI->getOperand(1);
1224 const MachineOperand &MaskOp = MI->getOperand(5);
1226 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1227 SmallVector<int, 16> Mask;
1228 DecodePSHUFBMask(C, Mask);
1230 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1234 case X86::VPERMILPSrm:
1235 case X86::VPERMILPDrm:
1236 case X86::VPERMILPSYrm:
1237 case X86::VPERMILPDYrm: {
1238 if (!OutStreamer->isVerboseAsm())
1240 assert(MI->getNumOperands() > 5 &&
1241 "We should always have at least 5 operands!");
1242 const MachineOperand &DstOp = MI->getOperand(0);
1243 const MachineOperand &SrcOp = MI->getOperand(1);
1244 const MachineOperand &MaskOp = MI->getOperand(5);
1246 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1247 SmallVector<int, 16> Mask;
1248 DecodeVPERMILPMask(C, Mask);
1250 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1255 // For loads from a constant pool to a vector register, print the constant
1258 case X86::VMOVAPDrm:
1259 case X86::VMOVAPDYrm:
1261 case X86::VMOVUPDrm:
1262 case X86::VMOVUPDYrm:
1264 case X86::VMOVAPSrm:
1265 case X86::VMOVAPSYrm:
1267 case X86::VMOVUPSrm:
1268 case X86::VMOVUPSYrm:
1270 case X86::VMOVDQArm:
1271 case X86::VMOVDQAYrm:
1273 case X86::VMOVDQUrm:
1274 case X86::VMOVDQUYrm:
1275 if (!OutStreamer->isVerboseAsm())
1277 if (MI->getNumOperands() > 4)
1278 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1279 std::string Comment;
1280 raw_string_ostream CS(Comment);
1281 const MachineOperand &DstOp = MI->getOperand(0);
1282 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1283 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1285 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1288 if (CDS->getElementType()->isIntegerTy())
1289 CS << CDS->getElementAsInteger(i);
1290 else if (CDS->getElementType()->isFloatTy())
1291 CS << CDS->getElementAsFloat(i);
1292 else if (CDS->getElementType()->isDoubleTy())
1293 CS << CDS->getElementAsDouble(i);
1298 OutStreamer->AddComment(CS.str());
1299 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1301 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1304 Constant *COp = CV->getOperand(i);
1305 if (isa<UndefValue>(COp)) {
1307 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1308 CS << CI->getZExtValue();
1309 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1310 SmallString<32> Str;
1311 CF->getValueAPF().toString(Str);
1318 OutStreamer->AddComment(CS.str());
1325 MCInstLowering.Lower(MI, TmpInst);
1327 // Stackmap shadows cannot include branch targets, so we can count the bytes
1328 // in a call towards the shadow, but must ensure that the no thread returns
1329 // in to the stackmap shadow. The only way to achieve this is if the call
1330 // is at the end of the shadow.
1332 // Count then size of the call towards the shadow
1333 SMShadowTracker.count(TmpInst, getSubtargetInfo());
1334 // Then flush the shadow so that we fill with nops before the call, not
1336 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1337 // Then emit the call
1338 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1342 EmitAndCountInstruction(TmpInst);