1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
22 // FIXME: This should move to a header.
26 reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch.
27 reloc_pcrel_1byte // 8-bit pcrel, e.g. branch_1
33 class X86MCCodeEmitter : public MCCodeEmitter {
34 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
35 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
36 const TargetMachine &TM;
37 const TargetInstrInfo &TII;
40 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
41 : TM(tm), TII(*TM.getInstrInfo()) {
42 Is64BitMode = is64Bit;
45 ~X86MCCodeEmitter() {}
47 unsigned getNumFixupKinds() const {
51 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
52 const static MCFixupKindInfo Infos[] = {
53 { "reloc_pcrel_4byte", 0, 4 * 8 },
54 { "reloc_pcrel_1byte", 0, 1 * 8 }
57 if (Kind < FirstTargetFixupKind)
58 return MCCodeEmitter::getFixupKindInfo(Kind);
60 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
62 return Infos[Kind - FirstTargetFixupKind];
65 static unsigned GetX86RegNum(const MCOperand &MO) {
66 return X86RegisterInfo::getX86RegNum(MO.getReg());
69 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
74 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
75 raw_ostream &OS) const {
76 // Output the constant in little endian byte order.
77 for (unsigned i = 0; i != Size; ++i) {
78 EmitByte(Val & 255, CurByte, OS);
83 void EmitImmediate(const MCOperand &Disp,
84 unsigned ImmSize, MCFixupKind FixupKind,
85 unsigned &CurByte, raw_ostream &OS,
86 SmallVectorImpl<MCFixup> &Fixups) const;
88 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
90 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
91 return RM | (RegOpcode << 3) | (Mod << 6);
94 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
95 unsigned &CurByte, raw_ostream &OS) const {
96 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
99 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
100 unsigned &CurByte, raw_ostream &OS) const {
101 // SIB byte is in the same format as the ModRMByte.
102 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
106 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
107 unsigned RegOpcodeField,
108 unsigned &CurByte, raw_ostream &OS,
109 SmallVectorImpl<MCFixup> &Fixups) const;
111 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
112 SmallVectorImpl<MCFixup> &Fixups) const;
116 } // end anonymous namespace
119 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
121 return new X86MCCodeEmitter(TM, false);
124 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
126 return new X86MCCodeEmitter(TM, true);
130 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
131 /// sign-extended field.
132 static bool isDisp8(int Value) {
133 return Value == (signed char)Value;
136 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
137 /// in an instruction with the specified TSFlags.
138 static MCFixupKind getImmFixupKind(unsigned TSFlags) {
139 unsigned Size = X86II::getSizeOfImm(TSFlags);
140 bool isPCRel = X86II::isImmPCRel(TSFlags);
142 // FIXME: Pass in the relocation type, this is just a hack..
144 default: assert(0 && "Unknown immediate size");
145 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
146 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
147 case 2: assert(!isPCRel); return FK_Data_2;
148 case 8: assert(!isPCRel); return FK_Data_8;
153 void X86MCCodeEmitter::
154 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
155 unsigned &CurByte, raw_ostream &OS,
156 SmallVectorImpl<MCFixup> &Fixups) const {
157 // If this is a simple integer displacement that doesn't require a relocation,
159 if (DispOp.isImm()) {
160 EmitConstant(DispOp.getImm(), Size, CurByte, OS);
164 // Emit a symbolic constant as a fixup and 4 zeros.
165 Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(), FixupKind));
166 EmitConstant(0, Size, CurByte, OS);
170 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
171 unsigned RegOpcodeField,
174 SmallVectorImpl<MCFixup> &Fixups) const{
175 const MCOperand &Disp = MI.getOperand(Op+3);
176 const MCOperand &Base = MI.getOperand(Op);
177 const MCOperand &Scale = MI.getOperand(Op+1);
178 const MCOperand &IndexReg = MI.getOperand(Op+2);
179 unsigned BaseReg = Base.getReg();
180 unsigned BaseRegNo = -1U;
181 if (BaseReg != 0 && BaseReg != X86::RIP)
182 BaseRegNo = GetX86RegNum(Base);
184 // Determine whether a SIB byte is needed.
185 // If no BaseReg, issue a RIP relative instruction only if the MCE can
186 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
187 // 2-7) and absolute references.
189 if (// The SIB byte must be used if there is an index register.
190 IndexReg.getReg() == 0 &&
191 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
192 // encode to an R/M value of 4, which indicates that a SIB byte is
194 BaseRegNo != N86::ESP &&
195 // If there is no base register and we're in 64-bit mode, we need a SIB
196 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
197 (!Is64BitMode || BaseReg != 0)) {
199 if (BaseReg == 0 || // [disp32] in X86-32 mode
200 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
201 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
202 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
206 // If the base is not EBP/ESP and there is no displacement, use simple
207 // indirect register encoding, this handles addresses like [EAX]. The
208 // encoding for [EBP] with no displacement means [disp32] so we handle it
209 // by emitting a displacement of 0 below.
210 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
211 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
215 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
216 if (Disp.isImm() && isDisp8(Disp.getImm())) {
217 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
218 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
222 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
223 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
224 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
228 // We need a SIB byte, so start by outputting the ModR/M byte first
229 assert(IndexReg.getReg() != X86::ESP &&
230 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
232 bool ForceDisp32 = false;
233 bool ForceDisp8 = false;
235 // If there is no base register, we emit the special case SIB byte with
236 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
237 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
239 } else if (!Disp.isImm()) {
240 // Emit the normal disp32 encoding.
241 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
243 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
244 // Emit no displacement ModR/M byte
245 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
246 } else if (isDisp8(Disp.getImm())) {
247 // Emit the disp8 encoding.
248 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
249 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
251 // Emit the normal disp32 encoding.
252 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
255 // Calculate what the SS field value should be...
256 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
257 unsigned SS = SSTable[Scale.getImm()];
260 // Handle the SIB byte for the case where there is no base, see Intel
261 // Manual 2A, table 2-7. The displacement has already been output.
263 if (IndexReg.getReg())
264 IndexRegNo = GetX86RegNum(IndexReg);
265 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
267 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
270 if (IndexReg.getReg())
271 IndexRegNo = GetX86RegNum(IndexReg);
273 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
274 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
277 // Do we need to output a displacement?
279 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
280 else if (ForceDisp32 || Disp.getImm() != 0)
281 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
284 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
285 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
286 /// size, and 3) use of X86-64 extended registers.
287 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
288 const TargetInstrDesc &Desc) {
289 // Pseudo instructions shouldn't get here.
290 assert((TSFlags & X86II::FormMask) != X86II::Pseudo &&
291 "Can't encode pseudo instrs");
294 if (TSFlags & X86II::REX_W)
297 if (MI.getNumOperands() == 0) return REX;
299 unsigned NumOps = MI.getNumOperands();
300 // FIXME: MCInst should explicitize the two-addrness.
301 bool isTwoAddr = NumOps > 1 &&
302 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
304 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
305 unsigned i = isTwoAddr ? 1 : 0;
306 for (; i != NumOps; ++i) {
307 const MCOperand &MO = MI.getOperand(i);
308 if (!MO.isReg()) continue;
309 unsigned Reg = MO.getReg();
310 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
311 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
312 // that returns non-zero.
317 switch (TSFlags & X86II::FormMask) {
318 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
319 case X86II::MRMSrcReg:
320 if (MI.getOperand(0).isReg() &&
321 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
323 i = isTwoAddr ? 2 : 1;
324 for (; i != NumOps; ++i) {
325 const MCOperand &MO = MI.getOperand(i);
326 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
330 case X86II::MRMSrcMem: {
331 if (MI.getOperand(0).isReg() &&
332 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
335 i = isTwoAddr ? 2 : 1;
336 for (; i != NumOps; ++i) {
337 const MCOperand &MO = MI.getOperand(i);
339 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
346 case X86II::MRM0m: case X86II::MRM1m:
347 case X86II::MRM2m: case X86II::MRM3m:
348 case X86II::MRM4m: case X86II::MRM5m:
349 case X86II::MRM6m: case X86II::MRM7m:
350 case X86II::MRMDestMem: {
351 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
352 i = isTwoAddr ? 1 : 0;
353 if (NumOps > e && MI.getOperand(e).isReg() &&
354 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
357 for (; i != e; ++i) {
358 const MCOperand &MO = MI.getOperand(i);
360 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
368 if (MI.getOperand(0).isReg() &&
369 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
371 i = isTwoAddr ? 2 : 1;
372 for (unsigned e = NumOps; i != e; ++i) {
373 const MCOperand &MO = MI.getOperand(i);
374 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
382 void X86MCCodeEmitter::
383 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
384 SmallVectorImpl<MCFixup> &Fixups) const {
385 unsigned Opcode = MI.getOpcode();
386 const TargetInstrDesc &Desc = TII.get(Opcode);
387 unsigned TSFlags = Desc.TSFlags;
389 // Keep track of the current byte being emitted.
390 unsigned CurByte = 0;
392 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
393 // in order to provide diffability.
395 // Emit the lock opcode prefix as needed.
396 if (TSFlags & X86II::LOCK)
397 EmitByte(0xF0, CurByte, OS);
399 // Emit segment override opcode prefix as needed.
400 switch (TSFlags & X86II::SegOvrMask) {
401 default: assert(0 && "Invalid segment!");
402 case 0: break; // No segment override!
404 EmitByte(0x64, CurByte, OS);
407 EmitByte(0x65, CurByte, OS);
411 // Emit the repeat opcode prefix as needed.
412 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
413 EmitByte(0xF3, CurByte, OS);
415 // Emit the operand size opcode prefix as needed.
416 if (TSFlags & X86II::OpSize)
417 EmitByte(0x66, CurByte, OS);
419 // Emit the address size opcode prefix as needed.
420 if (TSFlags & X86II::AdSize)
421 EmitByte(0x67, CurByte, OS);
423 bool Need0FPrefix = false;
424 switch (TSFlags & X86II::Op0Mask) {
425 default: assert(0 && "Invalid prefix!");
426 case 0: break; // No prefix!
427 case X86II::REP: break; // already handled.
428 case X86II::TB: // Two-byte opcode prefix
429 case X86II::T8: // 0F 38
430 case X86II::TA: // 0F 3A
433 case X86II::TF: // F2 0F 38
434 EmitByte(0xF2, CurByte, OS);
437 case X86II::XS: // F3 0F
438 EmitByte(0xF3, CurByte, OS);
441 case X86II::XD: // F2 0F
442 EmitByte(0xF2, CurByte, OS);
445 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
446 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
447 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
448 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
449 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
450 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
451 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
452 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
455 // Handle REX prefix.
456 // FIXME: Can this come before F2 etc to simplify emission?
458 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
459 EmitByte(0x40 | REX, CurByte, OS);
462 // 0x0F escape code must be emitted just before the opcode.
464 EmitByte(0x0F, CurByte, OS);
466 // FIXME: Pull this up into previous switch if REX can be moved earlier.
467 switch (TSFlags & X86II::Op0Mask) {
468 case X86II::TF: // F2 0F 38
469 case X86II::T8: // 0F 38
470 EmitByte(0x38, CurByte, OS);
472 case X86II::TA: // 0F 3A
473 EmitByte(0x3A, CurByte, OS);
477 // If this is a two-address instruction, skip one of the register operands.
478 unsigned NumOps = Desc.getNumOperands();
480 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
482 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
483 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
486 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
487 switch (TSFlags & X86II::FormMask) {
488 case X86II::MRMInitReg:
489 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
490 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
491 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
493 EmitByte(BaseOpcode, CurByte, OS);
496 case X86II::AddRegFrm:
497 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
500 case X86II::MRMDestReg:
501 EmitByte(BaseOpcode, CurByte, OS);
502 EmitRegModRMByte(MI.getOperand(CurOp),
503 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
507 case X86II::MRMDestMem:
508 EmitByte(BaseOpcode, CurByte, OS);
509 EmitMemModRMByte(MI, CurOp,
510 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
511 CurByte, OS, Fixups);
512 CurOp += X86AddrNumOperands + 1;
515 case X86II::MRMSrcReg:
516 EmitByte(BaseOpcode, CurByte, OS);
517 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
522 case X86II::MRMSrcMem: {
523 EmitByte(BaseOpcode, CurByte, OS);
525 // FIXME: Maybe lea should have its own form? This is a horrible hack.
527 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
528 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
529 AddrOperands = X86AddrNumOperands - 1; // No segment register
531 AddrOperands = X86AddrNumOperands;
533 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
534 CurByte, OS, Fixups);
535 CurOp += AddrOperands + 1;
539 case X86II::MRM0r: case X86II::MRM1r:
540 case X86II::MRM2r: case X86II::MRM3r:
541 case X86II::MRM4r: case X86II::MRM5r:
542 case X86II::MRM6r: case X86II::MRM7r:
543 EmitByte(BaseOpcode, CurByte, OS);
545 // Special handling of lfence, mfence, monitor, and mwait.
546 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
547 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
548 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
549 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r,
550 Opcode == X86::MWAIT),
553 EmitRegModRMByte(MI.getOperand(CurOp++),
554 (TSFlags & X86II::FormMask)-X86II::MRM0r,
558 case X86II::MRM0m: case X86II::MRM1m:
559 case X86II::MRM2m: case X86II::MRM3m:
560 case X86II::MRM4m: case X86II::MRM5m:
561 case X86II::MRM6m: case X86II::MRM7m:
562 EmitByte(BaseOpcode, CurByte, OS);
563 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
564 CurByte, OS, Fixups);
565 CurOp += X86AddrNumOperands;
568 EmitByte(BaseOpcode, CurByte, OS);
569 EmitByte(0xC1, CurByte, OS);
572 EmitByte(BaseOpcode, CurByte, OS);
573 EmitByte(0xC8, CurByte, OS);
576 EmitByte(BaseOpcode, CurByte, OS);
577 EmitByte(0xC9, CurByte, OS);
580 EmitByte(BaseOpcode, CurByte, OS);
581 EmitByte(0xE8, CurByte, OS);
584 EmitByte(BaseOpcode, CurByte, OS);
585 EmitByte(0xF0, CurByte, OS);
589 // If there is a remaining operand, it must be a trailing immediate. Emit it
590 // according to the right size for the instruction.
591 // FIXME: This should pass in whether the value is pc relative or not. This
592 // information should be aquired from TSFlags as well.
594 EmitImmediate(MI.getOperand(CurOp++),
595 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
596 CurByte, OS, Fixups);
600 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
601 errs() << "Cannot encode all operands of: ";