1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8 },
47 { "reloc_pcrel_1byte", 0, 1 * 8 },
48 { "reloc_riprel_4byte", 0, 4 * 8 }
51 if (Kind < FirstTargetFixupKind)
52 return MCCodeEmitter::getFixupKindInfo(Kind);
54 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
56 return Infos[Kind - FirstTargetFixupKind];
59 static unsigned GetX86RegNum(const MCOperand &MO) {
60 return X86RegisterInfo::getX86RegNum(MO.getReg());
63 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
68 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
69 raw_ostream &OS) const {
70 // Output the constant in little endian byte order.
71 for (unsigned i = 0; i != Size; ++i) {
72 EmitByte(Val & 255, CurByte, OS);
77 void EmitImmediate(const MCOperand &Disp,
78 unsigned ImmSize, MCFixupKind FixupKind,
79 unsigned &CurByte, raw_ostream &OS,
80 SmallVectorImpl<MCFixup> &Fixups,
81 int ImmOffset = 0) const;
83 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
85 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
86 return RM | (RegOpcode << 3) | (Mod << 6);
89 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
90 unsigned &CurByte, raw_ostream &OS) const {
91 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
94 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
95 unsigned &CurByte, raw_ostream &OS) const {
96 // SIB byte is in the same format as the ModRMByte.
97 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
101 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
102 unsigned RegOpcodeField,
103 unsigned TSFlags, unsigned &CurByte, raw_ostream &OS,
104 SmallVectorImpl<MCFixup> &Fixups) const;
106 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
107 SmallVectorImpl<MCFixup> &Fixups) const;
111 } // end anonymous namespace
114 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
117 return new X86MCCodeEmitter(TM, Ctx, false);
120 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
123 return new X86MCCodeEmitter(TM, Ctx, true);
127 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
128 /// sign-extended field.
129 static bool isDisp8(int Value) {
130 return Value == (signed char)Value;
133 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
134 /// in an instruction with the specified TSFlags.
135 static MCFixupKind getImmFixupKind(unsigned TSFlags) {
136 unsigned Size = X86II::getSizeOfImm(TSFlags);
137 bool isPCRel = X86II::isImmPCRel(TSFlags);
140 default: assert(0 && "Unknown immediate size");
141 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
142 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
143 case 2: assert(!isPCRel); return FK_Data_2;
144 case 8: assert(!isPCRel); return FK_Data_8;
149 void X86MCCodeEmitter::
150 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
151 unsigned &CurByte, raw_ostream &OS,
152 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
153 // If this is a simple integer displacement that doesn't require a relocation,
155 if (DispOp.isImm()) {
156 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
160 // If we have an immoffset, add it to the expression.
161 const MCExpr *Expr = DispOp.getExpr();
163 Expr = MCBinaryExpr::CreateAdd(Expr,MCConstantExpr::Create(ImmOffset, Ctx),
166 // Emit a symbolic constant as a fixup and 4 zeros.
167 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
168 EmitConstant(0, Size, CurByte, OS);
172 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
173 unsigned RegOpcodeField,
174 unsigned TSFlags, unsigned &CurByte,
176 SmallVectorImpl<MCFixup> &Fixups) const{
177 const MCOperand &Disp = MI.getOperand(Op+3);
178 const MCOperand &Base = MI.getOperand(Op);
179 const MCOperand &Scale = MI.getOperand(Op+1);
180 const MCOperand &IndexReg = MI.getOperand(Op+2);
181 unsigned BaseReg = Base.getReg();
183 // Handle %rip relative addressing.
184 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
185 assert(IndexReg.getReg() == 0 && Is64BitMode &&
186 "Invalid rip-relative address");
187 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
189 // rip-relative addressing is actually relative to the *next* instruction.
190 // Since an immediate can follow the mod/rm byte for an instruction, this
191 // means that we need to bias the immediate field of the instruction with
192 // the size of the immediate field. If we have this case, add it into the
193 // expression to emit.
194 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
195 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_riprel_4byte),
196 CurByte, OS, Fixups, -ImmSize);
200 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
202 // Determine whether a SIB byte is needed.
203 // If no BaseReg, issue a RIP relative instruction only if the MCE can
204 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
205 // 2-7) and absolute references.
207 if (// The SIB byte must be used if there is an index register.
208 IndexReg.getReg() == 0 &&
209 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
210 // encode to an R/M value of 4, which indicates that a SIB byte is
212 BaseRegNo != N86::ESP &&
213 // If there is no base register and we're in 64-bit mode, we need a SIB
214 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
215 (!Is64BitMode || BaseReg != 0)) {
217 if (BaseReg == 0) { // [disp32] in X86-32 mode
218 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
219 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
223 // If the base is not EBP/ESP and there is no displacement, use simple
224 // indirect register encoding, this handles addresses like [EAX]. The
225 // encoding for [EBP] with no displacement means [disp32] so we handle it
226 // by emitting a displacement of 0 below.
227 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
228 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
232 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
233 if (Disp.isImm() && isDisp8(Disp.getImm())) {
234 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
235 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
239 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
240 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
241 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
245 // We need a SIB byte, so start by outputting the ModR/M byte first
246 assert(IndexReg.getReg() != X86::ESP &&
247 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
249 bool ForceDisp32 = false;
250 bool ForceDisp8 = false;
252 // If there is no base register, we emit the special case SIB byte with
253 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
254 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
256 } else if (!Disp.isImm()) {
257 // Emit the normal disp32 encoding.
258 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
260 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
261 // Emit no displacement ModR/M byte
262 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
263 } else if (isDisp8(Disp.getImm())) {
264 // Emit the disp8 encoding.
265 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
266 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
268 // Emit the normal disp32 encoding.
269 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
272 // Calculate what the SS field value should be...
273 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
274 unsigned SS = SSTable[Scale.getImm()];
277 // Handle the SIB byte for the case where there is no base, see Intel
278 // Manual 2A, table 2-7. The displacement has already been output.
280 if (IndexReg.getReg())
281 IndexRegNo = GetX86RegNum(IndexReg);
282 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
284 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
287 if (IndexReg.getReg())
288 IndexRegNo = GetX86RegNum(IndexReg);
290 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
291 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
294 // Do we need to output a displacement?
296 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
297 else if (ForceDisp32 || Disp.getImm() != 0)
298 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
301 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
302 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
303 /// size, and 3) use of X86-64 extended registers.
304 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
305 const TargetInstrDesc &Desc) {
306 // Pseudo instructions shouldn't get here.
307 assert((TSFlags & X86II::FormMask) != X86II::Pseudo &&
308 "Can't encode pseudo instrs");
311 if (TSFlags & X86II::REX_W)
314 if (MI.getNumOperands() == 0) return REX;
316 unsigned NumOps = MI.getNumOperands();
317 // FIXME: MCInst should explicitize the two-addrness.
318 bool isTwoAddr = NumOps > 1 &&
319 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
321 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
322 unsigned i = isTwoAddr ? 1 : 0;
323 for (; i != NumOps; ++i) {
324 const MCOperand &MO = MI.getOperand(i);
325 if (!MO.isReg()) continue;
326 unsigned Reg = MO.getReg();
327 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
328 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
329 // that returns non-zero.
334 switch (TSFlags & X86II::FormMask) {
335 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
336 case X86II::MRMSrcReg:
337 if (MI.getOperand(0).isReg() &&
338 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
340 i = isTwoAddr ? 2 : 1;
341 for (; i != NumOps; ++i) {
342 const MCOperand &MO = MI.getOperand(i);
343 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
347 case X86II::MRMSrcMem: {
348 if (MI.getOperand(0).isReg() &&
349 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
352 i = isTwoAddr ? 2 : 1;
353 for (; i != NumOps; ++i) {
354 const MCOperand &MO = MI.getOperand(i);
356 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
363 case X86II::MRM0m: case X86II::MRM1m:
364 case X86II::MRM2m: case X86II::MRM3m:
365 case X86II::MRM4m: case X86II::MRM5m:
366 case X86II::MRM6m: case X86II::MRM7m:
367 case X86II::MRMDestMem: {
368 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
369 i = isTwoAddr ? 1 : 0;
370 if (NumOps > e && MI.getOperand(e).isReg() &&
371 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
374 for (; i != e; ++i) {
375 const MCOperand &MO = MI.getOperand(i);
377 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
385 if (MI.getOperand(0).isReg() &&
386 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
388 i = isTwoAddr ? 2 : 1;
389 for (unsigned e = NumOps; i != e; ++i) {
390 const MCOperand &MO = MI.getOperand(i);
391 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
399 void X86MCCodeEmitter::
400 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
401 SmallVectorImpl<MCFixup> &Fixups) const {
402 unsigned Opcode = MI.getOpcode();
403 const TargetInstrDesc &Desc = TII.get(Opcode);
404 unsigned TSFlags = Desc.TSFlags;
406 // Keep track of the current byte being emitted.
407 unsigned CurByte = 0;
409 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
410 // in order to provide diffability.
412 // Emit the lock opcode prefix as needed.
413 if (TSFlags & X86II::LOCK)
414 EmitByte(0xF0, CurByte, OS);
416 // Emit segment override opcode prefix as needed.
417 switch (TSFlags & X86II::SegOvrMask) {
418 default: assert(0 && "Invalid segment!");
419 case 0: break; // No segment override!
421 EmitByte(0x64, CurByte, OS);
424 EmitByte(0x65, CurByte, OS);
428 // Emit the repeat opcode prefix as needed.
429 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
430 EmitByte(0xF3, CurByte, OS);
432 // Emit the operand size opcode prefix as needed.
433 if (TSFlags & X86II::OpSize)
434 EmitByte(0x66, CurByte, OS);
436 // Emit the address size opcode prefix as needed.
437 if (TSFlags & X86II::AdSize)
438 EmitByte(0x67, CurByte, OS);
440 bool Need0FPrefix = false;
441 switch (TSFlags & X86II::Op0Mask) {
442 default: assert(0 && "Invalid prefix!");
443 case 0: break; // No prefix!
444 case X86II::REP: break; // already handled.
445 case X86II::TB: // Two-byte opcode prefix
446 case X86II::T8: // 0F 38
447 case X86II::TA: // 0F 3A
450 case X86II::TF: // F2 0F 38
451 EmitByte(0xF2, CurByte, OS);
454 case X86II::XS: // F3 0F
455 EmitByte(0xF3, CurByte, OS);
458 case X86II::XD: // F2 0F
459 EmitByte(0xF2, CurByte, OS);
462 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
463 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
464 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
465 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
466 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
467 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
468 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
469 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
472 // Handle REX prefix.
473 // FIXME: Can this come before F2 etc to simplify emission?
475 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
476 EmitByte(0x40 | REX, CurByte, OS);
479 // 0x0F escape code must be emitted just before the opcode.
481 EmitByte(0x0F, CurByte, OS);
483 // FIXME: Pull this up into previous switch if REX can be moved earlier.
484 switch (TSFlags & X86II::Op0Mask) {
485 case X86II::TF: // F2 0F 38
486 case X86II::T8: // 0F 38
487 EmitByte(0x38, CurByte, OS);
489 case X86II::TA: // 0F 3A
490 EmitByte(0x3A, CurByte, OS);
494 // If this is a two-address instruction, skip one of the register operands.
495 unsigned NumOps = Desc.getNumOperands();
497 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
499 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
500 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
503 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
504 switch (TSFlags & X86II::FormMask) {
505 case X86II::MRMInitReg:
506 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
507 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
508 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
510 EmitByte(BaseOpcode, CurByte, OS);
513 case X86II::AddRegFrm:
514 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
517 case X86II::MRMDestReg:
518 EmitByte(BaseOpcode, CurByte, OS);
519 EmitRegModRMByte(MI.getOperand(CurOp),
520 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
524 case X86II::MRMDestMem:
525 EmitByte(BaseOpcode, CurByte, OS);
526 EmitMemModRMByte(MI, CurOp,
527 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
528 TSFlags, CurByte, OS, Fixups);
529 CurOp += X86AddrNumOperands + 1;
532 case X86II::MRMSrcReg:
533 EmitByte(BaseOpcode, CurByte, OS);
534 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
539 case X86II::MRMSrcMem: {
540 EmitByte(BaseOpcode, CurByte, OS);
542 // FIXME: Maybe lea should have its own form? This is a horrible hack.
544 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
545 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
546 AddrOperands = X86AddrNumOperands - 1; // No segment register
548 AddrOperands = X86AddrNumOperands;
550 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
551 TSFlags, CurByte, OS, Fixups);
552 CurOp += AddrOperands + 1;
556 case X86II::MRM0r: case X86II::MRM1r:
557 case X86II::MRM2r: case X86II::MRM3r:
558 case X86II::MRM4r: case X86II::MRM5r:
559 case X86II::MRM6r: case X86II::MRM7r:
560 EmitByte(BaseOpcode, CurByte, OS);
561 EmitRegModRMByte(MI.getOperand(CurOp++),
562 (TSFlags & X86II::FormMask)-X86II::MRM0r,
565 case X86II::MRM0m: case X86II::MRM1m:
566 case X86II::MRM2m: case X86II::MRM3m:
567 case X86II::MRM4m: case X86II::MRM5m:
568 case X86II::MRM6m: case X86II::MRM7m:
569 EmitByte(BaseOpcode, CurByte, OS);
570 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
571 TSFlags, CurByte, OS, Fixups);
572 CurOp += X86AddrNumOperands;
575 EmitByte(BaseOpcode, CurByte, OS);
576 EmitByte(0xC1, CurByte, OS);
579 EmitByte(BaseOpcode, CurByte, OS);
580 EmitByte(0xC2, CurByte, OS);
583 EmitByte(BaseOpcode, CurByte, OS);
584 EmitByte(0xC3, CurByte, OS);
587 EmitByte(BaseOpcode, CurByte, OS);
588 EmitByte(0xC4, CurByte, OS);
591 EmitByte(BaseOpcode, CurByte, OS);
592 EmitByte(0xC8, CurByte, OS);
595 EmitByte(BaseOpcode, CurByte, OS);
596 EmitByte(0xC9, CurByte, OS);
599 EmitByte(BaseOpcode, CurByte, OS);
600 EmitByte(0xE8, CurByte, OS);
603 EmitByte(BaseOpcode, CurByte, OS);
604 EmitByte(0xF0, CurByte, OS);
607 EmitByte(BaseOpcode, CurByte, OS);
608 EmitByte(0xF8, CurByte, OS);
611 EmitByte(BaseOpcode, CurByte, OS);
612 EmitByte(0xF9, CurByte, OS);
616 // If there is a remaining operand, it must be a trailing immediate. Emit it
617 // according to the right size for the instruction.
618 // FIXME: This should pass in whether the value is pc relative or not. This
619 // information should be aquired from TSFlags as well.
621 EmitImmediate(MI.getOperand(CurOp++),
622 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
623 CurByte, OS, Fixups);
627 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
628 errs() << "Cannot encode all operands of: ";