1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8 },
47 { "reloc_pcrel_1byte", 0, 1 * 8 },
48 { "reloc_riprel_4byte", 0, 4 * 8 },
49 { "reloc_riprel_4byte_movq_load", 0, 4 * 8 }
52 if (Kind < FirstTargetFixupKind)
53 return MCCodeEmitter::getFixupKindInfo(Kind);
55 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
57 return Infos[Kind - FirstTargetFixupKind];
60 static unsigned GetX86RegNum(const MCOperand &MO) {
61 return X86RegisterInfo::getX86RegNum(MO.getReg());
64 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
69 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
70 raw_ostream &OS) const {
71 // Output the constant in little endian byte order.
72 for (unsigned i = 0; i != Size; ++i) {
73 EmitByte(Val & 255, CurByte, OS);
78 void EmitImmediate(const MCOperand &Disp,
79 unsigned ImmSize, MCFixupKind FixupKind,
80 unsigned &CurByte, raw_ostream &OS,
81 SmallVectorImpl<MCFixup> &Fixups,
82 int ImmOffset = 0) const;
84 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
86 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
87 return RM | (RegOpcode << 3) | (Mod << 6);
90 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
91 unsigned &CurByte, raw_ostream &OS) const {
92 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
95 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
96 unsigned &CurByte, raw_ostream &OS) const {
97 // SIB byte is in the same format as the ModRMByte.
98 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
102 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
103 unsigned RegOpcodeField,
104 unsigned TSFlags, unsigned &CurByte, raw_ostream &OS,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
108 SmallVectorImpl<MCFixup> &Fixups) const;
112 } // end anonymous namespace
115 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
118 return new X86MCCodeEmitter(TM, Ctx, false);
121 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
124 return new X86MCCodeEmitter(TM, Ctx, true);
128 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
129 /// sign-extended field.
130 static bool isDisp8(int Value) {
131 return Value == (signed char)Value;
134 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
135 /// in an instruction with the specified TSFlags.
136 static MCFixupKind getImmFixupKind(unsigned TSFlags) {
137 unsigned Size = X86II::getSizeOfImm(TSFlags);
138 bool isPCRel = X86II::isImmPCRel(TSFlags);
141 default: assert(0 && "Unknown immediate size");
142 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
143 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
144 case 2: assert(!isPCRel); return FK_Data_2;
145 case 8: assert(!isPCRel); return FK_Data_8;
150 void X86MCCodeEmitter::
151 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
152 unsigned &CurByte, raw_ostream &OS,
153 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
154 // If this is a simple integer displacement that doesn't require a relocation,
156 if (DispOp.isImm()) {
157 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
159 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
163 // If we have an immoffset, add it to the expression.
164 const MCExpr *Expr = DispOp.getExpr();
166 // If the fixup is pc-relative, we need to bias the value to be relative to
167 // the start of the field, not the end of the field.
168 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
169 FixupKind == MCFixupKind(X86::reloc_riprel_4byte))
171 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
175 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
178 // Emit a symbolic constant as a fixup and 4 zeros.
179 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
180 EmitConstant(0, Size, CurByte, OS);
184 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
185 unsigned RegOpcodeField,
186 unsigned TSFlags, unsigned &CurByte,
188 SmallVectorImpl<MCFixup> &Fixups) const{
189 const MCOperand &Disp = MI.getOperand(Op+3);
190 const MCOperand &Base = MI.getOperand(Op);
191 const MCOperand &Scale = MI.getOperand(Op+1);
192 const MCOperand &IndexReg = MI.getOperand(Op+2);
193 unsigned BaseReg = Base.getReg();
195 // Handle %rip relative addressing.
196 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
197 assert(IndexReg.getReg() == 0 && Is64BitMode &&
198 "Invalid rip-relative address");
199 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
201 unsigned FixupKind = X86::reloc_riprel_4byte;
203 // movq loads are handled with a special relocation form which allows the
204 // linker to eliminate some loads for GOT references which end up in the
205 // same linkage unit.
206 if (MI.getOpcode() == X86::MOV64rm_TC)
207 FixupKind = X86::reloc_riprel_4byte_movq_load;
209 // rip-relative addressing is actually relative to the *next* instruction.
210 // Since an immediate can follow the mod/rm byte for an instruction, this
211 // means that we need to bias the immediate field of the instruction with
212 // the size of the immediate field. If we have this case, add it into the
213 // expression to emit.
214 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
216 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
217 CurByte, OS, Fixups, -ImmSize);
221 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
223 // Determine whether a SIB byte is needed.
224 // If no BaseReg, issue a RIP relative instruction only if the MCE can
225 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
226 // 2-7) and absolute references.
228 if (// The SIB byte must be used if there is an index register.
229 IndexReg.getReg() == 0 &&
230 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
231 // encode to an R/M value of 4, which indicates that a SIB byte is
233 BaseRegNo != N86::ESP &&
234 // If there is no base register and we're in 64-bit mode, we need a SIB
235 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
236 (!Is64BitMode || BaseReg != 0)) {
238 if (BaseReg == 0) { // [disp32] in X86-32 mode
239 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
240 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
244 // If the base is not EBP/ESP and there is no displacement, use simple
245 // indirect register encoding, this handles addresses like [EAX]. The
246 // encoding for [EBP] with no displacement means [disp32] so we handle it
247 // by emitting a displacement of 0 below.
248 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
249 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
253 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
254 if (Disp.isImm() && isDisp8(Disp.getImm())) {
255 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
256 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
260 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
261 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
262 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
266 // We need a SIB byte, so start by outputting the ModR/M byte first
267 assert(IndexReg.getReg() != X86::ESP &&
268 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
270 bool ForceDisp32 = false;
271 bool ForceDisp8 = false;
273 // If there is no base register, we emit the special case SIB byte with
274 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
275 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
277 } else if (!Disp.isImm()) {
278 // Emit the normal disp32 encoding.
279 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
281 } else if (Disp.getImm() == 0 &&
282 // Base reg can't be anything that ends up with '5' as the base
283 // reg, it is the magic [*] nomenclature that indicates no base.
284 BaseRegNo != N86::EBP) {
285 // Emit no displacement ModR/M byte
286 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
287 } else if (isDisp8(Disp.getImm())) {
288 // Emit the disp8 encoding.
289 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
290 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
292 // Emit the normal disp32 encoding.
293 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
296 // Calculate what the SS field value should be...
297 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
298 unsigned SS = SSTable[Scale.getImm()];
301 // Handle the SIB byte for the case where there is no base, see Intel
302 // Manual 2A, table 2-7. The displacement has already been output.
304 if (IndexReg.getReg())
305 IndexRegNo = GetX86RegNum(IndexReg);
306 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
308 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
311 if (IndexReg.getReg())
312 IndexRegNo = GetX86RegNum(IndexReg);
314 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
315 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
318 // Do we need to output a displacement?
320 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
321 else if (ForceDisp32 || Disp.getImm() != 0)
322 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
325 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
326 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
327 /// size, and 3) use of X86-64 extended registers.
328 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
329 const TargetInstrDesc &Desc) {
330 // Pseudo instructions never have a rex byte.
331 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
335 if (TSFlags & X86II::REX_W)
338 if (MI.getNumOperands() == 0) return REX;
340 unsigned NumOps = MI.getNumOperands();
341 // FIXME: MCInst should explicitize the two-addrness.
342 bool isTwoAddr = NumOps > 1 &&
343 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
345 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
346 unsigned i = isTwoAddr ? 1 : 0;
347 for (; i != NumOps; ++i) {
348 const MCOperand &MO = MI.getOperand(i);
349 if (!MO.isReg()) continue;
350 unsigned Reg = MO.getReg();
351 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
352 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
353 // that returns non-zero.
358 switch (TSFlags & X86II::FormMask) {
359 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
360 case X86II::MRMSrcReg:
361 if (MI.getOperand(0).isReg() &&
362 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
364 i = isTwoAddr ? 2 : 1;
365 for (; i != NumOps; ++i) {
366 const MCOperand &MO = MI.getOperand(i);
367 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
371 case X86II::MRMSrcMem: {
372 if (MI.getOperand(0).isReg() &&
373 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
376 i = isTwoAddr ? 2 : 1;
377 for (; i != NumOps; ++i) {
378 const MCOperand &MO = MI.getOperand(i);
380 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
387 case X86II::MRM0m: case X86II::MRM1m:
388 case X86II::MRM2m: case X86II::MRM3m:
389 case X86II::MRM4m: case X86II::MRM5m:
390 case X86II::MRM6m: case X86II::MRM7m:
391 case X86II::MRMDestMem: {
392 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
393 i = isTwoAddr ? 1 : 0;
394 if (NumOps > e && MI.getOperand(e).isReg() &&
395 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
398 for (; i != e; ++i) {
399 const MCOperand &MO = MI.getOperand(i);
401 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
409 if (MI.getOperand(0).isReg() &&
410 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
412 i = isTwoAddr ? 2 : 1;
413 for (unsigned e = NumOps; i != e; ++i) {
414 const MCOperand &MO = MI.getOperand(i);
415 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
423 void X86MCCodeEmitter::
424 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
425 SmallVectorImpl<MCFixup> &Fixups) const {
426 unsigned Opcode = MI.getOpcode();
427 const TargetInstrDesc &Desc = TII.get(Opcode);
428 unsigned TSFlags = Desc.TSFlags;
430 // Keep track of the current byte being emitted.
431 unsigned CurByte = 0;
433 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
434 // in order to provide diffability.
436 // Emit the lock opcode prefix as needed.
437 if (TSFlags & X86II::LOCK)
438 EmitByte(0xF0, CurByte, OS);
440 // Emit segment override opcode prefix as needed.
441 switch (TSFlags & X86II::SegOvrMask) {
442 default: assert(0 && "Invalid segment!");
443 case 0: break; // No segment override!
445 EmitByte(0x64, CurByte, OS);
448 EmitByte(0x65, CurByte, OS);
452 // Emit the repeat opcode prefix as needed.
453 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
454 EmitByte(0xF3, CurByte, OS);
456 // Emit the operand size opcode prefix as needed.
457 if (TSFlags & X86II::OpSize)
458 EmitByte(0x66, CurByte, OS);
460 // Emit the address size opcode prefix as needed.
461 if (TSFlags & X86II::AdSize)
462 EmitByte(0x67, CurByte, OS);
464 bool Need0FPrefix = false;
465 switch (TSFlags & X86II::Op0Mask) {
466 default: assert(0 && "Invalid prefix!");
467 case 0: break; // No prefix!
468 case X86II::REP: break; // already handled.
469 case X86II::TB: // Two-byte opcode prefix
470 case X86II::T8: // 0F 38
471 case X86II::TA: // 0F 3A
474 case X86II::TF: // F2 0F 38
475 EmitByte(0xF2, CurByte, OS);
478 case X86II::XS: // F3 0F
479 EmitByte(0xF3, CurByte, OS);
482 case X86II::XD: // F2 0F
483 EmitByte(0xF2, CurByte, OS);
486 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
487 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
488 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
489 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
490 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
491 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
492 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
493 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
496 // Handle REX prefix.
497 // FIXME: Can this come before F2 etc to simplify emission?
499 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
500 EmitByte(0x40 | REX, CurByte, OS);
503 // 0x0F escape code must be emitted just before the opcode.
505 EmitByte(0x0F, CurByte, OS);
507 // FIXME: Pull this up into previous switch if REX can be moved earlier.
508 switch (TSFlags & X86II::Op0Mask) {
509 case X86II::TF: // F2 0F 38
510 case X86II::T8: // 0F 38
511 EmitByte(0x38, CurByte, OS);
513 case X86II::TA: // 0F 3A
514 EmitByte(0x3A, CurByte, OS);
518 // If this is a two-address instruction, skip one of the register operands.
519 unsigned NumOps = Desc.getNumOperands();
521 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
523 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
524 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
527 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
528 switch (TSFlags & X86II::FormMask) {
529 case X86II::MRMInitReg:
530 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
531 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
532 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
533 case X86II::Pseudo: return; // Pseudo instructions encode to nothing.
535 EmitByte(BaseOpcode, CurByte, OS);
538 case X86II::AddRegFrm:
539 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
542 case X86II::MRMDestReg:
543 EmitByte(BaseOpcode, CurByte, OS);
544 EmitRegModRMByte(MI.getOperand(CurOp),
545 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
549 case X86II::MRMDestMem:
550 EmitByte(BaseOpcode, CurByte, OS);
551 EmitMemModRMByte(MI, CurOp,
552 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
553 TSFlags, CurByte, OS, Fixups);
554 CurOp += X86AddrNumOperands + 1;
557 case X86II::MRMSrcReg:
558 EmitByte(BaseOpcode, CurByte, OS);
559 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
564 case X86II::MRMSrcMem: {
565 EmitByte(BaseOpcode, CurByte, OS);
567 // FIXME: Maybe lea should have its own form? This is a horrible hack.
569 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
570 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
571 AddrOperands = X86AddrNumOperands - 1; // No segment register
573 AddrOperands = X86AddrNumOperands;
575 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
576 TSFlags, CurByte, OS, Fixups);
577 CurOp += AddrOperands + 1;
581 case X86II::MRM0r: case X86II::MRM1r:
582 case X86II::MRM2r: case X86II::MRM3r:
583 case X86II::MRM4r: case X86II::MRM5r:
584 case X86II::MRM6r: case X86II::MRM7r:
585 EmitByte(BaseOpcode, CurByte, OS);
586 EmitRegModRMByte(MI.getOperand(CurOp++),
587 (TSFlags & X86II::FormMask)-X86II::MRM0r,
590 case X86II::MRM0m: case X86II::MRM1m:
591 case X86II::MRM2m: case X86II::MRM3m:
592 case X86II::MRM4m: case X86II::MRM5m:
593 case X86II::MRM6m: case X86II::MRM7m:
594 EmitByte(BaseOpcode, CurByte, OS);
595 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
596 TSFlags, CurByte, OS, Fixups);
597 CurOp += X86AddrNumOperands;
600 EmitByte(BaseOpcode, CurByte, OS);
601 EmitByte(0xC1, CurByte, OS);
604 EmitByte(BaseOpcode, CurByte, OS);
605 EmitByte(0xC2, CurByte, OS);
608 EmitByte(BaseOpcode, CurByte, OS);
609 EmitByte(0xC3, CurByte, OS);
612 EmitByte(BaseOpcode, CurByte, OS);
613 EmitByte(0xC4, CurByte, OS);
616 EmitByte(BaseOpcode, CurByte, OS);
617 EmitByte(0xC8, CurByte, OS);
620 EmitByte(BaseOpcode, CurByte, OS);
621 EmitByte(0xC9, CurByte, OS);
624 EmitByte(BaseOpcode, CurByte, OS);
625 EmitByte(0xE8, CurByte, OS);
628 EmitByte(BaseOpcode, CurByte, OS);
629 EmitByte(0xF0, CurByte, OS);
632 EmitByte(BaseOpcode, CurByte, OS);
633 EmitByte(0xF8, CurByte, OS);
636 EmitByte(BaseOpcode, CurByte, OS);
637 EmitByte(0xF9, CurByte, OS);
641 // If there is a remaining operand, it must be a trailing immediate. Emit it
642 // according to the right size for the instruction.
644 EmitImmediate(MI.getOperand(CurOp++),
645 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
646 CurByte, OS, Fixups);
650 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
651 errs() << "Cannot encode all operands of: ";